FAN6921ML

FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Current Mode PWM Controller June 2010 FAN6921ML Integrated Critical Mode PFC/Quasi-Resonant Current Mode PWM Controller Features Integrated PFC and Flyback Controller Critical Mode PFC Controller Zero-Current Detection for PFC Stage Quasi-Resonant Operation for PWM Stage Internal Minimum toff 8µs for QR PWM Stage Internal 10ms Soft-Start for PWM Brownout Protection H/L Line Over-Power Compensation (OPC) Latched Protection (FB Pin) − − − Over-Power/ Overload Protection Short-Circuit Protection Open-Loop Protection Description The highly integrated FAN6921ML combines a Power Factor Correction (PFC) controller and a QuasiResonant PWM controller. Integration provides costeffect design and allows for fewer external components. For PFC, FAN6921ML uses a controlled on-time technique to provide a regulated DC output voltage and to perform natural power factor correction. With an innovative THD optimizer, FAN6921ML can reduce input current distortion at zero-crossing duration to improve THD performance. For PWM, FAN6921ML enhances the power system performance through valley detection, green-mode operation, and high / low line over power compensation. FAN6921ML provides: secondary-side open-loop and over-current protection, external latch triggering, adjustable over-temperature protection by RT pin and external NTC resistor, internal over-temperature shutdown, VDD pin OVP, and DET pin over-voltage for output OVP, and brownin/out for AC input voltage under-voltage protection (UVP). The FAN6921ML controller is available in a 16-pin small outline package (SOP). Externally Latch Triggering (RT Pin) Adjustable Over-Temperature Latched (RT Pin) VDD Pin & Output Voltage OVP (Latched) Internal Temperature Shutdown (140°C) Applications AC/DC NB Adapters Open-Frame SMPS Battery Charger Ordering Information Part Number FAN6921MLMY OLP Mode Latch Operating Temperature Range -40°C to +105°C Package 16-Pin Small Outline Package (SOP) Packing Method Tape & Reel © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller Application Diagram Figure 1. Typical Application © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 2 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller Internal Block Diagram COMP HV VDD 2 RANGE 2.65V 2.75V Multi-Vector Amp. 2.75V 2.9V 2.3V 0.45V RANGE 16 OVP IHV 27.5V UVP OVP 7 Internal Bias Two Steps UVLO 18V/10V/7.5V DRV 15 NC Latched Debounce 70µs S Latched Brownout SET Q 15.5V 6 OPFC INV 3 2.5V THD Optimizer PFC Current Limit R CLR Q Sawtooth Generator /tON-MAX-PFC Disable Function 0.2V Debounce 550ms / 150µs Timer 50ms VC & PFC ON/OFF & Multi Vector Amp. ON/OFF Restarter PFC Zero Current Detector Inhibit Timer 2.1V/1.75V CSPFC 4 0.6V Blanking Circuit VCTL-PFC-ON/OFF 4.2V 0.7V IZCD 14 10V ZCD FB 11 Soft-Start 9.5ms 2R 2.5ms 32.5µs R Starter VB FB OLP DRV S Blanking Circuit PWM Current Limit IDET SET Q 17.5V 8 OPWM CSPWM 5 R CLR Q Over Power Compensation DET pin OVP VDD pin OVP Internal OTP (RT Pin) Prog. OTP Brownout (RT Pin) Externally Triggering Protection Output Short Circuit (FB Latched Pin) Output Open-Loop (FB Pin) Output Over Power/ Overload (FB Pin) VC Startup VB & clamp VCOMP to 1.6V Debounce 100ms Brownout comparator Debounce 100ms Lathed Protection tOFF-MIN (8us/37µs/2.5ms) IDET Valley Detector 1st Valley tOFF-MIN +9µs Latched tOFF Blanking (4µs) S/H VDET Latched 2.5V DET OVP IRT 1 RANGE Debounce Time 1.2V 0.8V VINV VINV 1V/1.2V 100us 10ms 2.35V/2.15V DET 10 5V IDET 100uA 0.3V 0.8V Internal OTP Latched 0.5V Prog. OTP / Externally Triggering 9 GND 12 RT 13 VIN PFC RANGE Control Figure 2. Functional Block Diagram © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 3 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller Marking Information 16 ZXYTT FAN6921FO TPM 1 - Fairchild Logo Z - Plant Code X - Year Code (1 Digit for SOP, 2 Digits for DIP) Y - Week Code (1 Digit for SOP, 2 Digits for DIP) TT – DIe-Run Code F - Frequency (M=Low, H=High Level) O - OLP Mode (L=Latch, R=Recovery) T - Package Type (N=DIP, M=SOP) P – Y=Green Package M - Manufacture Flow Code Figure 3. Marking Diagram Pin Configuration Figure 4. Pin Configuration Pin Definitions Pin # 1 Name RANGE Description RANGE pin’s impedance changes according to VIN pin voltage level. When the input voltage detected by the VIN pin is lower than a threshold voltage, it sets to high impedance; whereas it sets to low impedance if input voltage is high level. Output pin of the error amplifier. It is a transconductance type error amplifier for PFC output voltage feedback. Proprietary multi-vector current is built-in to this amplifier; therefore, the compensation for the PFC voltage feedback loop allows a simple compensation circuit between this pin and GND. Inverting input of the error amplifier. This pin is used to receive PFC voltage level by a voltage divider and provides PFC output over- and under-voltage protections. Input to the PFC over-current protection comparator that provides cycle-by-cycle current limiting protection. When the sensed voltage across the PFC current-sensing resistor reaches the internal threshold (0.6 typical), the PFC switch is turned off to activate cycle-by-cycle current limiting. 2 COMP 3 4 INV CSPFC © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 4 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller Pin Definitions Pin # Name Description Input to the comparator of the PWM over-current protection and performs PWM current-mode control with FB pin voltage. A resistor is used to sense the switching current of the PWM switch CSPWM and the sensing voltage is applied to the CSPWM pin for the cycle-by-cycle current limit, currentmode control, and high / low line over-power compensation according to DET pin source current during PWM on time. OPFC VDD OPWM GND Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage is 15.5V. Power supply. The threshold voltages for startup and turn-off are 18V and 7.5V, respectively. The startup current is less than 30µA and the operating current is lower than 10mA. Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped gate output voltage is 17.5V. The power ground and signal ground. This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for the following purposes: Producing an offset voltage to compensate the threshold voltage of PWM current limit for providing over-power compensation. The offset is generated in accordance with the input voltage when PWM switch is on. 10 DET Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley voltage switching and minimize the switching loss on the PWM switch. Providing output over-voltage protection. A voltage comparator is built-in to the DET pin. The DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output OVP and this flat voltage is higher than 2.5V, the controller enters latch mode and stops all PFC and PWM switching operation. Feedback voltage pin. This pin is used to receive the output voltage level signal to determine PWM gate duty for regulating output voltage. The FB pin voltage can also activate open-loop, overload, or output-short-circuit protection if the FB pin voltage is higher than a threshold of around 4.2V for more than 50ms.The input impedance of this pin is a 5kΩ equivalent resistance. A 1/3 attenuator is connected between the FB pin and the input of the CSPWM/FB comparator. Adjustable over-temperature protection and external latch triggering. A constant current flows out of the RT pin. When RT pin voltage is lower than 0.8V (typical), latch mode protection is activated and stops all PFC and PWM switching operation until the AC plug is removed. Line-voltage detection for brownin/out protections. This pin can receive the AC input voltage level through a voltage divider. The voltage level of the VIN pin is not only used to control RANGE pin’s status, but it can also perform brownin/out protection for AC input voltage UVP. Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges to zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching cycle. When the ZCD pin voltage is pulled to under 0.2V (typical), it disables the PFC stage and the controller stops PFC switching. This can be realized with an external circuit if disabling the PFC stage is desired. No connection High-voltage startup. HV pin is connected to the AC line voltage through a resistor (100kΩ typical) for providing a high-charging current to VDD capacitor. 5 6 7 8 9 11 FB 12 RT 13 VIN 14 ZCD 15 16 NC HV © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 5 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VHV VH VL VZCD PD ΘJA ΘJC TJ TSTG TL ESD DC Supply Voltage HV OPFC, OPWM Parameter Min. Max. 30 500 Unit V V V V V mW °C/W °C/W °C °C °C V -0.3 -0.3 -0.3 25.0 7.0 12.0 800 104 41 Others (INV, COMP, CSPFC, DET, FB, CSPWM, RT) Input Voltage to ZCD Pin Power Dissipation Thermal Resistance; Junction-to-Air Thermal Resistance; Junction-to-Case Operating Junction Temperature Storage Temperature Range Lead Temperature; Soldering 10 Seconds Human Body Model, JESD22-A114 (All Pins Except HV Pin) (3) (3) -40 -55 +150 +150 +260 4500 1250 Charged Device Model, JESD22-C101 (All Pins Except HV Pin) Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to the GND pin. 3. All pins including HV pin: CDM=750V, HBM=1000V. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature Min. -40 Max. +105 Unit °C © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 6 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller Electrical Characteristics VDD=15V, TA=-40~105°C (TA=TJ), unless otherwise specified. Symbol VDD Section VOP VDD-ON VDD-PWM-OFF VDD-OFF IDD-ST Parameter Continuously Operating Voltage Turn-On Threshold Voltage PWM Off Threshold Voltage Turn-Off Threshold Voltage Startup Current Conditions Min. Typ. Max. 25 Units V V V V µA 16.5 9 6.5 VDD=VDD-ON - 0.16V, Gate Open VDD=15V, OPFC; OPWM=100KHz; CL-PFC, CL-PWM=2nF VDD=15V, OPWM=450Hz, CL-PWM=2nF 70 26.5 100 VDD=7.5V 18.0 10 7.5 10 19.5 11 8.5 20 IDD-OP Operating Current 10 mA IDD-GREEN Green Mode Operating Supply Current (Average) 5.5 mA IDD-PWM-OFF VDD-OVP tVDD-OVP IDD-LATCH Operating Current at PWM-OFF VDD=VDD-PWM-OFF - 0.5V Phase VDD Over-Voltage Protection (Latch-Off) VDD OVP Debounce Time VDD OVP Latch-up Holding Current 120 27.5 150 120 170 28.5 200 µA V µs µA HV Startup Current Source Section VHV-MIN Minimum Startup Voltage on HV Pin VAC=90V (VDC=120V), VDD=0V HV=500V, VDD= VDD-OFF +1V 1.2 1.0 50 V mA µA IHV Supply Current from Pin HV VIN and RANGE Section VVIN-UVP VVIN-RE-UVP tVIN-UVP VVIN-RANGE-H VVIN-RANGE-L tRANGE VRANGE-OL tON-MAX-PFC The Threshold Voltage for AC Input Under-Voltage Protection Under-Voltage Protection Reset Voltage (for Startup) Under-Voltage Protection Debounce Time (No Need at Startup/Hiccup Mode) High VVIN Threshold for RANGE RANGE=Ground Comparator Low VVIN Threshold for RANGE RANGE=Open Comparator Range-Enable/Disable Debounce Time Output Low Voltage of RANGE Pin PFC Maximum On Time IO=1mA 22 25 0.95 VVIN-UVP +0.15V 70 2.30 2.10 70 1.00 VVIN-UVP +0.2V 100 2.35 2.15 100 1.05 VVIN-UVP +0.25V 130 2.40 2.20 130 0.5 28 V V ms V V ms V µs Continued on the following page… © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 7 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller Electrical Characteristics (Continued) VDD=15V, TA=-40~105°C (TA=TJ), unless otherwise specified. Symbol PFC Stage Parameter Conditions Min. Typ. Max. Units Voltage Error Amplifier Section Gm VREF VINV-H Transconductance (4) 100 2.465 2.70 2.60 1.06 1.04 2.25 RANGE=Open RANGE=Ground 50 0.35 50 0.7 1.15 0.7 4.8 1.15 15 0.50 20 20 125 2.500 2.75 2.65 150 2.535 2.80 2.70 1.14 1.08 µmho V V V Feedback Comparator Reference Voltage Clamp High Feedback Voltage RANGE=Open RANGE=Ground VINVH / VREF, RANGE=Open VINVH / VREF, RANGE=Ground VRATIO Clamp High Output Voltage Ratio VINV-L VINV-OVP tINV-OVP VINV-UVP tINV-UVP VINV-FB-Latch VINV-BO VINV-BO2 VCOMP VOZ Clamp Low Feedback Voltage Over Voltage Protection for INV Input 2.30 2.90 2.75 70 0.45 70 0.8 1.20 0.8 2.35 2.95 2.80 90 0.55 90 0.9 1.25 0.9 6.0 V V V µs V µs V V V V V µA mA µA µA Over-Voltage Protection Debounce Time Under-Voltage Protection for INV Input Under Voltage Protection Debounce Time INV Threshold Voltage for Blocking FB latch PWM and PFC Off Threshold for Brownout Protection PWM Off Threshold Voltage for Brownout Protection, PFC Off Comparator Output High Voltage Zero Duty Cycle Voltage on COMP Pin Comparator Output Source Current VINV=2.3V, VCOMP=1.5 VINV=1.5V RANGE=Open, VINV=2.75V, VCOMP=5 RANGE=Ground, VINV=2.65V, VCOMP=5 1.25 25 0.75 30 30 1.35 35 1.00 40 40 ICOMP Comparator Output Sink Current PFC Current Sense Section VCSPFC tPD tBNK AV Threshold Voltage for Peak Current Cycle-by-Cycle Limit Propagation Delay Leading-Edge Blanking Time CSPFC Compensation Ratio for THD 110 0.90 VCOMP=5V 0.60 110 180 0.95 200 250 1.00 V ns ns Continued on the following page… © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 8 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller Electrical Characteristics (Continued) VDD=15V, TA=-40℃~105℃ (TA=TJ), unless otherwise specified. Symbol PFC Output Section VZ VOL VOH tR tF Parameter PFC Gate Output Clamping Voltage PFC Gate Output Voltage Low PFC Gate Output Voltage High PFC Gate Output Rising Time PFC Gate Output Falling Time Conditions Min. Typ. Max. Units VDD= 25V VDD=15V, IO=100mA VDD=15V, IO=100mA VDD=12V, CL=3nF, 20~80% VDD=12V, CL=3nF, 80~20% 14.0 15.5 17.0 1.5 V V V 8 30 30 65 50 100 70 ns ns PFC Zero Current Detection Section VZCD VZCD-HYST VZCD-HIGH VZCD-LOW VZCD-SSC tDELAY tRESTART-PFC tINHIB VZCD-DIS tZCD-DIS Input Threshold Voltage Rising Edge Threshold Voltage Hysteresis Upper Clamp Voltage Lower Clamp Voltage Starting Source Current Threshold Voltage Maximum Delay from ZCD to Output Turn-On Restart Time Inhibit Time (Maximum Switching Frequency Limit) VCOMP=5V VZCD Increasing VZCD Decreasing IZCD=3mA IZCD=-1.5mA IZCD=5µA VCOMP=5V, fS=60KHz 1.9 0.25 8 0.55 0.8 100 300 1.5 150 100 500 2.5 200 150 2.1 0.35 10 0.70 0.9 0.85 1.0 200 700 3.5 250 200 2.3 0.45 V V V V V ns µs µs mV µs PFC Enable/Disable Function Threshold Voltage PFC Enable/Disable Function Debounce Time VZCD=100mV PWM Stage Feedback Input Section AV ZFB IOZ Input-Voltage to Current Sense (4) Attenuation Input Impedance Bias Current Zero Duty-Cycle Input Voltage (4) AV= VCS / VFB, 0 VFB-OLP 1.70 1.65 1.95 1.75 400 30 1.75 1.70 2.00 1.80 500 34 150 1.80 V 1.75 2.05 V 1.85 600 38 ms µs µs 3.0 39.5 ms µs VCTL-PFC-OFF VCTL-PFC-ON tPFC-OFF tINHIB-PFC-OFF tPFC-ON tSTARTER-PWM Start Timer (Time-Out Timer) 2.0 25.5 2.5 32.5 Continued on the following page… © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 10 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller Electrical Characteristics (Continued) VDD=15V, TA=-40℃~105℃ (TA=TJ), unless otherwise specified. Symbol PWM Output Section VCLAMP VOL VOH tR tF Parameter PWM Gate Output Clamping Voltage PWM Gate Output Voltage Low PWM Gate Output Voltage High PWM Gate Output Rising Time PWM Gate Output Falling Time Conditions Min. Typ. Max. Units VDD= 25V VDD= 15V, Io=100mA VDD= 15V, Io=100mA CL=3nF, VDD=12V, 20~80% CL=3nF, VDD=12V, 20~80% 16.0 17.5 19.0 1.5 V V V 8 80 40 110 70 ns ns Current Sense Section tPD Delay to Output IDET < 75µA, TA=25°C VLIMIT The Limit Voltage on CSPWM Pin for Over Power Compensation IDET=185µA, TA=25°C IDET=350µA, TA=25°C IDET=550µA, TA=25°C VSLOPE tON-BNK VCS-FLOATING tCS-H Slope Compensation (4) 150 0.81 0.69 0.55 0.37 0.25 0.05 0.84 0.72 0.58 0.40 0.30 0.10 300 CSPWM Pin Floating 4.5 150 200 0.87 0.75 0.61 0.43 0.35 0.15 ns V tON=45µs, RANGE=Open tON=0µs V Leading-Edge Blanking Time CSPWM Pin Floating VCSPWM Clamped High Voltage ns 5 V µs Delay Once CSPWM Pin Floating CSPWM Pin Floating Internal Threshold Temperature (4) for OTP Hysteresis Temperature for (4) Internal OTP Internal Source Current of RT Pin Latch-Mode Triggering Voltage Latch-Mode Release Voltage Threshold Voltage for Two-level Debounce Time Debounce Time for OTP Debounce Time for Externally Triggering VRT VN Figure 20. PWM Minimum Off Time for VFB=VG © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 13 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller Typical Performance Characteristics (Continued) These characteristic graphs are normalized at TA=25°C. 1.0 0.9 VDET-LOW(V) 0.8 0.7 0.6 0.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature(°C) 2.60 2.55 V DET-OVP(V) 2.50 2.45 2.40 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature(°C) Figure 21. Lower Clamp Voltage of DET Pin Figure 22. Reference Voltage for Output Over-Voltage Protection of DET Pin 0.90 110.0 105.0 0.85 V RT-LATCH(V) -40 -25 -10 5 20 35 50 65 Temperature(°C) 80 95 110 125 IRT(μA) 100.0 0.80 95.0 0.75 90.0 0.70 -40 -25 -10 5 20 35 50 65 Temperature(°C) 80 95 110 125 Figure 23. Internal Source Current of RT Pin Figure 24. Over-Temperature Protection Threshold Voltage of RT Pin © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 14 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller Functional Description PFC Stage Multi-Vector Error Amplifier and THD Optimizer For better dynamic performance, faster transient response, and precise clamping on PFC output, FAN6921ML uses a transconductance type amplifier with proprietary innovative multi-vector error amplifier (US Patent 6,900,623). The schematic diagram of this amplifier is shown in Figure 25. The PFC output voltage is detected from the INV pin by an external resistor divider circuit that consists of R1 and R2. When PFC output variation voltage reaches 6% over or under the reference voltage of 2.5V, the multi-vector error amplifier adjusts its output sink or source current to increase the loop response to simplify the compensated circuit. + ∑ + Figure 26. Multi-Vector Error Amplifier with THD Optimizer Figure 25. Multi-Vector Error Amplifier The feedback voltage signal on the INV pin is compared with reference voltage 2.5V, which makes the error amplifier source or sink current to charge or discharge its output capacitor CCOMP. The COMP voltage is compared with the internally generated sawtooth waveform to determine the on time of PFC gate. Normally, with lower feedback loop bandwidth, the variation of the PFC gate on time should be very small and almost constant within one input AC cycle. However, the power factor correction circuit operating at light-load condition has a defect, zero crossing distortion, that distorts input current and makes the system’s Total Harmonic Distortion (THD) worse. To improve the result of THD at light-load condition, especially at high input voltage, an innovative THD optimizer (US Patent 7,116,090) is inserted by sampling the voltage across the current-sense resistor. This sampling voltage on current-sense resistor is added into the sawtooth waveform to modulate the on time of PFC gate, so it is not constant on time within a half AC cycle. The method of operation between THD optimizer and PWM is shown in Figure 26. After THD optimizer processes, around the valley of AC input voltage, the compensated on time becomes wider than the original. The PFC on time, which is around the peak voltage, is narrowed by the THD optimizer. The timing sequences of the PFC MOS and the shape of the inductor current are shown in Figure 27. Figure 28 shows the difference between calculated fixed on time and fixed on time with THD optimizer during a half AC cycle. © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 Figure 27. Operation Waveforms of Fixed On Time with and without THD Optimizer Current (A) Figure 28. Calculated Waveforms of Fixed On Time with and without THD Optimizer During a Half AC Cycle www.fairchildsemi.com 15 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller RANGE Pin A built-in low voltage MOSFET can be turned on or off according to VVIN voltage level. The drain pin of this internal MOSFET is connected to the RANGE pin. Figure 29 shows the status curve of VVIN voltage level and RANGE impedance (open or ground). VZCD 10V 2.1V 1.75V VDS PFCVO t VIN,MAX Figure 29. Hysteresis Behavior between RANGE Pin and VIN Pin Voltage Zero Current Detection (ZCD Pin) Figure 30 shows the internal block of zero-current detection. The detection function is performed by sensing the information on an auxiliary winding of the PFC inductor. Referring to Figure 31, when PFC MOS is off, the stored energy of the PFC inductor starts to release to the output load. Then the drain voltage of PFC MOS starts to decrease since the PFC inductor resonates with parasitic capacitance. Once the ZCD pin voltage is lower than the triggering voltage (1.75V typical), the PFC gate signal is sent again to start a new switching cycle. If PFC operation needs to be shut down due to abnormal conditions, pull the ZCD pin LOW, with voltage under 0.2V (typical), to activate the PFC disable function to stop PFC switching operation. For preventing excessive high switching frequency at light load, a built-in inhibit timer is used to limit the minimum tOFF time. Even if the ZCD signal has been detected, the PFC gate signal is not sent during the inhibit time (2.5µs typical). PFC Gate Inhibit Time t t Figure 31. Operation Waveforms of PFC Zero-Current Detection Protection for PFC Stage PFC Output Voltage UVP and OVP (INV Pin) FAN6921ML provides several kinds of protection for the PFC stage. PFC output over- and under-voltage are essential for PFC stage. Both are detected and determined by INV pin voltage, as shown in Figure 32. When INV pin voltage is over 2.75V or under 0.45V, due to overshoot or abnormal conditions, and lasts for a debounce time around 70µs; the OVP or UVP circuit is activated to stop PFC switching operation immediately. The INV pin is not only used to receive and regulate PFC output voltage, but can also perform PFC output OVP/ UVP protection. For failure-mode test, this pin can shut down PFC switching if pin floating occurs. PFC VO Driver D eboun ce Time VREF (2.5V) COMP 2 CCOMP VCOMP V oltage R1 INV CO 1 D etector Error R2 Amplifier OVP = (VINV ≥ 2.75V) UVP = (VINV ≤ 0.45V) FAN6921 Figure 30. Internal Block of the Zero-Current Detection © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 Figure 32. Internal Block of PFC Over- and UnderVoltage Protection www.fairchildsemi.com 16 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller PFC Peak Current Limiting (CSPFC pin) During PFC stage switching operation, the PFC switch current is detected by a current-sense resistor on the CSPFC pin and the detected voltage on this resistor is delivered to an input terminal of a comparator and compared with a threshold voltage 0.6V (typical). Once the CSPFC pin voltage is higher than the threshold voltage, PFC gate is turned off immediately. The PFC peak switching current is adjustable by the current-sense resistor. Figure 33 shows the measured waveform of PFC gate and CSPFC pin voltage. PFC MOS Current Limit CSPFC OPFC Figure 33. Cycle-by-Cycle Current Limiting Brownin/out Protection (VIN Pin) W ith AC voltage detection, FAN6921ML can perform brownin/out protection (AC voltage UVP). Figure 34 shows the key operation waveforms. The VIN pin is used to detect AC input voltage level and is connected to AC input by a resistor divider (refer to Figure 1); therefore, the VVIN voltage is proportional to the AC input voltage. When the AC voltage drops; and VVIN voltage is lower than 1V for 100ms, the UVP protection is activated and the COMP pin voltage is clamped to around 1.6V. Because PFC gate duty is determined by comparing the sawtooth waveform and COMP pin voltage, lower COMP voltage results in narrow PFC on time, so that the energy converged is limited and the PFC output voltage decreases. When INV pin voltage is lower than 1.2V, FAN6921ML stops all PFC and PWM switching operation immediately until VDD voltage drops to turn-off voltage then rises to turn-on voltage again (UVLO). When the brownout protection is activated, all switching operation is turned off, the VDD voltage enters hiccup mode up and down continuously. Until VVIN voltage is higher than 1.2V (typical) and VDD reaches turn-on voltage again, the PWM and PFC gate is sent out. The measured waveforms of brownin/out protection are shown in Figure 35. Figure 34. Operation Waveforms of Brownin/out Protection VDD VDD Hiccup Mode Brownout AC Input OPWM OPFC Brownin AC Input Figure 35. Measured Waveform of Brownin/out Protection (Adapter Application) © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 17 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller PWM Stage HV Startup and Operating Current (HV Pin) The HV pin is connected to the AC line through a resistor (refer to Figure 1). With a built-in high-voltage startup circuit, when AC voltage is applied to power system, FAN6921ML provides a high current to charge external VDD capacitor to accelerate controller’s startup time and build up normal rated output voltage within three seconds. To save power consumption, after VDD voltage exceeds turn-on voltage and enters normal operation; this high voltage startup circuit is shut down to avoid power loss from startup resistor. Figure 36 shows the characteristic curve of VDD voltage and operating current IDD. When VDD voltage is lower than VDD-PWM-OFF, FAN6921ML stops all switching operation and turns off some unnecessary internal circuit to reduce operating current. By doing so, the period from VDD-PWM-OFF to VDD-OFF can be extended and the hiccup mode frequency can be decreased to reduce the input power in case of output short circuit. Figure 37 shows the typical waveforms of VDD voltage and gate signal at hiccup mode operation. is detected, FAN6921ML outputs PWM gate signal to turn on the switch and begin a new switching cycle. With green mode and valley detection, at light load condition; power system can perform extended valley switching at DCM operation and further reduce switching loss for better conversion efficiency. The FB pin voltage versus tOFF-MIN time characteristic curve is shown in Figure 38. As Figure 38 shows, FAN6921ML can extend tOFF time up to 2.5ms, which is around 400Hz switching frequency. Referring to Figure 1 and Figure 2, FB pin voltage is not only used to receive secondary feedback signal to determine gate on time, but also determines PFC stage on or off status. At no-load or light-load conditions, if PFC stage is set to be off; that can reduce power consumption from PFC stage switching device and increase conversion efficiency. When output loading is decreased, the FB pin voltage becomes lower and, therefore, the FAN6921ML can detect the output loading level according to the FB pin voltage to control the on / off status of the PFC part. Figure 36. VDD vs. IDD-OP Characteristic Curve Figure 38. VFB Voltage vs. tOFF-MIN Time Characteristic Curve Valley Detection (DET Pin) When FAN6921ML operates in green mode, tOFF-MIN is determined by the green mode circuit according to FB pin voltage level. After tOFF-MIN, the internal valleydetection circuit is activated. During the off time of the PWM switch, when transformer inductor current discharges to zero; the transformer inductor and parasitic capacitor of PWM switch start to resonate concurrently. When the drain voltage on the PWM switch falls, the voltage across on auxiliary winding VAUX also decreases since auxiliary winding is coupled to primary winding. Once the VAUX voltage resonates and falls to negative, VDET voltage is clamped by the DET pin (refer to Figure 39) and FAN6921ML is forced to flow out a current IDET. FAN6921ML reflects and compares this IDET current. If this source current rises to a threshold current, PWM gate signal is sent out after a fixed delay time (200ns typical). Figure 37. Typical Waveform of VDD Voltage and Gate Signal in Hiccup Mode Operation Green-Mode Operation and PFC-ON / OFF Control (FB Pin) Green mode is used to further reduce power loss in the system (e.g. switching loss). It uses an off-time modulation technique to regulate switching frequency according to FB pin voltage. When output loading is decreased, FB voltage becomes lower due to secondary feedback movement and the tOFF-MIN is extended. After tOFF-MIN (determined by FB voltage), the internal valley detection circuit is activated to detect the valley on the drain voltage of the PWM switch. When the valley signal © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 18 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller As the input voltage increases, the reflected voltage on the auxiliary winding, VAUX, becomes higher (as well as the current IDET) and the controller regulates the VLIMIT to a lower level. The RDET resistor is connected from auxiliary winding to the DET pin. Engineers can adjust this RDET resistor to get proper VLIMIT voltage to fit power system needs. The characteristic curve of IDET current vs. VLIMIT voltage on CSPWM pin is shown in Figure 42. Figure 39. Valley Detection I DET = ⎡VIN × ( N A NP ) ⎤ RDET ⎣ ⎦ (1) where VIN is input voltage; NA is turn number of auxiliary winding; and NP is turn number of primary winding. Figure 40. Measured Waveform of Valley Detection High / Low Line Over-Power Compensation (DET Pin) Generally, when the power switch turns off, there is a delay from gate signal falling edge to power switch off. This delay is produced by an internal propagation delay of the controller and the turn-off delay of the PWM switch due to gate resistor and gate-source capacitor CISS of PWM switch. At different AC input voltage, this delay time produces different maximum output power under the same PWM current limit level. Higher input voltage generates higher maximum output power since applied voltage on primary winding is higher and causes higher rising slope inductor current. It results in higher peak inductor current at the same delay. Furthermore, under the same output wattage, the peak switching current at high line is lower than at low line. Therefore, to make the maximum output power close at different input voltages, the controller needs to regulate VLIMIT of the CSPWM pin to control the PWM switch current. Referring to Figure 41, during the on time of the PWM switch, the input voltage is applied to primary winding and the voltage across on auxiliary winding, VAUX, is proportional to primary winding voltage. As the input voltage increases, the reflected voltage on auxiliary winding VAUX rises as well. FAN6921ML also clamps the DET pin voltage and flows out a current IDET. Since the current, IDET, is in accordance with VAUX, FAN6921ML can depend on this current IDET during PWM on time to regulate the current limit level of the PWM switch to perform high / low line over-power compensation. Figure 41. Relationship between VAUX and VIN Figure 42. IDET Current vs. VLIMIT Voltage Characteristic Curve Leading-Edge Blanking (LEB) When the PFC or PWM switches are turned on, a voltage spike is induced on the current-sense resistor due to the reciprocal effect by reverse recovery energy of the output diode and COSS of power MOSFET. To prevent this spike, a leading-edge blanking time is builtin and a small RC filter is recommended between the CSPWM pin and GND (e.g. 100Ω, 470pF). © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 19 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller Protection for PWM Stage VDD Pin Over-Voltage Protection (OVP) VDD over-voltage protection is used to prevent device damage once VDD voltage is higher than device stress rating voltage. In case of VDD OVP, the controller stops all switching operation immediately and enters latch-off mode until the AC plug is removed. Adjustable Over-Temperature Protection and Externally Latch Triggering (RT Pin) Figure 43 is a typical application circuit with an internal block of RT pin. As shown, a constant current IRT flows out from the RT pin, so the voltage VRT on RT pin can be obtained as IRT current multiplied by the resistor, which consists of NTC resistor and RA resistor. If the RT pin voltage is lower than 0.8V and lasts for a debounce time, latch mode is activated and stops all PFC and PWM switching. The RT pin is usually used to achieve over-temperature protection with a NTC resistor and provides external latch triggering for additional protection. Engineers can use an external triggering circuit (e.g. transistor) to pull low the RT pin and activate controller latch mode. Generally, the external latch triggering needs to activate rapidly since it is usually used to protect power system from abnormal conditions. Therefore, the protection debounce time of the RT pin is set to around 100µs once RT pin voltage is lower than 0.5V. For over-temperature protection, because the temperature would not change immediately; the RT pin voltage is reduced slowly as well. The debounce time for adjustable OTP should not need a fast reaction. To prevent improper latch triggering on the RT pin due to exacting test conditions (e.g. lightning test); when the RT pin triggering voltage is higher than 0.5V, the protection debounce time is set to around 10ms. To avoid improper triggering on the RT pin, it is recommended to add a small value capacitor (e.g. 1000pF) paralleled with NTC and RA resistor. FAN6921 Adjustable OverTemperature protection & External Latch triggering I RT =100µA 12 NTC R RT RT 0.8V 0.5V Output Over-Voltage Protection (DET Pin) Referring to Figure 44, during the discharge time of PWM transformer inductor; the voltage across on auxiliary winding is reflected from secondary winding and therefore the flat voltage on the DET pin is proportional to the output voltage. FAN6921ML can sample this flat voltage level after a tOFF blanking time to perform output over-voltage protection. This tOFF blanking time is used to ignore the voltage ringing from leakage inductance of PWM transformer. The sampled flat voltage level is compared with internal threshold voltage 2.5V and, once the protection is activated, FAN6921ML enters latch mode. The controller can protect rapidly by this kind of cycleby-cycle sampling method in the case of output over voltage. The protection voltage level can be determined by the ratio of external resistor divider RA and RDET. The flat voltage on DET pin can be expressed by the following equation: VDET = ( N A N S ) ×VO × PWM Gate RA RDET + RA (2) VAUX VO ⋅ NA NS t t PFC _ VO ⋅ VO ⋅ NA NP VDET NA RA ⋅ N S R DET + R A sampling here Deboun ce time 110µs 10ms L atched tOFF blanking 0.3V t Figure 43. Adjustable Over-Temperature Protection Figure 44. Operation Waveform of Output Over-Voltage Detection © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 20 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller Open-Loop, Short-Circuit, and Overload Protection (FB Pin) Referring to Figure 45, outside of FAN6921ML; the FB pin is connected to the collector of transistor of an optocoupler. Inside of FAN6921ML, the FB pin is connected to an internal voltage bias through a resistor of ~5kΩ. As the output loading is increased, the output voltage is decreased and the sink current of transistor of optocoupler on primary side is reduced. So the FB pin voltage is increased by internal voltage bias. In the case of an open loop, output short circuit, or overload conditions; this sink current is further reduced and the FB pin voltage is pulled to high level by internal bias voltage. When the FB pin voltage is higher than 4.2V for 50ms, the FB pin protection is activated. Under-Voltage Lockout (UVLO, VDD Pin) Referring to Figure 36 and Figure 37, the turn-on and turn-off VDD threshold voltages are fixed at 18V and 10V, respectively. During startup, the hold-up capacitor (VDD capacitor) is charged by the HV startup current until VDD voltage reaches the turn-on voltage. Before the output voltage rises to rated voltage and delivers energy to the VDD capacitor from auxiliary winding, this hold-up capacitor has to sustain the VDD voltage energy for operation. When VDD voltage reaches turn-on voltage, FAN6921ML starts all switching operation if no protection is triggered before VDD voltage drops to turnoff voltage VDD-PWM-OFF. Figure 45. FB Pin Open-Loop, Short Circuit, and Overload Protections © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 21 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Flyback PWM Controller Physical Dimensions Figure 46. 16-Pin Small Outline Package (SOIC) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 22 FAN6921ML — Integrated Critical Mode PFC / Quasi-Resonant Current Mode PWM Controller © 2010 Fairchild Semiconductor Corporation FAN6921ML • Rev. 1.0.1 www.fairchildsemi.com 23