FAN6961SZ

FAN6961 —Boundary Mode PFC Controller January 2009 FAN6961 Boundary Mode PFC Controller Features Boundary Mode PFC Controller Low Input Current THD Controlled On-Time PWM Zero-Current Detection Cycle-by-Cycle Current Limiting Leading-Edge Blanking instead of RC Filtering Low Start-up Current: 10µA Typical Low Operating Current: 4.5mA Typical Feedback Open-Loop Protection Programmable Maximum On-Time (MOT) Output Over-Voltage Clamping Protection Clamped Gate Output Voltage 16.5V Description The FAN6961 is an 8-pin, boundary-mode, PFC controller IC intended for controlling PFC preregulators. The FAN6961 provides a controlled on-time to regulate the output DC voltage and achieve natural power factor correction. The maximum on-time of the external switch is programmable to ensure safe operation during AC brownouts. An innovative multivector error amplifier is built in to provide rapid transient response and precise output voltage clamping. A builtin circuit disables the controller if the output feedback loop is opened. The start-up current is lower than 20µA and the operating current has been reduced to under 6mA. The supply voltage can be up to 25V, maximizing application flexibility. Applications Electric Lamp Ballasts AC-DC Switching Mode Power Converter Open Frame Power Supplies and Power Adapters Flyback Power Converters with ZCS / ZVS Ordering Information Part Number FAN6961SZ FAN6961DZ FAN6961SY Operating Temperature Range -40°C to +125°C -40°C to +125°C -40°C to +125°C Package 8-Pin, Small Outline Package (SOP) 8-Pin, Dual In-line Package (DIP) 8-Pin, Small Outline Package (SOP) Eco Status RoHS RoHS Green Packing Method Tape & Reel Tube Tape & Reel For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2008 Fairchild Semiconductor Corporation FAN6961 • Rev. 1.0.2 www.fairchildsemi.com FAN6961 — Boundary Mode PFC Controller Application Diagram Figure 1. Typical Application Block Diagram Figure 2. Function Block Diagram © 2008 Fairchild Semiconductor Corporation FAN6961 • Rev. 1.0.2 www.fairchildsemi.com 2 FAN6961 — Boundary Mode PFC Controller Marking Information F- Fairchild Logo Z- Plant Code X- Year Code Y- Week Code TT: Die Run Code T: Package type (S=SOP, D=DIP) P: Z: Pb Free Y: Green Compound M: Manufacture Flow Code Figure 3. Marking Information FAN6961 TPM Pin Configuration VCC GATE GND ZCD 8 7 6 5 1 INV 2 COMP 3 MOT 4 CS Figure 4. DIP and SOP Pin Configuration (Top View) Pin Definitions Pin # 1 2 3 Name INV COMP MOT Description Inverting input of the error amplifier. INV is connected to the converter output via a resistive divider. This pin is also used for over-voltage clamping and open-loop feedback protection. The output of the error amplifier. To create a precise clamping protection, a compensation network between this pin and GND is suggested. Maximum On Time A resistor from MOT to GND is used to determine the maximum on-time of the external power MOSFET. The maximum output power of the converter is a function of the maximum on time. Current Sense. Input to the over-current protection comparator. When the sensed voltage across the sense resistor reaches the internal threshold (0.8V), the switch is turned off to activate cycle-by-cycle current limiting. Zero Current Detection. This pin is connected to an auxiliary winding via a resistor to detect the zero crossing of the switch current. When the zero crossing is detected, a new switching cycle is started. If it is connected to GND, the device is disabled. Ground. The power ground and signal ground. Placing a 0.1µF decoupling capacitor between VCC and GND is recommended. Driver output. Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage is 16.5V. Power supply. Driver and control circuit supply voltage. www.fairchildsemi.com 3 4 CS 5 6 7 8 ZCD GND GATE VCC © 2008 Fairchild Semiconductor Corporation FAN6961 • Rev. 1.0.2 FAN6961 — Boundary Mode PFC Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltage, are given with respect to GND pin. Symbol VVCC VHIGH VLOW VZCD PD TJ θJA TSTG TL ESD DC Supply Voltage Gate Driver Parameter Min. -0.3 -0.3 -0.3 SOP DIP -40 SOP DIP -65 SOP DIP Max. 30 30.0 7.0 12.0 400 800 +125 150 113 +150 +230 +260 2.5 200 Unit V V V V mW °C °C/W °C °C KV V Others (INV, COMP, MOT, CS) Input Voltage to ZCD Pin Power Dissipation Operating Junction Temperature Thermal Resistance (Junction-to-Air) Storage Temperature Range Lead Temperature (Wave Soldering or IR, 10 Seconds) Human Body Model: JESD22-A114 Machine Model: JESD22-A115 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature Min. -40 Typ. Max. +125 Unit °C © 2008 Fairchild Semiconductor Corporation FAN6961 • Rev. 1.0.2 www.fairchildsemi.com 4 FAN6961 — Boundary Mode PFC Controller Electrical Characteristics VCC=15V and TA=25°C unless otherwise noted. Symbol VCC Section VCC-OP VCC-ON VCC-OFF ICC-ST ICC-OP VCC-OVP Parameter Continuous Operation Voltage Turn-on Threshold Voltage Turn-off Threshold Voltage Start-up Current Operating Supply Current VDD Over-Voltage Protection Level Conditions Min. Typ. Max. 24.5 Units V V V µA mA V µs 11 8.5 VCC=VCC-ON – 0.16V VCC=12V, VCS=0V, CL=3nF, fSW =60KHz 26.5 12 9.5 10 4.5 27.5 30 13 10.5 20 6 28.5 tD-VCCOVP VDD Over-Voltage Protection Debounce Error Amplifier Section VREF Gm VINVH VINVL Reference Voltage Transconductance Clamp High Feedback Voltage Clamp Low Feedback Voltage 2.25 4.8 1.15 2.70 0.40 VINV=2.35V, VCOMP=1.5V VINV=1.5V, VINV=2.65V, VCOMP=5V 10 550 10 2.475 2.500 125 2.65 2.30 2.525 V μmho 2.70 V V V VOUT HIGH Output High Voltage VOZ VINV-OVP VINV-UVP Zero Duty Cycle Output Voltage Over Voltage Protection for INV Input Under Voltage Protection for INV Input Source Current Sink Current Current-Sense Section VPK tPD tLEB Threshold Voltage for Peak Current Limit Cycle-by-Cycle Limit Propagation Delay RMOT=24kΩ, VCOMP=5V Leading-Edge Blanking Time RMOT=24kΩ, VCOMP=VOZ+50mV 1.25 2.75 0.45 20 800 20 1.35 2.80 0.50 V V V ICOMP μA 0.77 0.82 0.87 200 V ns ns 400 270 500 350 Gate Section VZ-OUT VOL VOH tR tF Output Voltage Maximum (Clamp) Output Voltage Low Output Voltage High Rising Time Falling Time VCC=25V VCC=15V, IO=100mA VCC=14V, IO=100mA VCC=12V, CL=3nF, 20~80% VCC=12V, CL=3nF, 80~20% 8 80 40 15.0 16.5 18.0 1.4 V V V ns ns Continued on the following page… © 2008 Fairchild Semiconductor Corporation FAN6961 • Rev. 1.0.2 www.fairchildsemi.com 5 FAN6961 — Boundary Mode PFC Controller Electrical Characteristics VCC=15V and TA=25°C unless otherwise noted. Symbol VZCD HYS of VZCD Parameter Input Threshold Voltage Rising Edge Threshold Voltage Hysteresis Conditions VZCD Increasing VZCD Decreasing IZCD=3mA IZCD=-1.5mA VCOMP=5V, fSW =60KHz Output Turned Off by ZCD RMOT=24kΩ Min. 1.9 Typ. 2.1 0.35 Max. 2.3 Units V V Zero Current Detection Section VZCD-HIGH Upper Clamp Voltage VZCD-LOW Lower Clamp Voltage tDEAD tRESTART tINHIB VDIS tZCD-DIS Maximum Delay, ZCD to Output Turn-On Restart Time Inhibit Time (Maximum Switching Frequency Limit) Disable Threshold Voltage Disable Function Debounce Time 12 0.3 100 300 500 2.8 150 200 250 400 700 V V ns μs μs mV μs RMOT=24kΩ, VZCD=100mV 800 Maximum On Time Section VMOT tON-MAX Maximum On Time Voltage Maximum On Time Programming (Resistor Based) RMOT=24kΩ, VCS=0V, VCOMP=5V 1.25 1.30 25 1.35 V μs © 2008 Fairchild Semiconductor Corporation FAN6961 • Rev. 1.0.2 www.fairchildsemi.com 6 FAN6961 — Boundary Mode PFC Controller Typical Performance Characteristics 2.525 2.515 2.505 2.495 2.485 2 .475 -40 -25 -10 5 20 35 50 65 80 95 110 125 3.0 2.4 I CC-OP ( mA) V ref ( V) 1.8 1.2 0.6 0.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( ℃ ) Figure 5. VREF vs. TA Temperature ( ℃ ) Figure 6. ICC-OP vs. TA 24.60 24.52 14.0 13.4 t ON-MAX (μ s) 24.44 24.36 24.28 2 4.20 -40 -25 -10 5 20 35 50 65 80 95 110 125 V th-ON ( V) 12.8 12.2 11.6 11.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( ℃ ) Figure 7. tON-MAX vs. TA Temperature (℃ ) Figure 8. Vth-ON vs. TA 10.5 10.1 9.7 9.3 8.9 8 .5 -40 -25 -10 5 20 35 50 65 80 95 110 125 16.0 13.6 I CC-ST (μ A) V th-OFF ( V) 11.2 8.8 6.4 4.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( ℃ ) Figure 9. Vth-OFF vs. TA Temperature ( ℃ ) Figure 10. ICC-ST vs. TA © 2008 Fairchild Semiconductor Corporation FAN6961 • Rev. 1.0.2 www.fairchildsemi.com 7 FAN6961 — Boundary Mode PFC Controller Typical Performance Characteristics (Continued) 1.350 1.330 1.310 1.290 1.270 1 .250 -40 -25 -10 5 20 35 50 65 80 95 110 125 18.0 17.4 V Z-OUT ( V) V MOT ( V) 16.8 16.2 15.6 15.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( ℃ ) Figure 11. VMOT vs. TA 0.87 0.85 Temperature ( ℃ ) Figure 12. VZ-OUT vs. TA V PK ( V) 0.83 0.81 0.79 0 .77 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( ℃ ) Figure 13. VPK vs. TA © 2008 Fairchild Semiconductor Corporation FAN6961 • Rev. 1.0.2 www.fairchildsemi.com 8 FAN6961 — Boundary Mode PFC Controller Functional Description Error Amplifier The inverting input of the error amplifier is referenced to INV. The output of the error amplifier is referenced to COMP. The non-inverting input is internally connected to a fixed 2.5V ± 2% voltage. The output of the error amplifier is used to determine the on-time of the PWM output and regulate the output voltage. To achieve a low input current THD, the variation of the on time within one input AC cycle should be very small. A multivector error amplifier is built in to provide fast transient response and precise output voltage clamping. For FAN6961, connecting a capacitance, such as 1µF, between COMP and GND is suggested. The error amplifier is a trans-conductance amplifier that converts voltage to current with a 125µmho. Leading-Edge Blanking (LEB) A turn-on spike on CS pin appears when the power MOSFET is switched on. At the beginning of each switching pulse, the current-limit comparator is disabled for around 400ns to avoid premature termination. The gate drive output cannot be switched off during the blanking period. Conventional RC filtering is not necessary, so the propagation delay of current limit protection can be minimized. Under-Voltage Lockout (UVLO) The turn-on and turn-off threshold voltage is fixed internally at 12V/9.5V. This hysteresis behavior guarantees a one-shot start-up with proper start-up resistor and hold-up capacitor. With an ultra-low startup current of 20µA, one 1MΩ RIN is sufficient for startup under low input line voltage, 85Vrms. Power dissipation on RIN would be less than 0.1W even under high line (VAC=265Vrms) condition. Startup Current Typical startup current is less than 20µA. This ultra-low startup current allows the usage of high resistance, low-wattage start-up resistor. For example, 1MΩ/0.25W startup resistor and a 10µF/25V (VCC hold-up) capacitor are recommended for an AC-to-DC power adaptor with a wide input range 85-265VAC. Output Driver W ith low on resistance and high current driving capability, the output driver can drive an external capacitive load larger than 3000pF. Cross conduction current has been avoided to minimize heat dissipation, improving efficiency and reliability. This output driver is internally clamped by a 16.5V Zener diode. Operating Current Operating current is typically 4.5mA. The low operating current enables a better efficiency and reduces the requirement of VCC hold-up capacitance. Zero-Current Detection (ZCD) The zero-current detection of the inductor is achieved using its auxiliary winding. When the stored energy of the inductor is fully released to output, the voltage on ZCD goes down and a new switching cycle is enabled after a ZCD trigger. The power MOSFET is always turned on with zero inductor current such that turn-on loss and noise can be minimized. The converter works in boundary mode and peak inductor current is always exactly twice of the average current. A natural power factor correction function is achieved with the lowbandwidth, on-time modulation. An inherent maximum off time is built in to ensure proper start-up operation. This ZCD pin can be used as a synchronous input. Maximum On-Time Operation Given a fixed inductor value and maximum output power, the relationship between on-time and line voltage is: t on = 2 • L • Po Vrms 2 • η (1) If the line voltage is too low or the inductor value is too high, tON is too long. To avoid extra low operating frequency and achieve brownout protection, the maximum value of tON is programmable by one resistor, RI, connected between MOT and GND. A 24kΩ resistor RI generates corresponds to 25µs maximum on time: t on(max) 25 = R I ( kΩ ) • (μs ) 24 Noise Immunity Noise on the current sense or control signal can cause significant pulse-width jitter, particularly in the boundary-mode operation. Slope compensation and built-in debounce circuit can alleviate this problem. Because the FAN6961 has a single ground pin, high sink current at the output cannot be returned separately. Good high-frequency or RF layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near to the FAN6961, and increasing the power MOSFET gate resistance improve performance. (2) The range of the maximum on-time is designed as 10 ~ 50µs. Peak Current Limiting The switch current is sensed by one resistor. The signal is feed into CS pin and an input terminal of a comparator. A high voltage in CS pin terminates a switching cycle immediately and cycle-by-cycle current limit is achieved. The designed threshold of the protection point is 0.82V. © 2008 Fairchild Semiconductor Corporation FAN6961 • Rev. 1.0.2 www.fairchildsemi.com 9 FAN6961 — Boundary Mode PFC Controller Reference Circuit Figure 14. Reference Circuit © 2008 Fairchild Semiconductor Corporation FAN6961 • Rev. 1.0.2 www.fairchildsemi.com 10 FAN6961 —Boundary Mode PFC Controller Physical Dimensions 9.83 9.00 6.67 6.096 8.255 7.61 5.08 MAX 3.683 3.20 7.62 0.33 MIN (0.56) 2.54 3.60 3.00 0.56 0.355 1.65 1.27 7.62 0.356 0.20 9.957 7.87 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994 E) DRAWING FILENAME AND REVSION: MKT-N08FREV2. Figure 15. 8-Lead, PDIP, JEDEC MS-001, .300 Inch Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation FAN6961 • Rev. 1.0.2 www.fairchildsemi.com 11 FAN6961 —Boundary Mode PFC Controller Physical Dimensions (Continued) 5.00 4.80 3.81 8 5 A 0.65 B 6.20 5.80 4.00 3.80 1 4 1.75 5.60 PIN ONE INDICATOR (0.33) 1.27 0.25 M CBA 1.27 LAND PATTERN RECOMMENDATION 0.25 0.10 1.75 MAX C 0.10 0.51 0.33 0.50 x 45° 0.25 C SEE DETAIL A 0.25 0.19 OPTION A - BEVEL EDGE R0.10 R0.10 GAGE PLANE 0.36 OPTION B - NO BEVEL EDGE NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 8° 0° 0.90 0.406 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 16. 8-Lead, SOIC,JEDEC MS-012, .150 Inch Narrow Body Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation FAN6961 • Rev. 1.0.2 www.fairchildsemi.com 12 FAN6961 —Boundary Mode PFC Controller © 2008 Fairchild Semiconductor Corporation FAN6961 • Rev. 1.0.2 www.fairchildsemi.com 13