FIN1532

FIN1532 5V LVDS 4-Bit High Speed Differential Receiver December 2001 Revised December 2001 FIN1532 5V LVDS 4-Bit High Speed Differential Receiver General Description This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data. The FIN1532 can be paired with its companion driver, the FIN1531, or any other LVDS driver. Features s Greater than 400Mbs data rate s 5V power supply operation s 0.5 ns maximum differential pulse skew s 3 ns maximum propagation delay s Low power dissipation s Power-Off protection for inputs and outputs s Fail safe protection for open-circuit, shorted and terminated receiver inputs s Meets or exceeds the TIA/EIA-644 LVDS standard s Pin compatible with equivalent RS-422 and PECL devices s 16-Lead SOIC and TSSOP packages save space Ordering Code: Order Number FIN1532M FIN1532MTC Package Number M16A MTC16 Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Pin Name RIN1+, RIN2+, RIN3+, RIN4+ RIN1−, RIN2−, RIN3−, RIN4− EN EN VCC GND Description Non-inverting LVDS Inputs Inverting LVDS Inputs Driver Enable Pin Inverting Driver Enable Pin Power Supply Ground ROUT1, ROUT2, ROUT3, ROUT4 LVTTL Data Outputs Connection Diagram Function Table Input EN H H H X X X L H = HIGH Logic Level Z = High Impedance Outputs RIN+ H L H L X RIN+ L H L H ROUT H L H H L H Z Top View EN X X X L L L H Fail Safe Condition Fail Safe Condition L = LOW Logic Level X = Don’t Care Fail Safe = Open, Shorted, Terminated © 2001 Fairchild Semiconductor Corporation DS500504 www.fairchildsemi.com FIN1532 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Voltage (VIN) Enable Inputs Receiver Inputs DC Output Voltage (VOUT) DC Output Current (IO) Storage Temperature Range (TSTG) Max Junction Temperature (TJ) Lead Temperature (TL) (Soldering, 10 seconds) ESD (Human Body Model) ESD (Machine Model) 260°C −0.5 V to +6 V −0.5 V to +6 V −0.5 V to +6 V −0.5 V to +6 V 16 mA Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VIN) Enable Inputs Receiver Inputs Magnitude of Differential Voltage (|VID|) Common-mode Input Voltage (VIC) Operating Temperature (TA) |VID|/2 to (2.4−|VID|/2) 100 mV to 600 mV 0 to VCC 0 to 2.4 V 4.5 V to 5.5 V −65°C to +150°C 150°C −40°C to +85°C ≥ 8000 V ≥ 300 V Note 1: The “Absolute Maximum Ratings”: are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification. DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol VTH VTL IIN Parameter Differential Input Threshold HIGH Differential Input Threshold LOW Input Current EN or EN Input Current Receiver Inputs VIH VIL VOH VOL VIK IOZ IO(OFF) IOS ICCZ ICC IPU/PD CIN COUT Input High Voltage (EN or EN) Input Low Voltage (EN or EN) Output HIGH Voltage Output LOW Voltage Input Clamp Voltage Disabled Output Leakage Current Power-OFF Output Current Output Short Circuit Test Disabled Power Supply Current Power Supply Current Output Power Up/Power Down High Z Leakage Current Input Capacitance Output Capacitance 5.5 4.5 pF pF IOH = −100 µA IOH = −8 mA IOH = 100 µA IOL = 8 mA IIK = −18 mA EN = 0.8 and EN = 2V, VOUT = 5.5V or 0V VOUT = 0V or 5.5V, VCC = 0V Receiver Enabled, VOUT = 0V (one output shorted at a time) Receiver Disabled Receiver Enabled, RIN+ = 1V and RIN− = 1.4V Receiver Enabled, RIN+ = 1.4V and RIN− = 1V VCC = 0V to 2.0V −15 1.2 11 15 −1.5 Test Conditions VIC = +1.2V, See Figure 1 VIC = +1.2V, See Figure 1 VIN = 0V or VCC, VCC = 5.5 or 0V VIN = 0V or 2.4 V, VCC = 5.5 or 0V 2.0 GND VCC −0.2 3.8 4.98 4.68 0.01 0.22 −0.8 ±20 50 −100 5 17 23 ±20 0.2 0.5 −100 ±20 ±20 VCC 0.8 Min Typ (Note 2) 100 Max Units mV mV µA µA V V V V V µA µA mA mA mA µA Note 2: All typical values are at TA = 25°C and with VCC = 5V. www.fairchildsemi.com 2 FIN1532 AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol tPLH tPHL tTLH tTHL tSK(P) tSK(LH), tSK(HL) tSK(PP) fMAX tZH tZL tHZ tLZ Parameter Propagation Delay LOW-to-HIGH Propagation Delay HIGH-to-LOW Output Rise Time (20% to 80%) Output Fall Time (80% to 20%) Pulse Skew |tPLH - tPHL| Channel-to-Channel Skew (Note 4) Part-to-Part Skew (Note 5) Maximum Operating Frequency (Note 6) RL = 1kΩ, CL = 10 pF, See Figure 1 and Figure 2 200 260 8 8 4 4 12.0 12.0 8.0 8.0 |VID| = 400 mV, CL = 10 pF, RL = 1kΩ See Figure 1 and Figure 2 Test Conditions Min Typ (Note 3) 1.0 1.0 2.0 2.0 1.3 1.1 0.2 0.1 0.5 0.3 1.0 3.0 3.0 Max Units ns ns ns ns ns ns ns MHz ns ns ns ns LVTTL Output Enable Time from Z to HIGH RL = 1kΩ, CL = 10 pF, LVTTL Output Enable Time from Z to LOW See Figure 3 and Figure 4 LVTTL Output Disable Time from HIGH to Z LVTTL Output Disable Time from LOW to Z Note 3: All typical values are at TA = 25°C and with VCC = 5V. Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. Note 6: fMAX Criteria: Input tR = tF < 1 ns, VID = 300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, VOL < 0.5V, VOH > 2.4V. All channels switching in phase. Note A: All input pulses have frequency = 10 MHz, tR or tF = 1 ns Note B: CL includes all probe and jig capacitances FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay 3 www.fairchildsemi.com FIN1532 FIGURE 2. LVDS Input to LVTTL Output AC Waveforms Test Circuit for LVTTL Outputs FIGURE 3. AC Loading Circuit for LVTTL Outputs Voltage Waveforms Enable and Disable Times Note A: CL includes probes and jig capacitance Note B: All LVTTL input pulses have the following characteristics: Frequency = 10 MHz, tR or tF = 2 ns FIGURE 4. LVTTL Outputs Test Circuit and AC Waveforms www.fairchildsemi.com 4 FIN1532 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com FIN1532 5V LVDS 4-Bit High Speed Differential Receiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com