FIN1532MX_NF40

Revised December 2001 FIN1532 5V LVDS 4-Bit High Speed Differential Receiver General Description Features This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data. ■ Greater than 400Mbs data rate The FIN1532 can be paired with its companion driver, the FIN1531, or any other LVDS driver. ■ Fail safe protection for open-circuit, shorted and terminated receiver inputs ■ 5V power supply operation ■ 0.5 ns maximum differential pulse skew ■ 3 ns maximum propagation delay ■ Low power dissipation ■ Power-Off protection for inputs and outputs ■ Meets or exceeds the TIA/EIA-644 LVDS standard ■ Pin compatible with equivalent RS-422 and PECL devices ■ 16-Lead SOIC and TSSOP packages save space Ordering Code: Order Number Package Number FIN1532M M16A FIN1532MTC Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Connection Diagram Pin Name Description ROUT1, ROUT2, ROUT3, ROUT4 LVTTL Data Outputs RIN1+, RIN2+, RIN3+, RIN4+ Non-inverting LVDS Inputs RIN1−, RIN2−, RIN3−, RIN4− Inverting LVDS Inputs EN Driver Enable Pin EN Inverting Driver Enable Pin VCC Power Supply GND Ground Function Table Input Outputs EN EN RIN+ RIN+ ROUT H X H L H H X L H H X X L H L X L L H X L L H H = HIGH Logic Level Z = High Impedance L Fail Safe Condition Top View H H L Fail Safe Condition H X Z L = LOW Logic Level X = Don’t Care Fail Safe = Open, Shorted, Terminated © 2001 Fairchild Semiconductor Corporation DS500504 www.fairchildsemi.com FIN1532 5V LVDS 4-Bit High Speed Differential Receiver December 2001 FIN1532 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) Recommended Operating Conditions −0.5 V to +6 V DC Input Voltage (VIN) Enable Inputs −0.5 V to +6 V Receiver Inputs −0.5 V to +6 V DC Output Voltage (VOUT) 4.5 V to 5.5 V Input Voltage (VIN) Enable Inputs −0.5 V to +6 V DC Output Current (IO) Storage Temperature Range (TSTG) Supply Voltage (VCC) 0 to VCC Receiver Inputs 16 mA 0 to 2.4 V Magnitude of Differential Voltage −65°C to +150°C (|VID|) 100 mV to 600 mV 150°C Common-mode Input Voltage (Soldering, 10 seconds) 260°C ESD (Human Body Model) ≥ 8000 V Operating Temperature (TA) Max Junction Temperature (TJ) Lead Temperature (TL) −40°C to +85°C Note 1: The “Absolute Maximum Ratings”: are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification. ≥ 300 V ESD (Machine Model) |VID|/2 to (2.4−|VID|/2) (VIC) DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol Parameter Test Conditions VTH Differential Input Threshold HIGH VIC = +1.2V, See Figure 1 VTL Differential Input Threshold LOW VIC = +1.2V, See Figure 1 IIN Min Typ Max (Note 2) 100 −100 Units mV mV Input Current EN or EN VIN = 0V or VCC, VCC = 5.5 or 0V ±20 µA Input Current Receiver Inputs VIN = 0V or 2.4 V, VCC = 5.5 or 0V ±20 µA VIH Input High Voltage (EN or EN) 2.0 VCC V VIL Input Low Voltage (EN or EN) GND 0.8 V VOH Output HIGH Voltage IOH = −100 µA IOH = −8 mA VOL Output LOW Voltage VCC −0.2 4.98 3.8 4.68 V IOH = 100 µA 0.01 0.2 IOL = 8 mA 0.22 0.5 −1.5 VIK Input Clamp Voltage IIK = −18 mA IOZ Disabled Output Leakage Current EN = 0.8 and EN = 2V, VOUT = 5.5V or 0V ±20 µA IO(OFF) Power-OFF Output Current VOUT = 0V or 5.5V, VCC = 0V 50 µA IOS Output Short Circuit Test Receiver Enabled, VOUT = 0V −100 mA (one output shorted at a time) −0.8 V −15 V ICCZ Disabled Power Supply Current Receiver Disabled 1.2 5 ICC Power Supply Current Receiver Enabled, RIN+ = 1V and RIN− = 1.4V 11 17 Receiver Enabled, RIN+ = 1.4V and RIN− = 1V 15 IPU/PD Output Power Up/Power Down VCC = 0V to 2.0V 23 ±20 mA mA µA High Z Leakage Current CIN Input Capacitance 5.5 pF COUT Output Capacitance 4.5 pF Note 2: All typical values are at TA = 25°C and with VCC = 5V. www.fairchildsemi.com 2 Over supply voltage and operating temperature ranges, unless otherwise specified Symbol tPLH Parameter Test Conditions Propagation Delay LOW-to-HIGH tPHL Propagation Delay Min Typ Max (Note 3) Units 1.0 2.0 3.0 ns 1.0 2.0 3.0 ns HIGH-to-LOW |VID| = 400 mV, CL = 10 pF, RL = 1kΩ tTLH Output Rise Time (20% to 80%) See Figure 1 and Figure 2 tTHL Output Fall Time (80% to 20%) 1.1 tSK(P) Pulse Skew |tPLH - tPHL| 0.2 0.5 tSK(LH), Channel-to-Channel Skew 0.1 0.3 ns 1.0 ns tSK(HL) (Note 4) tSK(PP) Part-to-Part Skew (Note 5) fMAX Maximum Operating Frequency RL = 1kΩ, CL = 10 pF, (Note 6) See Figure 1 and Figure 2 1.3 200 ns ns 260 ns MHz tZH LVTTL Output Enable Time from Z to HIGH RL = 1kΩ, CL = 10 pF, 8 12.0 ns tZL LVTTL Output Enable Time from Z to LOW See Figure 3 and Figure 4 8 12.0 ns tHZ LVTTL Output Disable Time from HIGH to Z 4 8.0 ns tLZ LVTTL Output Disable Time from LOW to Z 4 8.0 ns Note 3: All typical values are at TA = 25°C and with VCC = 5V. Note 4: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. Note 5: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. Note 6: fMAX Criteria: Input tR = tF < 1 ns, VID = 300 mV, (1.05V to 1.35V pp), 50% duty cycle; Output duty cycle 40% to 60%, VOL < 0.5V, VOH > 2.4V. All channels switching in phase. Note A: All input pulses have frequency = 10 MHz, tR or tF = 1 ns Note B: CL includes all probe and jig capacitances FIGURE 1. Differential Receiver Voltage Definitions and Propagation Delay 3 www.fairchildsemi.com FIN1532 AC Electrical Characteristics FIN1532 FIGURE 2. LVDS Input to LVTTL Output AC Waveforms Test Circuit for LVTTL Outputs FIGURE 3. AC Loading Circuit for LVTTL Outputs Voltage Waveforms Enable and Disable Times Note A: CL includes probes and jig capacitance Note B: All LVTTL input pulses have the following characteristics: Frequency = 10 MHz, tR or tF = 2 ns FIGURE 4. LVTTL Outputs Test Circuit and AC Waveforms www.fairchildsemi.com 4 FIN1532 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com FIN1532 5V LVDS 4-Bit High Speed Differential Receiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6