FM3560M20

FM3540/60 4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches October 2001 FM3540/60 4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches General Description The FM3540/60 multiplexes the I-port input signals with two internal non-volatile registers that can be loaded through the serial port. The multiplexer is selected via the serial port and defaults to the I-Port upon power-up. Pull-up resistors are provided on the input port to accommodate connections to open drain outputs and to eliminate the need for external resistors. The device supports a choice of either 2.5V output or Open Drain Outputs for easy interface to devices with different VDD Levels. The serial port is an IIC compatible slave only interface and supports both 100kbits and 400kbits modes of operation. The port is used to read the I-Port, Write Data to the internal non-volatile registers and select whether the I-Port or one of the internal nonvolatile registers is output to the Y-port. The FM3540/60 is fabricated with an advanced CMOS technology to achieve high density and low power. Features I Extended Operating Voltage Range 3.0V-5.5V I IIC Compatible Slave Interface. I ESD performance: Human body model > 2000V I Choice of 2.5V outputs or Open-Drain Outputs Block Diagram Non_Mux_Out I[4:0] Y[4:0] Mux1 SOPRA Mux2 SOPRB MXSB, MXSA IIC Read Logic Mux3 Control Logic MUXSEL OVRD SDA SCL IIC Interface Shift Register Slave Address Register ASEL Comparator Start/Stop Logic © 2001 Fairchild Semiconductor Corporation FM3540/60 Rev. C 1 www.fairchildsemi.com FM3540/60 4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches Ordering Information Order Number FM3540CM14 FM3540CMT14 FM3540SM14 FM3540SMT14 FM3560M20 FM3560MT20 Note About Y-Port Output Type: FM3560 device has a dedicated input pin (LEVEL) to select either "Fixed 2.5Volts" or "Open-Collector" Y-Port output type. Note About Device Address: 1. For FM3540 with an alternate device address of 0110111, contact Fairchild Marketing/Sales. 2. FM3560 device has a dedicated input pin (ASEL) to select either "1001110" or 0110111" as device address. Package Number M14A MTC14 M14A MTC14 M20B MTC20 Package Description 14-Pin SO 14-Pin TSSOP 14-Pin SO 14-Pin TSSOP 20-Pin SO 20-Pin TSSOP Packing T&R T&R T&R T&R T&R T&R Y-Port Output Type Open-Collector Open-Collector Fixed 2.5V Fixed 2.5V (See Note below) (See Note below) Device Address 1001110 1001110 1001110 1001110 (See Note below) (See Note below) Pin Connection Diagrams 14-Pin Packages FM3540 SDA I0 I1 I2 I3 I4 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 SCL VCC Y0 Y1 Y2 Y3 Y4 20-Pin Packages FM3560 SCL SDA OVRD I0 I1 I2 I3 I4 Level GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC ASEL WP Non_Mux_Out MUXSEL Y0 Y1 Y2 Y3 Y4 Pin Description Pin Name I[0:4] Y[0:4] SCL Override# WP Non_Mux_Out Mux_Sel Level ASEL SDA Description Data Inputs w/Pullups (10K-40K) O/D Data Outputs Serial Port Clock Input (120K pullup) Override Input, sets all outputs to 0 Write Protect Input Non-Multiplexed Output Mux. Select Input Level Select Input Address Select Input Serial Port Data I/O (120K pullup) 2 FM3540/60 Rev. C www.fairchildsemi.com FM3540/60 4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches Functional Description The FM3540/60 has two primary functional modes of operation and an additional mode for programming the device. Operational Modes During standard operation the device will either pass an address to the Y-Port from the I-Port or from an internally programmed value. At power up the device will default to passing the I-Port value to the Y-Port. The I-port values are generated from the motherboard of the system and may be hardwired or driven by another device. Pullup resistors are provided on the device to accommodate this device being driven by open drain output drivers. The device expects standard CMOS input signals. The level of the output signal is determined by the Level input. If this input is connected to Vss/Ground, the output is at 2.5V on the multiplexed outputs (Y0-Y4). The non-multiplexed output is always at CMOS levels. The Level input, if left unconnected (it has an internal pullup), will cause the Y0-Y4 outputs to operate as open-drain outputs. The override# input, when set to 0, will cause all the outputs to be set to 0. The WP signal, if set to logic 1, will prevent data from being written to the non-volatile register. The mux_sel input, when set to logic 0, will select the data from the non-volatile register to drive on the Y0-4 outputs. If set to logic 1, the data from the inputs are selected instead. The non_mux_out latch is transparent when the mux_sel signal is at logic 0, and will latch data when the mux_select is in a logic 1 state. Serial Output Port Register (SOPR) (Address 000b and 001b) MXSB MXSA 0 b7 0 b6 I5 b5 NMO b4 Data Field I3 b3 I2 b2 I1 B1 I0 b0 b7-b6 - Multiplexer Select Bits (MXSB,MXSA) 00 - Multiplexer passes the SOPR(A). 01 - Multiplexer passer the SOPR(B). 10 - Multiplexer defaults to passing the I-Port Value. b5, b3-b0 - Data Field. New value to be output through the multiplexer. nmo - Non multiplexed output from internal non-volatile bit Parallel Input Port Register (PIPR) (Address 002b) Address Field 0 b7 0 b6 0 b5 I4 b4 Data Field I3 b3 I2 b2 I1 B1 I0 b0 b7-b5 - Address field. Value is always 000 b4-b0 - Data Field. Value is equal to the value on the I-Port. The external Port Register captures the value on the I-Port. Data is latched into this register on the first clock after a start condition is seen. This insures that a valid value will always be in this register if it is read. This register is a read only register with respect to the IIC port. Override# 0 0 1 1 mux_ sel MXSB MXSA 0 1 0 0 X X 1 0 X X 0 0 mux_outputs all 0's Mux_inputs (see note 1) Mux_inputs (see note 1) Non_ mux_output all 0's latched NMO latched NMO Output Port: Y0-Y4 The output port is an open drain output to allow for easy connection to devices running at different voltage levels. The port is always active and either passes the value on the I-Port or the value in the Serial output port Register (SOPR). Changing the Mux Path is accomplished by writing to b7, b6 of the Serial Input Port Register. SOPR-b7, b6 defaults to a value of "10" at power up and the default path is from the I-Port through to the output port. The multiplexer only updates when an IIC stop condition is observed. Register Description The FM3540/60 has 3 registers in total. These registers are made up of a combination of read only, write only and read write bits. The two registers are listed below. Serial Output Port Register A(SOPRA) Address: 00H - A read/ write register that contains the new value to be written to output Port-Y and the multiplexer select bit. Serial Output Port Register B(SOPRB) Address: 01H - A read/ write register that contains the new value to be written to output Port-Y and the multiplexer select bit. Parallel Input Port Register (PIPR) Address: 02H - A read only register that is loaded with the 5 bit value of the I-Port. From NonFrom nonvolatile regvolatile register (SOPRA) ister (SOPRA) Do not use this combination From NonFrom nonvolatile regvolatile register (SOPRB) ister (SOPRB) Mux_inputs From Nonvolatile register (SOPRA or SOPRB) 1 1 0 0 1 0 1 1 1 1 Note 2 Note 1 Note 1: Latched NMO state will be the value present on the NMO output at the time of the mux_sel input transitioning from logic 0 to logic 1 state. Note 2: Output depends on previously selected state of MXSB and MXSA bits written to device. 3 FM3540/60 Rev. C www.fairchildsemi.com FM3540/60 4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches Multiplexer Logic The output multiplexer logic determines what value is actually output to the Y-port. The value that is output is dependent upon b7b6 of the SOPRA and SOPRB registers, as well as the external mux_sel and override# inputs. The is only one set of MXS bits in the SOPRA and SOPRB registers. Regardless of whether one writes to SOPRA or SOPRB register for setting the MXS bits, the result is the same. These same bits appear in both the registers. If the mux_sel is logic 0 and OVRD is logic 1, then, if b7,b6 is “10” then the value on the I-port is passed. When b7 is “00” the value of the SOPRA register is passed on the next IIC stop condition, and .When b7 is “01” the value of the SOPRB register is passed on the next IIC stop condition. If mux_sel is logic 1 and OVRD is logic 1, the input lines I0-4 are used to drive the outputs. The above table describes all the combinations. If so desired only the SOPRA register can be read. This is accomplished by issuing a stop command after acknowledge bit for the first byte read. If no stop is issued, the device will output the registers in the above sequence. Writing to the Registers Data is written to the SOPR registers through the serial port interface. When a write request is received with the Start Address it is assumed that the intent is to write the SOPR registers. The value placed in the least 6 significant bits of the register contain the new code to be placed in the SOPR A/B registers. The value of the two most significant bits must contain the address of the destination register SOPRA or SOPRB. The internal non-volatile latch takes about 10 ms to update its data. The new data is reflected on the outputs after the internal non-volatile latch is updated, if the corresponding select bits (MXSx, OVRD and mux_sel) are set to reflect the state of the nonvolatile register IIC Interface The IIC Interface is a standard slave interface. As a slave interface the device will not generate its own clock. Data can be read from and written into the device. Commands for reading and writing the registers are generated by the IIC Master. Register Read Sequence Slave SOPRA SOPRB PIPR S Address R A Register A Register A Register A P S 1001110 1 A 00bbbbbb A 00bbbbbb A 00bbbbbb A P START and STOP Conditions SDA Register Write Sequence Slave SOPRx S Address W A Register A S SCL START Condition STOP Condition S 1001110 0 A xxbbbbbb AS xx = Register Selection bits (MXSB and MXSA) xx = 00 selects SOPRA, 01 selects SOPRB The IIC protocol uniquely defines START and STOP conditions. A START condition is defined as a HIGH to LOW transition of the SDA signal while SCL is HIGH. A STOP condition is defined as a LOW to HIGH transition of the SDA signal while SCL is HIGH. These are shown in Figure 2. Register Write Sequence using Repeated Start Condition Slave SOPRA Slave SOPRx S Address R A Register A S Address W A Register A P S 1001110 1 A 00bbbbbb A S 1001110 0 A xxbbbbbb A P Device Addressing The device uses 7 bit IIC addressing. The address has been defined as 1001 110 if the ASEL input is ‘1’ and 0110 111 if the ASEL input is ‘0’. The address byte is the first byte of data sent after a start condition. This is the only address that this device will respond to. The device will not respond to the general call address 0000 000. Figure 4 Reading from the Registers Data can be read from both of the internal registers. All reads are non-destructive and do not change the value in the register or the internal state of the device. When a start condition is received with a read request both registers can be read out in the following sequence. (1) (2) (3) SOPRA - Serial Output Port Register A SPORB - Serial Output Port Register B PIPR - PORT-I Value 4 FM3540/60 Rev. C www.fairchildsemi.com FM3540/60 4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches Absolute Maximum Ratings (Note 1) Supply Voltage (VCC ) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-STATED Outputs Active (Note 2) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) V O < 0V VO > Vcc DC Output Source/Sink Current (IOH/IOL) DC Vcc or Ground Current per Supply Pin (ICC or Ground) Storage Temperature Range (TSTG) -0.5V to +6.5V -0.5V to +6.5V -0.5V to +6.5V -0.5 to VCC+0.5V -50mA -50mA +50mA ±50mA ±100mA -65°C to +150°C Recommended Operating Conditions (Note 3) Power Supply Input Voltage Output Voltage (VO) Output Current IOL Free Air Operating Temperature(TA) Minimum Input Edge Rate (dT/dV) VIN = 0.8V to 2.0V, Vcc = 3.0V 3.0V to 5.5V -0.3V to 5.5V 0V TO VCC 3mA -0°C to +70°C 10nS/V Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: Floating or unused pins (inputs or I/O’s) must be held HIGH or LOW. DC Electrical Characteristics (4.5V < VCC ≤ 5.5V) Symbol VIH VIL VOL IIR ICC Parameter High Level Input Voltage Low Level Input Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current Conditions VCC (V) 4.5 - 5.5 4.5 - 5.5 Min VCC x 0.7 Max VCC x 0.3 0.2 0.4 Units V V V µA µA IOL = 100µA IOL = 3mA VI=VIL VI = VCC or GND VCC ≤ (VaI, VO) ≤ 3.6V 4.5 - 5.5 5.5 4.5 - 5.5 -10 300 +10 975 DC Electrical Characteristics Extended (3.0V ≤ VCC ≤ 5.5V) Symbol VIH VIL VOL VOH Parameter High Level Input Voltage Low Level Input Voltage Low Level Output Voltage Output High Voltage Conditions Vcc (V) 3.0 - 5.5 3.0 - 5.5 Min VCC x 0.7 Max VCC x 0.3 0.2 0.4 Units V V V V IOL = 100µA IOL = 3mA Fixed output mode, ('s' grade samples, or FM3560 with LEVEL input = logical ‘0’) 1 TTL load, 50pf capacitance VI=VIL VI = VCC or GND VCC ≤ (VI, VO) ≤ 3.6V 3.0 - 5.5 3.0 - 5.5 2.3 2.5 IIR ICC Input Leakage Current Quiescent Supply Current 5.5 3.0 - 5.5 -10 300 +10 975 µA µA 5 FM3540/60 Rev. C www.fairchildsemi.com FM3540/60 4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches AC Characteristics Symbol Parameter TA = 0°C to +70°C,CL = 30pF, RL = 500Ω VCC = 5.0V ± 0.5V VCC = 3.3 ± 0.3V Min tPHL TPLH tPHL TPLH Prop Delay I to Y Prop Delay I to Y Prop Delay to Y (from OVRD’ or Mux_Sel) Prop Delay to Y (from OVRD’ or Mux_Sel) Units Max 50 50 50 50 Min Max 50 50 50 50 ns ns ns ns IIC AC Characteristics Symbol Parameter TA = 0°C to +70°C,CL = 30pF, RL = 500Ω 100kHz 400kHz Min fSCL T1 tAA tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO SCL Clock Frequency Noise Supression Time Constant SCL Low to SDA Data Out Valid Time the Bus must be free before a new Transmission can start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (For a repeated Start Condition) Data in Hold Time Data in Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time 4.7 0.3 4.7 4.0 4.7 4.0 4.7 0 250 1000 300 0.6 Units Max 100 100 3.5 Min Max 400 50 kHz nS µS µS µS µS µS 0.1 1.3 0.6 0.6 0.6 0.6 0 100 0.9 µS nS 300 300 nS nS µS Capacitance Symbol Cin CI/O COUT Parameter Input Capacitance (I4-I0) Input/Output Capacitance (SDA) Output Capacitance (Y4-Y0) Conditions VI =0V or VCC, VCC=3.3 or 5.0 VI=0V or VCC, VCC=3.3 or 5.0 TA = +25°C Typical 6 7 7 Units PF PF PF Non-Volatile Memory Characteristics Parameter Data Retention Number of writes Specification 10 years minimum 1,000,000 cycles 6 FM3540/60 Rev. C www.fairchildsemi.com FM3540/60 4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches Physical Dimensions inches (millimeters) unless otherwise noted 0.496 - 05.12 [12.598 - 13.005] 20 11 0.394 - 0.419 [10.008 - 10.643] 30¡ TYP Lead No. 1 IDENT 1 10 0.010 MAX [0.254] 0.291-0.299 [7.391- 7.595] 0.010 - 0.029 x45¡ [0.254 - 0.737] 0.093 - 0.104 [2.362 - 2.642] 0.004-0.012 [0.102-0.305] TYP 8¡ Max Typ All Leads 0.009-0.013 [0.229-0.330] TYP All Leads 0.004 [0.102] All Leads Tips Seating Plane 0.016 - 0.050 [0.406 - 1.270] Typ All Leads 0.050 [1.270] TYP 0.014-0.020 TYP [0.356-0.508] 0.014 [0.356] 0.008 TYP [0.203] Molded Small Outline Package (M) Order Number FM3560XM Package Number M20B X = C for open collector and X = S for 2.5V 7 FM3540/60 Rev. C www.fairchildsemi.com FM3540/60 4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches Physical Dimensions inches (millimeters) unless otherwise noted 0.335 - 0.344 (8.509 - 8.788) 14 13 12 11 10 9 8 0.228 - 0.244 (5.791 - 6.198) 0.010 Max. (0.254) 1 Lead #1 IDENT 0.150 - 0.157 (3.810 - 3.988) 2 3 4 5 6 7 30° Typ. 0.010 - 0.020 x 45° (0.254 - 0.508) 8° Max, Typ. All leads 0.04 (0.102) All lead tips 0.053 - 0.069 (1.346 - 1.753) 0.004 - 0.010 (0.102 - 0.254) Seating Plane 0.016 - 0.050 (0.406 - 1.270) Typ. All Leads 0.014 (0.356) 0.050 (1.270) Typ 0.014 - 0.020 Typ (0.356 - 0.508) 0.008 Typ (0 203) 0.008 - 0.010 (0.203 - 0.254) Typ. all leads Molded Small Outline Package (M) Order Number FM3540XM Package Number M14A X = C for open collector and X = S for 2.5V 8 FM3540/60 Rev. C www.fairchildsemi.com FM3540/60 4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches Physical Dimensions inches (millimeters) unless otherwise noted 5.0 –0.1 -A- 14 8 (4.16) Typ (7.72) Typ 4.4 – 0.1 -B(1.78) Typ 6.4 3.2 (0.42) Typ (0.65) Typ 1 Pin #1 IDENT 1 Max TYP 7 0.2 C B A All Lead Tips Land pattern recommendation 0.1 C All Lead Tips (0.9) See detail A -C0.10 – 0.05 TYP 0.9 - 0.20 TYP 0.65 Typ. 0.19 - 0.30 TYP 0.13 M A B s C s 0¡-8¡ Gage plane 0.25 Dimensions are in millimeters 0.6 –0.1 Seating plane DETAIL A Typ. Scale: 40X Notes: Unless otherwise specified 1. Reference JEDED registration MO153. Variation AB. Ref. Note 6, dated 7/93 Order Number FM3540XMT Package Number MTC14 X = C for open collector and X = S for 2.5V 9 FM3540/60 Rev. C www.fairchildsemi.com FM3540/60 4/5 Bit Multiplexed, 1 Bit Latched Port with Standard 2-Wire Bus Interface and Non-Volatile Latches Physical Dimensions inches (millimeters) unless otherwise noted Order Number FM3560MT Package Number MTC20 Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Français Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383 Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 10 FM3540/60 Rev. C www.fairchildsemi.com