FMS6403MTC20_NL

www.fairchildsemi.com FMS6403 Triple Video Drivers with Selectable HD/PS/SD/ Bypass Filters for RGB and YPbPr Signals Features • Three video anti-aliasing or reconstruction filters • 2:1 Mux inputs for YPbPr and RGB inputs • Supports D1, D2, D3 and D4 video D-connector (EIAJ CP-4120) • Selectable 8MHz/15MHz/30MHz 6th order filters plus bypass • Works with SD (480i), Progressive (480p) and HD (1080i/ 720p) • AC-coupled inputs include DC restore /bias circuitry • All outputs can drive AC or DC coupled 75Ω loads and provide either 0dB or 6dB of gain • 0.40% differential gain, 0.25° differential phase • Lead (Pb)-free TSSOP-20 packaging Description The FMS6403 offers comprehensive filtering for TV, set top box or DVD applications. This part consists of a triple 6th order filter with selectable 30MHz, 15MHz, or 8MHz cutoff frequencies. The filters may also be bypassed so that the bandwidth is limited only by the output amplifiers. A 2 to 1 multiplexer is provided on each filter channel. The triple filters are intended for YPbPr and RGB signals. The DC clamp levels are set according to the RGB_SEL control input. YPbPr sync tips are clamped to 250mV, 1.125V and 1.125V respectively while RGB sync tips are all clamped to 250mV. Sync clamp timing can be derived from the Y/G inputs or from the external SYNC_IN pin. The 8MHz and 15MHz filter settings support bi-level sync while the 30MHz filter setting and bypass mode support tri-level sync. All channels nominally accept AC coupled 1Vpp signals. Selectable 0dB or 6dB gain allows the outputs to drive 1Vpp or 2Vpp signals into AC or DC coupled terminated loads with a 1Vpp input. Input signals cannot exceed 1.5Vpp and outputs cannot exceed 2.5Vpp. Applications • Progressive scan • Cable set top boxes • Home theaters • Satellite set top boxes • DVD players • HDTV • Personal Video Recorders (PVR) • Video On Demand (VOD) Functional Block Diagram SYNC_IN Y1/G1 Y2/G2 EXT_SYNC 8MHz, 15MHz, 30MHz, Bypass Sync Strip Y/GOUT gM 250mV Pb1/B1 Pb2/B2 8MHz, 15MHz, 30MHz, Bypass Pb/BOUT gM RGB_SEL 250mV 1.125V Selectable 0dB or 6dB output gain 8MHz, 15MHz, 30MHz, Bypass 250mV Pr1/R1 Pr2/R2 IN2_SEL 1.125V Pr/ROUT gM FSEL0 FSEL1 0dB_SEL REV. 1C March 2005 DATA SHEET FMS6403 DC Electrical Specifications (TC = 25°C, Vi = 1Vpp, VCC = 5.0V, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted) Symbol ICC Vi Vil Vih VCLAMP1 VCLAMP2 PSRR Parameter Supply Current1 Input Voltage Max Digital Input Low1 Digital Input High1 Output Clamp Voltage Output Clamp Voltage Power Supply Rejection Ratio FSEL0, FSEL1, RGB_SEL, 0dB_SEL, EXT_SYNC, IN2_SEL, SYNC_IN FSEL0, FSEL1, RGB_SEL, 0dB_SEL, EXT_SYNC, IN2_SEL, SYNC_IN R,G,B,Y Pb and Pr DC (All Channels) 0 2.4 250 1.125 -40 Conditions VCC no load Min Typ 90 1.5 0.8 VCC Max Units 130 mA Vpp V V mV V dB Standard Definition Electrical Specifications (TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 0, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted) Symbol AVSD AVSD f1dBSD fCSD fSBSD dG dφ THD XTALK INMUXISO Parameter SD Gain, 0dB_SEL = ‘0’1 1 1 Conditions All Channels SD Mode All Channels SD Mode All Channels All Channels 1 Min 5.6 -0.4 5.5 40 Typ 6.0 0 7.6 8.5 56 0.40 0.25 0.4 -68 -70 74 80 10 4 Max Units 6.4 0.4 dB dB MHz MHz dB % ° % dB dB dB ns ns µs SD Gain, 0dB_SEL = ‘1’ -1dB Bandwidth for SD -3dB Bandwidth for SD Attenuation: SD (Stopband Reject) Differential Gain Differential Phase Output Distortion (All Channels) Crosstalk (Channel-to-Channel) INMUX Isolation Signal-to-Noise Ratio Propagation Delay for SD SYNC to SYNC_IN Delay SYNC_IN Min Pulse Width All Channels at f = 27MHz All Channels All Channels Vout = 1.8Vpp at 1MHz at 1.0MHz at 1.0MHz All Channels, NTC-7 Weighting, 4.2MHz lowpass, 100kHz Highpass Delay from Input to Output at 4.5MHz SNR tpdSD T1 T2 Progressive Scan (PS) Electrical Specifications (TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 0, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted) Symbol AVPS AVPS f1dBPS Parameter PS Gain, 0dB_SEL = ‘0’ -1dB Bandwidth for PS 1 1 1 Conditions All Channels PS Mode All Channels PS Mode All Channels Min 5.6 -0.4 10 Typ 6.0 0 15 Max Units 6.4 0.4 dB dB MHz PS Gain, 0dB_SEL = ‘1’ Note: 1. 100% tested at 25°C. 2 REV. 1C March 2005 FMS6403 DATA SHEET Progressive Scan (PS) Electrical Specifications (Continued) (TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 0, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted) Symbol fCPS fSBPS tpdPS T1 T2 Parameter -3dB Bandwidth for PS Attenuation: PS (Stopband Propagation Delay for PS SYNC to SYNC_IN Delay SYNC_IN Min Pulse Width Reject)1 Conditions All Channels All Channels at f = 54MHz Delay from Input to Output at 10MHz Min 40 Typ 17 48 45 10 2 Max Units MHz dB ns ns µs High Definition Electrical Specifications (TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 1, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted) Symbol AVHD AVHD f1dBHD fCHD fSBHD tpdHD T1 T2 Parameter HD Gain, 0dB_SEL = ‘0’ HD Gain, 0dB_SEL = ‘1’ -1dB Bandwidth for HD1 Reject)1 -3dB Bandwidth for HD Attenuation: HD (Stopband Propagation Delay for HD SYNC to SYNC_IN Delay SYNC_IN Min Pulse Width 1 1 Conditions All Channels HD Mode All Channels HD Mode All Channels All Channels All Channels at f = 74.25MHz Delay from Input to Output at 20MHz Min 5.6 -0.4 20 30 Typ 6.0 0 29 33 40 26 10 1.5 Max Units 6.4 0.4 dB dB MHz MHz dB ns ns µs Unfiltered 1080p Bypass (Wide Bandwidth) Electrical Specifications (TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 1, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted) Symbol AVWB AVWB f1dBWB fCWB tpdWB Parameter Gain, 0dB_SEL = Gain, 0dB_SEL = -1dB Bandwidth -3dB Bandwidth Propagation Delay ‘0’1 ‘1’1 Conditions All Channels Bypass Mode All Channels Bypass Mode All Channels All Channels Delay from Input to Output at 20MHz Min 5.6 -0.4 Typ 6.0 0 63 91 10 Max Units 6.4 0.4 dB dB MHz MHz ns Note: 1. 100% tested at 25°C. REV. 1C March 2005 3 DATA SHEET FMS6403 Absolute Maximum Ratings (beyond which the device may be damaged) Parameter DC Supply Voltage Analog and Digital I/O Output Current, Any One Channel (Do not exceed) Min -0.3 -0.3 Max 6 VCC + 0.3 60 Units V V mA Note: Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if operating conditions are not exceeded. Reliability Information Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Thermal Resistance (θJA), JEDEC Standard Multi-layer Test Boards, Still Air 74 -65 Min Typ Max 150 150 300 Units °C °C °C °C/W Recommended Operating Conditions Parameter Operating Temperature Range VCC Range Input Source Resistance (Rsource) Min 0 4.75 5.0 Typ Max 70 5.25 150 Units °C V Ω 4 REV. 1C March 2005 FMS6403 DATA SHEET Standard Definition Typical Performance Characteristics (TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 0, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted) Figure 1. SD Frequency Response 10 0 -10 1 2 Figure 2. SD Group Delay vs. Frequency 60 40 20 1 Delay (ns) 3 Gain (dB) -20 -30 -40 -50 -60 Mkr Frequency Ref 400kHz 1 2 3 7.58MHz 8.47MHz 27MHz Gain 6dB -1dB BW -3dB BW -53.80dB 0 -20 -40 -60 1 = 8.2MHz (36.80ns) fSBSD = Gain(ref) – Gain(3) = 59.80dB -70 400kHz 5 10 15 20 25 30 -80 400kHz 5 10 15 20 25 30 Frequency (MHz) Frequency (MHz) Figure 3. SD Noise vs. Frequency -60 -70 0.1 Figure 4. SD Differential Gain NTSC Differential Gain (%) 0 -80 Noise (dB) -90 -100 -110 -120 -130 -140 400kHz 1 2 3 4 5 -0.1 -0.2 -0.3 -0.4 1st 2nd 3rd 4th 5th 6th Min = -0.40 Max = 0.00 ppMax = 0.40 Frequency (MHz) Figure 5. SD Differential Phase 0.25 NTSC Differential Phase (deg) 0.20 0.15 0.10 0.05 0 Min = -0.00 Max = 0.25 ppMax = 0.25 1st 2nd 3rd 4th 5th 6th REV. 1C March 2005 5 DATA SHEET FMS6403 Progressive Scan (PS) Typical Performance Characteristics (TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 0, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted) Figure 6. PS Frequency Response 5 -5 1 2 Figure 7. PS Group Delay vs. Frequency 20 10 1 Noise (dB) -25 -35 -45 -55 -65 400kHz 10 20 30 40 50 60 Mkr Frequency Ref 400kHz 1 2 3 14.78MHz 16.57MHz 54MHz Gain 6dB -1dB BW -3dB BW -56.57dB 3 Delay (ns) -15 0 -10 -20 -30 1 = 15MHz (15.95ns) fSBSD = Gain(ref) – Gain(3) = 62.57dB -40 400kHz 10 20 30 40 50 60 Frequency (MHz) Frequency (MHz) High Definition Typical Performance Characteristics (TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 1, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted) Figure 8. HD Frequency Response 10 0 -10 1 2 Figure 9. HD Group Delay vs. Frequency 10 5 1 Delay (ns) Gain (dB) -20 -30 -40 -50 -60 400kHz 10 20 30 40 50 60 70 80 90 100 Mkr Ref 1 2 3 Frequency 400kHz 29.07MHz 32.57MHz 74.25MHz Gain 6dB -1dB BW -3dB BW -35.82dB 3 0 -5 -10 1 = 32MHz (7.07ns) fSBSD = Gain(ref) – Gain(3) = 41.82dB -15 400kHz 10 20 30 40 50 60 70 80 90 100 Frequency (MHz) Frequency (MHz) 6 REV. 1C March 2005 FMS6403 DATA SHEET Unfiltered 1080p Bypass (WB) Typical Performance Characteristics (TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 1, 0dB_SEL = 0 (gain = 6dB), Rsource = 37.5Ω, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted) Figure 10. Bypass Mode Frequency Response Figure 11. Bypass Mode Group Delay vs. Frequency 2 1 6.5 6 5.5 1 4.5 4 3.5 3 2.5 2 400kHz 10 20 30 40 50 Mkr Frequency Ref 400kHz 1 2 62.54MHz 90.51MHz Gain 6dB -1dB BW -3dB BW Delay (ns) Gain (dB) 5 0 -1 -2 -3 1 = 80MHz (-2.22ns) 1 2 -4 60 70 80 90 100 400kHz 10 20 30 40 50 60 70 80 90 100 Frequency (MHz) Frequency (MHz) REV. 1C March 2005 7 DATA SHEET FMS6403 Pin Configuration Pin# EXT_SYNC RGB_SEL Y1/G1 Pin EXT_SYNC Type Input Description Selects the external SYNC_IN signal when set to logic ‘1’, do not float Selects RGB clamp levels when set to logic ‘1’, YPbPr clamp levels when set to logic ‘0’, do not float Y or G input 1 - may be connected to a signal which includes sync Y or G input 2 - may be connected to a signal which includes sync Pb or B input 1 Pb or B input 2 Pr or R input 1 Pr or R input 2 Selects filter corner frequency or bypass, see table, do not float Selects filter corner frequency or bypass, see table, do not float Must be tied to Ground, do not float Must be tied to Ground, do not float Selects output gain of 0dB when set to logic ‘1’, 6dB when set to logic ‘0’, do not float Pr or R output Pb or B output Y or G output Selects mux input 2 when set to logic ‘1’, mux input 1 when set to logic ‘0’, do not float External sync input signal, square wave crossing Vil and Vih input thresholds, do not float +5V supply, do not float +5V supply, do not float 1 2 3 4 5 6 7 8 9 10 20 VCC VCC SYNC_IN In2_SEL 1 FMS6403 20-pin TSSOP 19 18 17 16 15 14 13 12 11 2 RGB_SEL Input Y2/G2 Pb1/B1 Pb2/B2 Pr1/R1 Pr2/R2 FSEL0 FSEL1 Y/GOUT Pb/BOUT Pr/ROUT 0dB_SEL GND GND 3 4 5 6 7 8 9 10 11 12 13 Y1/G1 Y2/G2 Pb1/B1 Pb2/B2 Pr1/R1 Pr2/R2 FSEL0 FSEL1 GND GND 0dB_SEL Input Input Input Input Input Input Input Input Input Input Input 14 15 16 17 Pr/ROUT Pb/BOUT Y/GOUT IN2_SEL Output Output Output Input 18 SYNC_IN Input 19 20 VCC VCC Input Input 8 REV. 1C March 2005 FMS6403 DATA SHEET Gain Settings 0dB_SEL, Pin 13 0 1 above ground. Sync Settings Gain (dB) 6 VIN* 1Vpp 1Vpp VOUT* 2Vpp 1Vpp EXT_SYNC, Pin1 0 1 Sync Source Y/G input, Pin 3/4 0 SYNC_IN input, Pin 2 * Video level, does not include clamp voltage which will offset the input Filter Settings FSEL1, Pin 10 0 0 1 1 FSEL0, Pin 9 0 Filter -3dB Freq 8MHz 15MHz 32MHz Filter Bypass Video Format SD, 480i PS, 480p HD, 1080i, 720p Unfiltered 1080p Sync Format Bi-level, 4.7µs pulse width Bi-level, 2.35µs pulse width Tri-level, 589ns pulse width Tri-level, 290ns, pulse width 1 0 1 Clamp Settings RGB_SEL, Pin 2 0 Input Y1, Pin 3 Pb1, Pin 5 Pr1, Pin 7 1 G1, Pin 3 B1, Pin 5 R1, Pin 7 Output Y, Pin 16 Pb, Pin 15 Pr, Pin 14 G, Pin 16 B, Pin 15 R, Pin 14 Clamp Voltage 250mV 1.125V 1.125V 250mV 250mV 250mV REV. 1C March 2005 9 DATA SHEET FMS6403 Functional Description Introduction The FMS6403 is a next generation filter solution from Fairchild Semiconductor addressing the expanding filtering needs for televisions, set top boxes, and DVD players including progressive scan capability. The product provides selectable filtering with cutoff frequencies of 30MHz, 15MHz, and 8.0MHz for all three channels. In addition, the filters can be bypassed for wider bandwidth applications. The FMS6403 allows consumer devices to support a variety of resolution standards with the same hardware. Multiplexers on the channel inputs are controlled by the IN2_SEL pin. The RGB_SEL pin can be used to set the sync tip clamp voltages for YPbPr or RGB applications. All three channels are set for 250mV sync tips to reduce DC-coupled power dissipation for RGB inputs. The lower output bias voltage is not suitable for the PbPr outputs so for YPbPr inputs these signals are clamped to 1.125V while Y is still clamped to 250mV. Sync tip clamping voltages are set by forcing the desired DC bias level during the active sync period. For systems without sync on Y/G, an external sync input is provided. If sync exists on one input Y/G signal but not on the other Y/G input signal, the IN2_SEL and EXT_SYNC control inputs may be wired together on the PCB to switch the sync source with the input source. Both standard definition (bi-level) and high definition (trilevel) sync are supported at the Y/G inputs and SYNC_IN depending on the FSEL[1:0] inputs. See the Sync Processing section for further details. Standard definition (480i) and progressive (480p) signals are clamped by forcing the signal to the desired voltage during the sync pulse. For signals with sync, the sync tip itself will be forced to the clamp voltage (typically 250mV). When high definition sync is present (tri-level sync) the sync tip duration is too short to allow this approach. In order to accurately clamp HD signals, the sync pulse starts a timer and the actual clamping is done at the blanking level right after the sync pulse. The sync tip will still typically be placed at 250mV if its amplitude is 300mV. All three outputs are driven by amplifiers with selectable gains of 0dB or +6dB. The gain is set with the 0dB_SEL pin. These amplifiers can drive two terminated video loads (75Ω) to 2Vpp with a 1Vpp input when set to 6dB gain. The input range is limited to 1.5Vpp and the output range is limited to 2.5Vpp. All control inputs must be driven high or low. Do not leave them floating. not include sync, the FMS6403 can be used in External SYNC Mode. When the FMS6403 is used in external sync mode, (EXT_SYNC pin is high), a pulsed input must be applied to the SYNC_IN pin. If there is no video signal present, therefore no sync signal present, there must still be an input applied to the SYNC_IN pin. When there is no video signal on the video inputs SYNC_IN can be a sync pulse every 60µs to mimic the slowest sync in a regular video signal. The following two sections discuss the sync processing and timing required in more detail. SD and Progressive Scan Video Sync Processing The FMS6403 must control the DC offset of AC-coupled input signals since the average DC level of video varies with image content. If the input offset is allowed to wander, the common mode input range of the amplifiers can be exceeded leading to signal distortion. DC offset adjustment is referred to as clamping or in some cases, biasing, and must be done at the correct time during each video line. The optimum time is during the sync pulse since it is the lowest input voltage. This approach works well for 480i and 480p signals since the sync tip duration is long enough to allow the DC-offset errors to be compensated from line to line. The DC-offset of the sync tip is adjusted as illustrated in Figure 12 by forcing a current on the input during the sync pulse. The sync tip will be clamped to approximately 250mV. Signals like Pb and Pr with a symmetric voltage range (±350mV) will be clamped to approximately 1.125V. Note that the following diagrams illustrate DC restore functionality and indicate output voltage levels for both 0dB and 6dB gain (1Vpp and 2Vpp video signals at the FMS6403 output pin). 0dB Gain 6dB 1475mV 1875mV 1125mV 1125mV 775mV 425mV Required Pb Offset 1250mV 2250mV Av = 1 (0dB) or 2 (6dB) Av*700mV 550mV 250mV 0mV 850mV 250mV 0mV Active Active Video Av*300mV Required Sync Tip Offset Figure 12. Bi-Level Sync Tip Clamping and Bias In some cases, the sync voltage may be compressed to less than the nominal 300mV value. The FMS6403 can successfully recover SD and Progressive Scan sync which is greater than 100mV (compressed to 33% of nominal). The FMS6403 can properly recover sync timing from luma and green which include sync. If none of the video signals External SYNC Mode The FMS6403 can properly recover sync timing from video signals that include sync. If the Y-input video signals does 10 REV. 1C March 2005 FMS6403 DATA SHEET includes sync, the EXT_SYNC control input can be set high and an external sync signal must be input on the SYNC_IN pin. Refer to the External Sync section for more details. The timing required for this operating mode is shown in Figure 13. SYNC timings, T1 and T2, are defined in the SD Electrical Specifications table on page 2. 0dB Gain 6dB 950mV 1650mV Av = 1 (0dB) or 2 (6dB) NOTE: Tri-level sync may only be compressed 5%. If HD sync is compressed more than 5% it may not be properly located. Sync Timing Normally, the FMS6403 will respond to bi-level sync and clamp the sync tip during period ‘B’ in Figure 15(a). When the filters are switched to high definition mode (30MHz) or bypass mode the sync processing will respond to tri-level sync and clamp to the blanking level during period ‘C’ in Figure 15(b). NOTE: The diagram indicates SYNC timings at the output pin. Av*700mV 250mV 0mV 250mV 0mV Active Video Required Blanking Offset True Sync Position T1 Allowable SYNC_IN T2 (a) 2250mV Figure 13. Bi-Level External Sync Clamping and Bias 850mV 480i and 480p HD and Bypass Mode Video Sync Processing When the input signal is a high definition signal, the tri-level sync pulse is too short to allow proper clamp operation. Rather than clamp during the sync pulse, the sync pulse is located and the signal is clamped to the blanking level. This is done in such a way that the sync tip will still be set to approximately 250mV for signals with 300mV sync tip amplitude. The EXT_SYNC control input selects the sync stripper output or the SYNC_IN pin for use by the clamp circuit. NOTE: The SYNC_IN timing for HD signals is different than the timing for SD or PS signals. For HD signals, the SYNC_IN signal must be high when the clamp must be active. This is during the time immediately after the sync pulse while the signal is at the blanking level. This operation is shown in Figure 14. Note that the following diagrams illustrate DC restore functionality and indicate output voltage levels for both 0dB and 6dB gain (1Vpp and 2Vpp video signals at the FMS6403 output pin). SYNC timings, T1 and T2, are defined in the HD Electrical Specifications table on page 3. 0dB Gain 6dB 1250mV 2250mV Av = 1 (0dB) or 2 (6dB) 250mV A B C (b) 2250mV 720p, 1080i, 1080p 1450mV 850mV 250mV A B B C Figure 15. Sync Timing; Bi-Level (a), Tri-Level (b) The tri-level sync pulse is located such that the broad pulses in the vertical interval do not trigger the clamp. In order to improve the system settling at turn-on, the broad pulses will be clamped to just above ground. Once the broad pulses (and tri-level sync tips) are above ground, the normal clamping process takes over and clamps to the blanking level during period ‘C’ in Figure 15(b). The FMS6403 is designed to support the video standards and associated sync timings shown in Table 1, (additional standards such as 483p59.94 will also work correctly). The Filter Settings table from page 9 is repeated on page 12 for convenience.. 850mV 1450mV 550mV 250mV 0mV 850mV 250mV 0mV True Sync Position 0H Av*700mV Active Video Av*300mV Av*300mV Required Sync Tip Offset (Next Sync Tip Will Be Offset Correctly) T1 Allowable SYNC_IN T2 Figure 14. Tri-Level Blanking Clamp REV. 1C March 2005 11 DATA SHEET FMS6403 Filter Settings FSEL1, Pin 10 0 0 1 1 Table I Format 480i 480p 720p 1080i 1080p Refresh 30Hz 60Hz 60Hz 30Hz 60Hz FSEL0, Pin 9 0 Filter -3dB Freq 8MHz 15MHz 32MHz Filter Bypass Video Format SD, 480i PS, 480p HD, 1080i, 720p Unfiltered 1080p Sync Format Bi-level, 4.7µs pulse width Bi-level, 2.35µs pulse width Tri-level, 589ns pulse width Tri-level, 290ns, pulse width 1 0 1 Sample Rate 13.5MHz 27MHz 74.25MHz 74.25MHz 148.5MHz Period (T) 74ns 37ns 13.4ns 13.4ns 6.7ns A 20T = 1.5µs 20T = 750ns 70T = 938ns 44T = 589ns 44T = 296ns B 64T = 4.7µs 64T = 2.35µs 40T = 536ns 44T = 589ns 44T = 296ns C 61T = 4.5µs 61T = 2.25µs 220T = 2.95µs 148T = 1.98µs 148T = 996ns H-Rate 15.75kHz 31.5kHz 45kHz 33.75kHz 67.5kHz Note: Timing values are approximate for 30Hz/60Hz refresh rates. Application Information Input Circuitry The DC restore circuit in the FMS6403 requires a source impedance (Rsource = Rs || RT) of less than or equal to 150Ω for correct operation. Driving the FMS6403 with a highimpedance source (e.g. a DAC loaded with 330Ω) will not yield optimum results. Refer to the Typical Application Circuit diagram on page 13 for more details. The 220uF capacitor coupled with the 150Ω termination, as shown in the Typical Application Circuit of Figure 5, forms a high pass filter that blocks the DC while passing the video frequencies and avoiding tilt. Any value lower than 220µF will create problems, such as video tilt. Higher values, such as 470µF - 1000µF are the most optimal output coupling capacitor. By AC coupling, the average DC level is zero. Thus, the output voltages of all channels will be centered around zero. Output Drive The FMS6403 is specified to operate with output currents typically less than 60mA, more than sufficient for a dual (75Ω) video load. Internal amplifiers are current limited to approximately 100mA and should withstand brief duration short circuit conditions, however this capability is not guaranteed. The maximum specified input voltage of 1.5Vpp can be sustained for all inputs. When the input is clamped to 1.125V, this does not result in a meaningful output signal. With a gain of 6dB, the output should be 1.125V ±1.5V which is not possible since the output cannot drive below ground. This condition will not damage the part; however, the output will be clipped. For signals which are clamped to 250mV, this does not occur. Signals that are at midscale during SYNC (Pb and Pr) must be clamped to 1.125V and signals that are at their lowest during SYNC (Y, R, G, B) must be clamped to 250mV for proper operation. Clamping a Pr signal to 250mV will result in clipping the bottom of the signal. Sync Recovery The FMS6403 will typically recover bi-level sync with amplitude greater than 100mV (33% compressed relative to the nominal 300mV amplitude). The FMS6403 looks for the lowest signal voltage and clamps this to approximately 250mV at the output. Tri-level sync may not be compressed more than 5% (15mV) for correct operation. Tri-level sync is located by finding the edges of the tri-level pulse and running a timer to operate the clamp during the back porch interval. The selection of the 8MHz or 15MHz filters enables bi-level sync recovery. Selection of the 30MHz filter or bypass mode enables tri-level sync recovery. Bi-level and tri-level sync recovery are not interchangeable. See the detailed sync processing section for more information. 12 REV. 1C March 2005 FMS6403 DATA SHEET Power Dissipation TheFMS6403 output drive configuration must be considered when calculating overall power dissipation. Care must be taken not to exceed the maximum die junction temperature. The following example can be used to calculate the FMS6403’s power dissipation and internal temperature rise. Tj = TA + Pd • ΘJA where Pd = PCH1 + PCH2 + PCH3 and PCHx = Vs • ICH - (VO2/RL) where VO = 2Vin + 0.280V ICH = (ICC / 3) + (VO/RL) Vin = RMS value of input signal ICC = 90mA Vs = 5V RL = channel load resistance Board layout can also affect thermal characteristics. Refer to the Layout Considerations Section for more information. The FMS6403 is specified to operate with output currents typically less than 60mA, more than sufficient for a single (150Ω) video load. Internal amplifiers are current limited to a maximum of 100mA and should withstand brief duration short circuit conditions, however this capability is not guaranteed. use as a guide for layout and to aid in device testing and characterization. The FMS6403DEMO is a 4-layer board with a full power and ground plane. For optimum results, follow the steps below as a basis for high frequency layout: • • • • • Include 10µF and 0.1µF ceramic bypass capacitors Place the 10µF capacitor within 0.75 inches of the power pin Place the 0.1µF capacitor within 0.1 inches of the power pin Connect all external ground pins as tightly as possible, preferably with a large ground plane under the package Layout channel connections to reduce mutual trace inductance Minimize all trace lengths to reduce series inductances. If routing across a board, place device such that longer traces are at the inputs rather than the outputs. • If using multiple, low impedance DC coupled outputs, special layout techniques may be employed to help dissipate heat. For dual-layer boards, place a 0.5” to 1” (1.27cm to 2.54cm) square ground plane directly under the device and on the bottom side of the board. Use multiple vias to connect the ground planes. For multi-layer boards, additional planes (connected with vias) can be used for additional thermal improvements. Worse case additional die power due to DC loading can be estimated at (VCC2/4Rload) per output channel. This assumes a constant DC output voltage of VCC2. For 5V VCC with a dual DC video load, add 25/(4*75) = 83mW, per channel. Layout Considerations General layout and supply bypassing play major roles in high frequency performance and thermal characteristics. Fairchild offers a demonstration board, FMS6403DEMO, to REV. 1C March 2005 13 DATA SHEET FMS6403 Y1/G1 Rs 75Ω RT 75Ω 0.1µF 3 Y1/G1 VCC VCC 20 19 +5V 0.1µF 1µF Y2/G2 Rs 75Ω RT 75Ω 0.1µF 4 FMS6403 20L TSSOP Y2/G2 Y/GOUT 16 75Ω May also be DC coupled 220µF 75Ω Video Cables 75Ω Pb1/B1 Rs 75Ω RT 75Ω 0.1µF 5 Pb1/B1 Pb/BOUT 15 75Ω 220µF 75Ω Video Cables 75Ω Pb2/B2 Rs 75Ω RT 75Ω 0.1µF 6 Pb2/B2 Pr/ROUT 14 75Ω 220µF 75Ω Video Cables 75Ω 0.1µF 7 Pr1/R1 Rs 75Ω RT 75Ω Pr1/R1 Pr2/R2 Rs 75Ω RT 75Ω 0.1µF 8 GND Pr2/R2 GND Note: Pins 1, 2, 9, 10, 13, 17, and 18 will need to be set according to the input signal format 12 11 Figure 16. Typical Application Circuit 14 REV. 1C March 2005 FMS6403 DATA SHEET Package Dimensions TSSOP-20 6 N 5 e –B– 7 2X E/2 1.0 DIA 1.0 (b) 8 TSSOP-20 c1 SYMBOL A A1 A2 L R R1 b b1 c c1 01 L1 aaa bbb ccc ddd e 02 03 D E1 E e N MIN – 0.05 0.85 0.50 0.09 0.09 0.19 0.19 0.09 0.09 0° NOM – – 0.90 0.60 – – – 0.22 – – – 1.0 REF 0.10 0.10 0.05 0.20 0.65 BSC 12° REF 12° REF 6.50 4.40 6.4 BSC 0.65 BSC 20 MAX 1.10 0.15 0.95 0.75 – – 0.30 0.25 0.20 0.16 8° E1 E c b1 ddd C B A 2X N/2 TIPS 123 6 1.0 e /2 9 SECTION AA ccc 7 –A– D8 3 A2 A aaa C –C– b NX bbb M C B A A1 (02) (0.20) R1 –H– R GAGE PLANE 10 6.50 4.30 6.60 4.50 A A 0.25 (03) L (L1) 01 NOTES: 1 All dimensions are in millimeters (angle in degrees). 2 3 4 5 Dimensioning and tolerancing per ASME Y14.5–1994. Dimensions "D" does not include mold flash, protusions or gate burrs. Mold flash protusions or gate burrs shall not exceed 0.15 per side . Dimension "E1" does not include interlead flash or protusion. Interlead flash or protusion shall not exceed 0.25 per side. Dimension "b" does not include dambar protusion. Allowable dambar protusion shall be 0.08mm total in excess of the "b" dimension at maximum material condition. Dambar connot be located on the lower radius of the foot. Minimum space between protusion and adjacent lead is 0.07mm for 0.5mm pitch packages. Terminal numbers are shown for reference only. Datums – A – and – B – to be determined at datum plane – H – . Dimensions "D" and "E1" to be determined at datum plane – H – . This dimensions applies only to variations with an even number of leads per side. For variation with an odd number of leads per side, the "center" lead must be coincident with the package centerline, Datum A. 6 7 8 9 10 Cross sections A – A to be determined at 0.10 to 0.25mm from the leadtip. REV. 1C March 2005 15 DATA SHEET FMS6403 Ordering Information Model FMS6403 FMS6403 Part Number FMS6403MTC20_NL FMS6403MTC20X_NL Lead Free Yes Yes Package TSSOP-20 TSSOP-20 Container Tube Tape and Reel Pack Qty 94 2500 Temperature range for all parts: 0°C to +70°C. 16 REV. 1C March 2005 FMS6403 DATA SHEET www.fairchildsemi.com © 2005 Fairchild Semiconductor Corporation