FOD2200T

FOD2200 — Low Input Current Logic Gate Optocouplers August 2008 FOD2200 Low Input Current Logic Gate Optocouplers Features ■ 1kV/µs minimum common mode rejection ■ Compatible with LSTTL, TTL, and CMOS logic ■ Wide VCC range (4.5V to 20V) ■ 2.5Mbd guaranteed over temperature ■ Low input current (1.6mA) ■ Three state output (no pullup resistor required) ■ Guaranteed performance from 0°C to 85°C ■ Hysteresis ■ Safety approvals pending – UL, CSA, VDE ■ VISO = 5kVRMS Description The FOD2200 is an optically coupled logic gate that combine an AlGaAs LED and an integrated high gain photo detector. The detector has a three state output stage and has a detector threshold with hysteresis. The three state output eliminates the need for a pullup resistor and allows for direct drive of data busses. The hysteresis provides differential mode noise immunity and eliminates the potential for output signal chatter. The Electrical and Switching Characteristics of the FOD2200 are guaranteed over the temperature range of 0°C to 85°C and a VCC range of 4.5V to 20V. Low IF and wide VCC range allow compatibility with TTL, LSTTL, and CMOS logic and result in lower power consumption compared to other high speed opto-couplers. Logic signals are transmitted with a maximum propagation delay of 300ns. The FOD2200 is useful for isolating high speed logic interfaces, buffering of input and output lines, and implementing isolated line receivers in high noise environments. Applications ■ Isolation of high speed logic systems ■ Computer peripheral interfaces ■ Microprocessor system interfaces ■ Ground loop elimination ■ Pulse transformer replacement ■ Isolated bus driver ■ High speed line receiver Truth Table (Positive Logic) LED On Off On Off Enable H H L L Output Z Z H L Functional Block Diagram and Schematic ICC NC 1 ANODE 2 CATHODE 3 NC 4 8 VCC 7 VO 6 VE 5 GND Package Outlines VCC 8 1 8 IF + VF – 2 IE 3 SHIELD 6 5 IO 7 VO VE GND 8 1 8 1 SHIELD ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.1 www.fairchildsemi.com FOD2200 — Low Input Current Logic Gate Optocouplers Absolute Maximum Ratings (TA = 25°C unless otherwise specified) Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol TSTG TOPR TSOL EMITTER IF (PK) IF VR PD DETECTOR VCC IO VE VO PD Supply Voltage Average Output Current Storage Temperature Operating Temperature Parameter Value -40 to +125 -40 to +85 260 for 10 sec 1.0 10 5.0 45 0 to 20 25 -0.5 to 20 -0.5 to 20 150 Units °C °C °C A mA V mW V mA V V mW Lead Solder Temperature (1.6mm below seating plane) Peak Transient Input Current (≤1µs PW, 300pps) Average Forward Input Current Reverse Input Voltage Output Power Dissipation (No derating required up to 85°C) Three State Enable Voltage Output Voltage Output Power Dissipation (No derating required up to 85°C) Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol IF(ON) IF(OFF) VCC VEL VEH TA N Parameter Forward Input Current Forward Input Current Supply Voltage, Output Enable Voltage, LOW Level Enable Voltage, HIGH Level Operating Temperature Fan Out (TTL Load) Min. 1.6* 4.5 0 2.0 0 Max. 5 0.1 20 0.8 20 +85 4 Units mA mA V V V °C *The initial switching threshold is 1.6mA or less. It is recommended that 2.2mA be used to permit at least a 20% CTR degradation guardband. ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.1 www.fairchildsemi.com 2 FOD2200 — Low Input Current Logic Gate Optocouplers Electrical Characteristics (TA = 0°C to +85°C, VCC = 4.5V to 20V, IF(ON) = 1.6mA to 5mA, VEH = 2V to 20V, VEL = 0V to 0.8V, IF(OFF) = 0 mA to 0.1mA unless otherwise specified.)(1) Individual Component Characteristics Symbol EMITTER VF BVR CIN Input Forward Voltage Input Reverse Breakdown Voltage Input Capacitance IF = 5mA TA = 25°C IR = 10µA Pins 2 & 3, VF = 0, f = 1MHz IF = 5mA 5.0 60 -1.4 1.40 1.75 1.7 V pF mV/°C V Parameter Test Conditions Min. Typ.* Max. Unit ∆VF/∆TA Input Diode Temperature Coefficient DETECTOR ICCH ICCL IEL IEH High Level Supply Current Low Level Supply Current Low Level Enable Current High Level Enable Current IF = 5mA, IO = Open, VE = Don’t Care IF = 0, IO = Open, VE = Don’t care VE = 0.4V VE = 2.7V VE = 5.5V VE = 20V VCC = 5.5V VCC = 20V VCC = 5.5V VCC = 20V 3.5 4.0 4.4 5.2 -0.1 4.5 6.0 6.0 7.5 -0.32 20 100 mA mA mA µA 0.005 2.0 250 V 0.8 V VEH VEL High Level Enable Voltage Low Level Enable Voltage Switching Characteristics (TA = 0°C to +85°C, IF(ON) = 1.6mA to 5mA, IF(OFF) = 0 to 0.1mA, VCC = 4.5V to 20V unless otherwise specified.) Symbol TPLH TPHL tr tf tPZH tPZL TPHZ TPLZ |CMH| AC Characteristics Propagation Delay Time to Output High Level Propagation Delay Time to Output Low Level Output Rise Time (10% to 90%) Output Fall Time (90% to 10%) Enable Propagation Delay Time to Output High Level Enable Propagation Delay Time to Output Low Level Disable Propagation Delay Time from Output High Level Disable Propagation Delay Time from Output Low Level Test Conditions With Peaking Capacitor(2)(4) (Fig. 1) Min. Typ.* 120 180 80 25 40 50 95 80 Max. Unit 300 300 ns ns ns ns ns ns ns ns V/µs With Peaking Capacitor(3)(4) (Fig. 1) (5) (6) (Fig. 1) (Fig. 1) (Fig. 2) (Fig. 2) (Fig. 2) (Fig. 2) Common Mode Transient Immunity TA =25°C, IF = 1.6mA, |VCM| = 50V 1000 (at Output High Level) VOH (Min.) = 2.0V, VCC = 5V(7) (Fig. 3) Common Mode Transient Immunity (at Output Low Level) TA =25°C, IF = 0mA, VOL (Max.) = 0.8 V, VCC = 5V(8) (Fig. 3) |VCM| = 50V 1000 |CML| V/µs *Typical values at TA = 25°C, VCC = 5V, IF(ON) = 3mA unless otherwise specified. ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.1 www.fairchildsemi.com 3 FOD2200 — Low Input Current Logic Gate Optocouplers Electrical Characteristics (Continued) Transfer Characteristics (TA = 0°C to +85°C, VCC = 4.5V to 20V, IF(ON) = 1.6mA to 5mA, VEH = 2V to 20V, VEL = 0V to 0.8V, IF(OFF) = 0mA to 0.1mA unless otherwise specified.)(1) Symbol IOHH VOL IFT VOH IOZL IOZH DC Characteristics Output Leakage Current (VOUT > VCC) Low Level Output Voltage Input Threshold Current Logic High Output Voltage High Impedance State Output Current High Impedance State Output Current Test Conditions VCC = 4.5V, IF = 5mA VO = 5.5V VO = 20V VCC = 4.5 V, IF = 0mA, VE = 0.4 V, IOL = 6.4mA(2) VCC = 4.5V, VO = 0.5V, VE = 0.4V, IOL = 6.4mA IOH = -2.6mA VO = 0.4V, VEN = 2V, IF = 5mA VO = 2.4 V, VEN = 2 V, IF = 5mA VO = 5.5 V, VEN = 2 V, IF = 5mA VO = 20 V, VEN = 2 V, IF = 5mA VO = VCC = 5.5V, IF = 0mA VO = VCC = 20V, IF = 0mA VCC = 5.5V, IF = 5mA, VO = GND VCC = 20V, IF = 5mA, VO = GND VCC = 4.5V Min. Typ.* 2.0 2.5 0.33 Max. 100 500 0.5 1.6 Unit µA V mA V 2.4 VCC – 1.8 -20 20 100 500 µA µA IOSL IOSH IHYS Logic Low Short Circuit Output Current(10) Logic High Short Circuit Output Current(10) Input Current Hysteresis 25 40 -10 -25 0.03 mA mA mA Isolation Characteristics (TA = 0°C to +85°C unless otherwise specified) Symbol VISO RI-O CI-O Characteristics Withstand Insulation Test Voltage Resistance (Input to Output) Capacitance (Input to Output) VI-O = Test Conditions RH < 50%, TA = 25°C, t = 1 500 VDC(9) VI-O = 0V, f = 1MHz(9) min.(9) Min. 5000 Typ.* 1012 0.6 Max. Unit VRMS Ω pF *Typical values at TA = 25°C, VCC = 5V, IF(ON) = 3mA unless otherwise stated. Notes: 1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC and GND pins of each device. 2. tPLH – Propagation delay is measured from the 50% level on the LOW to HIGH transition of the input current pulse to the 1.3V level on the LOW to HIGH transition of the output voltage pulse. 3. tPHL – Propagation delay is measured from the 50% level on the HIGH to LOW transition of the input current pulse to the 1.3V level on the HIGH to LOW transition of the output voltage pulse. 4. When the peaking capacitor is omitted, propagation delay times may increase by 100ns. 5. tr – Rise time is measured from the 10% to the 90% levels on the LOW to HIGH transition of the output pulse. 6. tf – Fall time is measured from the 90% to the 10% levels on the HIGH to LOW transition of the output pulse. 7. CMH – The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the high state (i.e., VOUT > 2.0V). 8. CML – The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low state (i.e., VOUT < 0.8V). 9. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted together. 10. Duration of output short circuit time should not exceed 10ms. ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.1 www.fairchildsemi.com 4 FOD2200 — Low Input Current Logic Gate Optocouplers Test Circuits PULSE GEN. t r = t f = 5 ns f = 100 kHz 10 % DUTY CYCLE VO = 5 V IF INPUT MONITORING NODE R1 VCC OUTPUT VO MONITORING NODE FOD2200 1 2 3 5V D1 619 Ω VCC 8 7 6 C2 = 15 pF 5 kΩ D2 D3 D4 4 C1 = 120 pF GND 5 THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C 1 AND C2. 2.15 kΩ 1.10 kΩ 681 Ω RI 5 mA IF (ON) 1.6 mA 3 mA ALL DIODES ARE 1N916 OR 1N3064. INPUT IF IF (ON) 50 % IF (ON) 0 mA t PLH t PHL OUTPUT VO VOH 1.3 V VOL Fig. 1. Test Circuit and Waveforms for tPLH, tPHL, tr and tf PULSE GENERATOR ZO = 50 Ω t r = t f = 5 ns 1 CL = 15 pF INCLUDING PROBE AND JIG CAPACITANCES . VCC FOD2200 VCC 8 D1 7 6 +5 V VO S1 619 Ω IF 2 3 4 CL 5 kΩ D2 D3 D4 S2 GND 5 INPUT VC MONITORING NODE D1-4 ARE 1N916 OR 1N3064. INPUT VE t PZL 1.3 V t PLZ 0.5 V 0.5 V 1.3 V 0V t PHZ 3.0 V 1.3 V 0V S1 AND S2 CLOSED VOL VOH ≈1.5 V S1 AND S2 CLOSED OUTPUT S1 CLOSED VO S2 OPEN t PZH OUTPUT VO S1 OPEN S2 CLOSED Fig. 2. Test Circuit and Waveforms for tPHZ, tPZH, tPLZ, and tPZL ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.1 www.fairchildsemi.com 5 FOD2200 — Low Input Current Logic Gate Optocouplers Test Circuits (Continued) FOD2200 A B 1 2 3 VCC OUTPUT VO MONITORING NODE 0.1 µF BYPASS VCC 8 7 6 5 RIN VFF 4 GND VCM – PULSE GENERATOR + VCM 0V VOH OUTPUT VO VOL * SEE NOTE 6. 50 V SWITCH AT A: I F = 1.6mA VO (MIN.)* SWITCH AT B: I F = 0mA VO (MAX.)* Fig. 3. Test Circuit and Typical Waveforms for Common Mode Transient Immunity VCC1 (+5V) VCC1 (+5V) 1.1 kΩ 120pF FOD2200 1 2 DATA INPUT TOTEM POLE OUTPUT GATE 1 2 120pF (OPTIONAL*) 1.1 kΩ FOD2200 1 2 VCC2 (+5V) DATA OUTPUT VCC2 (4.5V TO 20V) VCC 8 7 6 GND 5 VCC 8 7 6 RL CMOS DATA OUTPUT 3 TTL OR LSTTL 4 UP TO 16 LSTTL LOADS OR 4 TTL LOADS DATA INPUT TOTEM POLE OUTPUT GATE 1 3 TTL OR LSTTL 4 GND 5 VCC2 5V 10V 15V 20V RL 1.1kΩ 2.37kΩ 3.83kΩ 5.11kΩ 2 Figure 4. Recommended LSTTL to LSTTL Circuit Figure 5. LSTTL to CMOS Interface Circuit VCC (+5 V) VCC1 (+5 V) 1.1kΩ DATA INPUT TTL OR LSTTL D1 FOD2200 120pF (OPTIONAL*) 1.1 kΩ FOD2200 1 2 3 1 2 3 4 VCC 8 VCC 8 7 6 7 6 GND DATA INPUT OPEN COLLECTOR GATE 4.7k Ω TTL OR LSTTL 5 4 GND 5 D1 (1N4150) REQUIRED FOR ACTIVE PULL-UP DRIVER. Figure 6. Recommended LED Drive Circuit Figure 7. Series LED Drive with Open Collector Gate (4.7kΩ Resistor Shunts IOH from the LED) *The 120pF capacitor may be omitted in applications where 500ns propagation delay is sufficient. ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.1 www.fairchildsemi.com 6 FOD2200 — Low Input Current Logic Gate Optocouplers Typical Performance Curves Figure 8. Input Forward Current vs Forward Voltage 100 IF – FORWARD CURRENT (mA) 5 VCC = 4.5V TA = 25°C 10 TA = 85°C 1 TA = 70°C TA = 25°C 0.1 TA = 0°C TA = -40°C VO – Output Voltage (V) 4 Figure 9. Output Voltage vs. Input Forward Current 3 IO = -2.6mA 2 IF(OFF) 1 IO = 6.4mA IF(ON) 0.01 0.001 0.9 1.0 1.1 1.2 1.3 1.4 1.5 V F – FORWARD VOLTAGE (V) 1.6 1.7 0 0.0 0.2 0.4 0.6 0.8 1.0 IF – INPUT FORWARD CURRENT (mA) 1.2 Figure 10. Input Threshold Current vs. Ambient Temperature INPUT CURRENT THRESHOLD (mA) VOL – LOGIC LOW OUTPUT VOLTAGE (V) 1.2 VCC = 5V, 20V 1.0 0.8 IF(ON) 0.6 0.4 0.2 0.0 -40 IF(OFF) Figure 11. Logic Low Output Voltage vs. Ambient Temperature 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -40 -20 0 20 40 60 80 TA – AMBIENT TEMPERATURE (°C) 100 VCC = 4.5V IF = 0 mA IO = 6.4 mA -20 0 20 40 60 TA – Ambient Temperature (°C) 80 100 VOH – LOGIC HIGH OUTPUT VOLTAGE (V) IOH – LOGIC HIGH OUTPUT CURRENT (mA) Figure 12. Logic High Output Voltage vs. Supply Voltage 20 IO = -2.6 mA TA = 25°C IF ≥ IF (ON) Figure 13. Logic High Output Current vs. Ambient Temperature 0 -1 -2 VO = 2.7V -3 -4 VO = 2.4V -5 -6 -7 -40 VCC = 4.5V IF = 5 mA 16 12 8 4 0 0 4 8 12 16 VCC – SUPPLY VOLTAGE (V) 20 -20 0 20 40 60 80 TA – AMBIENT TEMPERATURE (°C) 100 Figure 14. Propagation Delay vs Ambient Temperature 260 tP – PROPAGATION DELAY (µs) VCC = 5V C1 (120pF) Peaking Capacitor Is Used. See Figure 1. 200 tf, tr – RISE, FALL TIME (µs) Figure 15. Rise, Fall Time vs Ambient Temperature VCC = 5V IF = 1.6mA 160 220 180 tPHL, IF = 3mA tPHL, IF = 5mA tPHL, IF = 1.6mA 120 tr 140 80 100 tPLH, IF = 1.6mA–5mA 40 tf 60 -40 -20 0 20 40 60 80 TA – AMBIENT TEMPERATURE (°C) 100 0 -40 -20 0 20 40 60 80 TA – AMBIENT TEMPERATURE (°C) 100 ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.1 www.fairchildsemi.com 7 FOD2200 — Low Input Current Logic Gate Optocouplers Package Dimensions Through Hole PIN 1 ID. 4 3 2 1 4 3 2 1 0.4" Lead Spacing PIN 1 ID. 0.270 (6.86) 0.250 (6.35) 5 6 7 8 0.270 (6.86) 0.250 (6.35) 0.390 (9.91) 0.370 (9.40) 5 6 7 8 SEATING PLANE 0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.140 (3.55) 0.020 (0.51) MIN SEATING PLANE 0.390 (9.91) 0.370 (9.40) 0.070 (1.78) 0.045 (1.14) 0.200 (5.08) 0.140 (3.55) 0.004 (0.10) MIN 0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP 0.016 (0.40) 0.008 (0.20) 15° MAX 0.300 (7.62) TYP 0.154 (3.90) 0.120 (3.05) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP 0.016 (0.40) 0.008 (0.20) 0° to 15° 0.400 (10.16) TYP Surface Mount 0.390 (9.91) 0.370 (9.40) 4 3 2 1 8-Pin DIP – Land Pattern 0.070 (1.78) PIN 1 ID. 0.270 (6.86) 0.250 (6.35) 0.060 (1.52) 5 6 7 8 0.100 (2.54) 0.295 (7.49) 0.415 (10.54) 0.030 (0.76) 0.070 (1.78) 0.045 (1.14) 0.020 (0.51) MIN 0.300 (7.62) TYP 0.016 (0.41) 0.008 (0.20) 0.022 (0.56) 0.016 (0.41) 0.100 (2.54) TYP Lead Coplanarity : 0.004 (0.10) MAX 0.045 (1.14) 0.315 (8.00) MIN 0.405 (10.30) MAX. Note: All dimensions are in inches (millimeters) ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.1 www.fairchildsemi.com 8 FOD2200 — Low Input Current Logic Gate Optocouplers Ordering Information Option No Option S SD T V TV SV SDV Example Part Number FOD2200 FOD2200S FOD2200SD FOD2200T FOD2200V FOD2200TV FOD2200SV FOD2200SDV Description Standard Through Hole Surface Mount Lead Bend Surface Mount; Tape and Reel 0.4" Lead Spacing VDE0884 VDE0884; 0.4” Lead Spacing VDE0884; Surface Mount VDE0884; Surface Mount; Tape and Reel Marking Information 1 2200 V 3 4 2 6 XX YY B 5 Definitions 1 2 3 4 5 6 Fairchild logo Device number VDE mark (Note: Only appears on parts ordered with VDE option – See order entry table) Two digit year code, e.g., ‘03’ Two digit work week ranging from ‘01’ to ‘53’ Assembly package code ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.1 www.fairchildsemi.com 9 FOD2200 — Low Input Current Logic Gate Optocouplers Carrier Tape Specifications D0 K0 t P0 P2 E A0 W1 B0 F W d User Direction of Feed P D1 Symbol W t P0 D0 E F P2 P A0 B0 K0 W1 d R Pocket Pitch Tape Width Description Tape Thickness Sprocket Hole Pitch Sprocket Hole Diameter Sprocket Hole Location Pocket Location Dimension in mm 16.0 ± 0.3 0.30 ± 0.05 4.0 ± 0.1 1.55 ± 0.05 1.75 ± 0.10 7.5 ± 0.1 4.0 ± 0.1 12.0 ± 0.1 10.30 ±0.20 10.30 ±0.20 4.90 ±0.20 Pocket Dimensions Cover Tape Width Cover Tape Thickness Max. Component Rotation or Tilt Min. Bending Radius 1.6 ± 0.1 0.1 max 10° 30 Reflow Profile 300 Temperature (°C) 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Time (Minute) • Peak reflow temperature: 260 C (package surface temperature) • Time of temperature higher than 183 C for 160 seconds or less • One time soldering reflow is recommended ©2004 Fairchild Semiconductor Corporation FOD2200 Rev. 1.0.1 www.fairchildsemi.com 10 245 C, 10–30 s 260 C peak Time above 183C,