FSAL200_06

FSAL200 Wide Bandwidth Quad 2:1 Analog Multiplexer / Demultiplexer Switch June 2006 FSAL200 Wide Bandwidth Quad 2:1 Analog Multiplexer / Demultiplexer Switch Features ■ Typical 6Ω switch connection between two ports ■ Minimal propagation delay through the switch ■ Low ICC ■ Zero bounce in flow-through mode ■ Control inputs compatible with TTL level ■ Rail-to-rail signal handling ■ Low insertion loss ■ Route communications signals include: Description The Fairchild Switch FSAL200 is a rail-to-rail quad 2:1 high-speed CMOS TTL-compatible analog multiplexer/ demultiplexer switch. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. When OE is LOW, the select pin connects the A Port to the selected B Port output. When OE is HIGH, the switch is OPEN and a high-impedance state exists between the two ports. • • • • • • • 10/100 Ethernet 100VG-AnyLAN ATM25 SONET OCI 51.8 Mbps USB1.1 T1/E1 Token Ring 4/16 Mbps Ordering Information Part Number FSAL200QSC FSAL200MTC Package Number Pb-Free MQA16 MTC16 Yes Yes Package 16-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Packing Method This device is also available in tape and reel. To order, append X to the part number. © 2002 - 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSAL200 Rev. 1.7.0 Analog Symbol Connection Diagram Truth Table S X LOW HIGH OE HIGH LOW LOW Function Disconnect A=B1 A=B2 Pin Descriptions Pin Name OE S A, B1, B2 Function Switch Enable Select Input Data Port © 2002 - 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSAL200 Rev. 1.7.0 2 Absolute Maximum Ratings The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the conditions for actual device operation. Symbol VCC VS VIN IIK IOUT ICC/IGND TSTG PD TA Supply Voltage Parameter DC Switch Voltage(1) DC Input Voltage (1) Min. -0.5 -0.5 -0.5 Max. 7.0 0.5 7.0 -50 120 ±100 Unit V V V mA mA mA °C W °C DC Input Diode Current @ (IIK) VIN < 0V DC Output Current DC VCC or Ground Current Storage Temperature Range Power Dissipation @ ±85°C Ambient Temperature with Power Applied -40 -65 +150 0.5 85 Recommended Operating Conditions(2) Symbol VCC VIN VIN VOUT TA tr, tf OJA Parameter Supply Voltage Operating Control Input Voltage Switch Input Voltage Output Voltage Operating Temperature Input RIse and Fall Time Control Input Vcc = 2.3V - 3.6V Control Input Vcc = 4.5V - 5.5V Thermal Resistance Min. 3.0 0 0 0 -40 0 0 Max. 5.5 VCC VCC VCC +85 10 5 350 Unit V V V V °C ns/V ns/V °C/W 1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. 2. Control input must be held HIGH or LOW; it must not float. © 2002 - 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSAL200 Rev. 1.7.0 3 DC Electrical Characteristics VCC Symbol VIH VIL IOZ RON IIN ICC TA =-40°C to+85°C Min. 2.0 2.0 -0.5 -0.5 6 15 0.8 0.8 100 12 22 ±1 ±1 1 0 0.4 1 100 80 3 7 Ω VCC 2 3 mA mA V Ω mA nA Ω V Parameter HIGH-Level Input Voltage LOW-Level Input Voltage OFF State Leakage Current Switch On Resistance (3) Conditions (V) 4.5 - 5.5 3.0 - 3.6 4.5 - 5.5 3.0 - 3.6 Typ. Max. Units V 0 £ VIN £5.5V ION = 10 - 30 mA ION = 10 - 30 mA VIN = VCC or GND VIN = VCC or GND VIN = VCC or GND IOUT = 0 0 - 5.5 4.5 - 5.5 3.0 - 3.6 5.5 3.6 5.5 VCC Control Input Leakage Current Quiescent Supply Current All Channels ON or OFF Analog Signal Range ΔRON IO Rflat On Resistance Match Between Channels (3,4) IA= -30 mA, VBn = 3.15 IA = -10 mA, VBn 2.1 Bn, Bn, S = 0V to 5V 4.5 - 5.5 3.0 - 3.6 4.5 - 5.5 3.0 - 3.6 4.5 - 5.5 3.0 - 3.6 Output Current On Resistance Flatness(3,5) A, B1, B2 = 0V to 5V A, B1, B2 = 0V to 5V 3. Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A or B Ports). 4. ΔRON = RON maximum - RON minimum measured at identical VCC, temperature, and voltage levels. 5. Flatness is defined as the difference between the maximum and minimum value of On Resistance over the specified range of conditions. © 2002 - 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSAL200 Rev. 1.7.0 4 AC Electrical Characteristics VCC Symbol tON tOFF Q TA = -40°C to +85°C Min. Typ. 10 28 5 4 7 3 -55 -75 -70 -75 137 110 2 3 dB dB dB dB MHz MHz % Figure 4 Figure 4 Figure 5 Figure 5 Figure 8 Figure 8 Parameter Turn-On Time S to Output Turn-Off Time S to Output Charge Injection (6) Conditions VBn = 3V VBn = 1.5V VBn = 3V VBn = 1.5V CL = 0.1 nF, VGEN = 0V RGEN = 0Ω RL = 100Ω f = 30 MHz RL = 50Ω f = 1 MHz (V) 4.5 - 5.5 3.0 - 3.6 4.5 - 5.5 3.0 - 3.6 5.0 3.3 4.5 - 5.5 3.0 - 3.6 4.5 - 5.5 3.0 - 3.6 4.5 - 5.5 3.0 - 3.6 4.5 - 5.5 3.0 - 3.6 Max. 20 40 10 20 Units ns ns ns ns pC Figure Figure 1 Figure 2 Figure 1 Figure 2 Figure 3 OIRR Off Isolation (7) Xtalk Crosstalk RL = 100Ω f = 30 MHz RL = 50Ω f = 1 MHz BW D -3dB Bandwidth ΔRON/RL Distortion(6) RL = 100Ω RL = 50Ω RL = 100Ω 6. Guaranteed by design. 7. Off Isolation = 20 log10 [VA / VBn]. Capacitance(8) Symbol CIN CIO-B CON Parameter Control Pin Input Capacitance B Port Off Capacitance A Port Off Capacitance Channel On Capacitance Conditions VCC = 0V VCC = 5.0V and 3.0V VCC = 5.0V and 3.0V VCC = 5.0V and 3.0V Typ. 2.3 8 13 15 Max. Units. pF pF pF pF Figure Figure 6 Figure 7 Figure 7 8. TA = +25°C, f = 1 MHz. Capacitance is characterized, but not tested in production. © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com Device Number Rev. 1.7.0 5 AC Loading and Waveforms Figure 1. AC Waveforms Figure 2. ton, toff Loading © 2002 - 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSAL200 Rev. 1.7.0 6 Figure 3. Charge Injection Test Figure 4. Off Isolation Figure 7. Channel On Capacitance Figure 5. Crosstalk Figure 8. Bandwidth Figure 6. Channel Off Capacitance © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com Device Number Rev. 1.7.0 7 Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 9. 16-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0/0150” Wide, Package Number MQA16 © 2002 - 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FSAL200 Rev. 1.7.0 8 Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 10. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide, Package Number MTC16 © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com Device Number Rev. 1.7.0 9 © 2002 - 2006 Fairchild Semiconductor Corporation FSAL200 Rev. 1.7.0 10 www.fairchildsemi.com