HUF75645S3ST_NL

HUF75645P3, HUF75645S3S October 2013 Data Sheet N-Channel UltraFET Power MOSFET 100 V, 75 A, 14 mΩ Packaging Features JEDEC TO-220AB JEDEC TO-263AB DRAIN (FLANGE) SOURCE DRAIN GATE GATE SOURCE DRAIN (FLANGE) • Ultra Low On-Resistance - rDS(ON) = 0.014Ω, VGS = 10V • Simulation Models - Temperature Compensated PSPICE® and SABER™ Electrical Models - Spice and Saber Thermal Impedance Models - www.fairchildsemi.com • Peak Current vs Pulse Width Curve HUF75645P3 HUF75645S3ST • UIS Rating Curve Ordering Information Symbol D G PART NUMBER PACKAGE BRAND HUF75645P3 TO-220AB 75645P HUF75645S3ST TO-263AB 75645S S Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified HUF75645P3, HUF75645S3ST UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 100 V Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 100 V Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V Drain Current Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 75 65 Figure 4 A A Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figures 6, 14, 15 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 2.07 W W/oC Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300 260 oC oC NOTES: 1. TJ = 25oC to 150oC. CAUTION: Stresses above those listed in “Absol24ute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html For severe environments, see our Automotive HUFA series. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification. ©2001 Fairchild Semiconductor Corporation HUF75645P3, HUF75645S3S Rev. C0 HUF75645P3, HUF75645S3S Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 100 - - V VDS = 95V, VGS = 0V - - 1 µA VDS = 90V, VGS = 0V, TC = 150oC - - 250 µA VGS = ±20V - - ±100 nA OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current BVDSS IDSS IGSS ID = 250µA, VGS = 0V (Figure 11) ON STATE SPECIFICATIONS Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V Drain to Source On Resistance rDS(ON) ID = 75A, VGS = 10V (Figure 9) - 0.0115 0.014 Ω TO-220 and TO-263 - - 0.48 oC/W - - 62 oC/W - - 197 ns - 14 - ns - 117 - ns td(OFF) - 41 - ns tf - 97 - ns tOFF - - 207 ns - 198 238 nC - 106 127 nC - 6.8 8.2 nC THERMAL SPECIFICATIONS Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time tON td(ON) tr Turn-Off Delay Time Fall Time Turn-Off Time VDD = 50V, ID = 75A VGS = 10V, RGS = 2.5Ω (Figures 18, 19) GATE CHARGE SPECIFICATIONS Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V Total Gate Charge VDD = 50V, ID = 75A, Ig(REF) = 1.0mA (Figures 13, 16, 17) Gate to Source Gate Charge Qgs - 14 - nC Gate to Drain “Miller” Charge Qgd - 41 - nC - 3790 - pF - 810 - pF - 230 - pF MIN TYP MAX UNITS ISD = 75A - - 1.25 V ISD = 35A - - 1.00 V trr ISD = 75A, dISD/dt = 100A/µs - - 145 ns QRR ISD = 75A, dISD/dt = 100A/µs - - 360 nC CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ©2001 Fairchild Semiconductor Corporation SYMBOL VSD TEST CONDITIONS HUF75645P3, HUF75645S3S Rev. C0 HUF75645P3, HUF75645S3S Typical Performance Curves 80 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 60 VGS = 10V 40 20 0.2 0 0 25 50 75 100 150 125 0 175 25 50 75 TC , CASE TEMPERATURE (oC) 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 ZθJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE IDM, PEAK CURRENT (A) 2000 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 1000 175 - TC I = I25 150 VGS = 10V 100 50 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY ©2001 Fairchild Semiconductor Corporation HUF75645P3, HUF75645S3S Rev. C0 HUF75645P3, HUF75645S3S Typical Performance Curves (Continued) 500 100 100µs 10 10ms SINGLE PULSE T J = MAX RATED T C = 25oC 1 1 100 10 STARTING TJ = 25oC 100 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - V DD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 600 STARTING TJ = 150oC 10 0.001 300 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 5. FORWARD BIAS SAFE OPERATING AREA 150 120 90 60 TJ = 175oC TJ = -55oC 30 VGS = 7V VGS = 6V VGS = 20V VGS = 10V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 150 120 VGS =5V 90 60 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC 30 TJ = 25oC 0 0 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) 0 6 FIGURE 7. TRANSFER CHARACTERISTICS 1.2 VGS = 10V, ID = 75A VGS = VDS, ID = 250µA 2.5 NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 4 FIGURE 8. SATURATION CHARACTERISTICS 3.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V) 2.0 1.5 1.0 0.8 0.6 1.0 0.4 0.5 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE ©2001 Fairchild Semiconductor Corporation 200 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE HUF75645P3, HUF75645S3S Rev. C0 HUF75645P3, HUF75645S3S Typical Performance Curves (Continued) 20000 VGS = 0V, f = 1MHz ID = 250µA 10000 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.2 1.1 1.0 CISS = CGS + CGD 1000 COSS ≅ CDS + CGD CRSS = CGD 100 0.9 -80 -40 0 40 80 120 200 160 50 0.1 TJ , JUNCTION TEMPERATURE (oC) 1.0 10 100 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE VGS , GATE TO SOURCE VOLTAGE (V) 10 VDD = 50V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 75A ID = 50A ID = 25A 2 0 0 30 60 90 Qg, GATE CHARGE (nC) 120 NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT ©2001 Fairchild Semiconductor Corporation HUF75645P3, HUF75645S3S Rev. C0 HUF75645P3, HUF75645S3S Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD VGS = 10V VGS DUT VGS = 2V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS VDS tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + VGS VDD - 10% 10% 0 DUT 90% RGS VGS VGS 0 FIGURE 18. SWITCHING TIME TEST CIRCUIT ©2001 Fairchild Semiconductor Corporation 10% 50% 50% PULSE WIDTH FIGURE 19. SWITCHING TIME WAVEFORM HUF75645P3, HUF75645S3S Rev. C0 HUF75645P3, HUF75645S3S PSPICE Electrical Model .SUBCKT HUF75645 2 1 3 ; rev 21 May 1999 CA 12 8 5.31e-9 CB 15 14 5.31e-9 CIN 6 8 3.56e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD LDRAIN DPLCAP DRAIN 2 5 10 5 51 ESLC 11 - RDRAIN 6 8 EVTHRES + 19 8 + LGATE GATE 1 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD + 50 - IT 8 17 1 EVTEMP RGATE + 18 22 9 20 21 EBREAK 17 18 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 7.80e-3 RGATE 9 20 0.83 RLDRAIN 2 5 10 RLGATE 1 9 26 RLSOURCE 3 7 11 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.65e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B DBREAK + RSLC2 ESG LDRAIN 2 5 1.0e-9 LGATE 1 9 5.1e-9 LSOURCE 3 7 4.4e-9 RLDRAIN RSLC1 51 EBREAK 11 7 17 18 115.5 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RLSOURCE S1A 12 S2A 13 8 14 13 S1B CA 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - - IT 14 + + 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD RBREAK 15 VBAT 5 8 EDS - + 8 22 RVTHRES VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*205),3.5))} .MODEL DBODYMOD D (IS = 3.00e-12 IKF = 19 RS = 1.78e-3 XTI = 5 TRS1 = 2.25e-3 TRS2 = 1.00e-5 CJO = 5.32e-9 TT = 7.4e-8 M = 0.68) .MODEL DBREAKMOD D (RS = 2.15e- 1IKF = 1 TRS1 = 8e- 4TRS2 = 3e-6) .MODEL DPLCAPMOD D (CJO = 5.55e- 9IS = 1e-3 0M = 0.98) .MODEL MMEDMOD NMOS (VTO = 3.13 KP = 10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.83) .MODEL MSTROMOD NMOS (VTO = 3.51 KP = 93 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.65 KP = 0.11 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.33 ) .MODEL RBREAKMOD RES (TC1 = 9.9e- 4TC2 = -1.3e-6) .MODEL RDRAINMOD RES (TC1 = 9.40e-3 TC2 = 2.93e-5) .MODEL RSLCMOD RES (TC1 = 2.63e-3 TC2 = 1.05e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.57e-3 TC2 = -7.05e-6) .MODEL RVTEMPMOD RES (TC1 = -2.87e- 3TC2 = -2.21e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -6.2 VOFF= -2.4) VON = -2.4 VOFF= -6.2) VON = -1.8 VOFF= 0.5) VON = 0.5 VOFF= -1.8) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. ©2001 Fairchild Semiconductor Corporation HUF75645P3, HUF75645S3S Rev. C0 HUF75645P3, HUF75645S3S SABER Electrical Model REV 21 May 1999 template ta75645 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 3.00e-12, cjo = 5.32e-9, tt = 7.4e-8, xti = 5, m = 0.68) d..model dbreakmod = () d..model dplcapmod = (cjo = 5.55e-9, is = 1e-30, vj=1.0, m = 0.8) m..model mmedmod = (type=_n, vto = 3.13, kp = 10, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.51, kp = 93, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.65, kp = 0.11, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.2, voff = -2.4) DPLCAP sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.4, voff = -6.2) 10 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.8, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -1.8) c.ca n12 n8 = 5.31e-9 c.cb n15 n14 = 5.31e-9 c.cin n6 n8 = 3.56e-9 DRAIN 2 RSLC1 51 RLDRAIN RDBREAK RSLC2 72 ISCL RDRAIN 6 8 ESG EVTHRES + 19 8 + i.it n8 n17 = 1 LGATE GATE 1 EVTEMP RGATE + 18 22 9 20 MWEAK MSTRO CIN DBODY EBREAK + 17 18 MMED m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u 71 11 16 6 RLGATE res.rbreak n17 n18 = 1, tc1 = 9.9e-4, tc2 = -1.3e-6 res.rdbody n71 n5 = 1.78e-3, tc1 = 2.25e-3, tc2 = 1.e-5 res.rdbreak n72 n5 = 2.15e-1, tc1 = 8e-4, tc2 = 3e-6 res.rdrain n50 n16 = 7.8e-3, tc1 = 9.4e-3, tc2 = 2.93e-5 res.rgate n9 n20 = 0.83 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 26 res.rlsource n3 n7 = 11 res.rslc1 n5 n51 = 1e-6, tc1 = 2.63e-3, tc2 = 1.05e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.65e-3, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.87e-3, tc2 = -2.21e-6 res.rvthres n22 n8 = 1, tc1 = -2.57e-3, tc2 = -7.05e-6 21 RDBODY DBREAK 50 - d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 5.1e-9 l.lsource n3 n7 = 4.4e-9 LDRAIN 5 - 8 LSOURCE 7 SOURCE 3 RSOURCE RLSOURCE S1A 12 S2A 14 13 13 8 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 + 6 8 EGS 19 CB + - - IT 14 VBAT 5 8 EDS - + 8 22 RVTHRES spe.ebreak n11 n7 n17 n18 = 115.5 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/205))** 3.5)) } } ©2001 Fairchild Semiconductor Corporation HUF75645P3, HUF75645S3S Rev. C0 HUF75645P3, HUF75645S3S SPICE Thermal Model th JUNCTION REV 28 July 1999 HUF75645T CTHERM1 th 6 8.80e-3 CTHERM2 6 5 2.50e-2 CTHERM3 5 4 2.70e-2 CTHERM4 4 3 3.70e-2 CTHERM5 3 2 4.40e-2 CTHERM6 2 tl 3.40e-1 RTHERM1 RTHERM1 th 6 1.20e-2 RTHERM2 6 5 3.00e-2 RTHERM3 5 4 4.30e-2 RTHERM4 4 3 8.80e-2 RTHERM5 3 2 9.90e-2 RTHERM6 2 tl 1.10e-1 RTHERM2 CTHERM1 6 CTHERM2 5 RTHERM3 CTHERM3 SABER Thermal Model SABER thermal model HUF75645T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 8.80e-3 ctherm.ctherm2 6 5 = 2.50e-2 ctherm.ctherm3 5 4 = 2.70e-2 ctherm.ctherm4 4 3 = 3.70e-2 ctherm.ctherm5 3 2 = 4.40e-2 ctherm.ctherm6 2 tl = 3.40e-1 rtherm.rtherm1 th 6 = 1.20e-2 rtherm.rtherm2 6 5 = 3.00e-2 rtherm.rtherm3 5 4 = 4.30e-2 rtherm.rtherm4 4 3 = 8.80e-2 rtherm.rtherm5 3 2 = 9.90e-2 rtherm.rtherm6 2 tl = 1.10e-1 } 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl ©2001 Fairchild Semiconductor Corporation CASE HUF75645P3, HUF75645S3S Rev. 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Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I66 ©2001 Fairchild Semiconductor Corporation HUF75645P3, HUF75645S3S Rev. C0