ML4800IP

www.fairchildsemi.com ML4800 Power Factor Correction and PWM Controller Combo Features • Internally synchronized leading-edge PFC and trailingedge PWM in one IC • TriFault Detect™ for UL1950 compliance and enhanced safety • Slew rate enhanced transconductance error amplifier for ultra-fast PFC response • Low power: 200µA startup current, 5.5mA operating current • Low total harmonic distortion, high PF • Reduced ripple current in storage capacitor between PFC and PWM sections • Average current, continuous boost leading edge PFC • PWM configurable for current-mode or voltage mode operation • Current fed gain modulator for improved noise immunity • Overvoltage and brown-out protection, UVLO, and soft start General Description The ML4800 is a controller for power factor corrected, switched mode power supplies. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC1000-3-2 specification. Intended as a BiCMOS version of the industry-standard ML4824, the ML4800 includes circuits for the implementation of leading edge, average current, “boost” type power factor correction and a trailing edge, pulse width modulator (PWM). It also includes a TriFault Detect™ function to help ensure that no unsafe conditions will result from single component failure in the PFC. Gate-drivers with 1A capabilities minimize the need for external driver circuits. Low power requirements improve efficiency and reduce component costs. An over-voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brownout protection. The PWM section can be operated in current or voltage mode, at up to 250kHz, and includes an accurate 50% duty cycle limit to prevent transformer saturation. Block Diagram 16 VEAO VFB 15 2.5V IAC 2 VRMS 4 ISENSE 3 RAMP 1 7 RAMP 2 8 OSCILLATOR R Q GAIN MODULATOR 1.6kΩ VEA + 1 IEAO POWER FACTOR CORRECTOR 0.5V 1.6kΩ IEA + - 13 VCC OVP + 2.75V - TRI-FAULT + - VCC 17V 7.5V REFERENCE S Q VREF 14 + - -1V + - R S Q PFC OUT Q 12 PFC ILIMIT DUTY CYCLE LIMIT VDC 6 VCC SS 5 25µA 1.25V + + PWM OUT S VFB 2.45V + Q VIN OK 1.0V + 11 R DC ILIMIT Q DC ILIMIT 9 VREF PULSE WIDTH MODULATOR VCC UVLO REV. 1.0.5 9/25/01 ML4800 PRODUCT SPECIFICATION Pin Configuration ML4800 16-Pin PDIP (P16) 16-Pin Narrow SOIC (S16N) IEAO 1 IAC 2 ISENSE 3 VRMS 4 SS 5 VDC 6 RAMP 1 7 RAMP 2 8 16 VEAO 15 VFB 14 VREF 13 VCC 12 PFC OUT 11 PWM OUT 10 GND 9 DC ILIMIT TOP VIEW Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name IEAO IAC ISENSE VRMS SS VDC RAMP 1 RAMP 2 DC ILIMIT GND PWM OUT PFC OUT VCC VREF VFB VEAO Function Slew rate enhanced PFC transconductance error amplifier output PFC AC line reference input to Gain Modulator Current sense input to the PFC Gain Modulator PFC Gain Modulator RMS line voltage compensation input Connection point for the PWM soft start capacitor PWM voltage feedback input Oscillator timing node; timing set by RTCT When in current mode, this pin functions as the current sense input; when in voltage mode, it is the PWM modulation ramp input. PWM cycle-by-cycle current limit comparator input Ground PWM driver output PFC driver output Positive supply Buffered output for the internal 7.5V reference PFC transconductance voltage error amplifier input PFC transconductance voltage error amplifier output 2 REV. 1.0.5 9/25/01 PRODUCT SPECIFICATION ML4800 Abolute Maximum Ratings Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter VCC ISENSE Voltage Voltage on Any Other Pin IREF IAC Input Current Peak PFC OUT Current, Source or Sink Peak PWM OUT Current, Source or Sink PFC OUT, PWM OUT Energy Per Cycle Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance (θJA) Plastic DIP Plastic SOIC -65 -5 GND - 0.3 Min. Max. 18 0.7 VCCZ + 0.3 10 10 1 1 1.5 150 150 260 80 105 Units V V V mA mA A A µJ °C °C °C °C/W °C/W Operating Conditions Temperature Range ML4800CX ML4800IX Min 0 -40 .Max. 70 85 Units °C °C Electrical Characteristics Unless otherwise specified, VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1) Symbol Parameter Input Voltage Range Transconductance Feedback Reference Voltage Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio Current Error Amplifier Input Voltage Range Transconductance Input Offset Voltage VNON INV = VINV, VEAO = 3.75V -1.5 50 0 100 4 2 150 15 V mV Ω µΩ 11V < VCC < 16.5V VIN = ±0.5V, VOUT = 6V VIN = ±0.5V, VOUT = 1.5V -40 40 50 50 Note 2 6.0 VNON INV = VINV, VEAO = 3.75V Conditions Min. 0 30 2.43 65 2.5 -0.5 6.7 0.1 -140 140 60 60 0.4 Typ. Max. Units 5 90 2.57 -1.0 V V µA V V µA µA dB dB Ω 3 Voltage Error Amplifier µΩ REV. 1.0.5 9/25/01 ML4800 PRODUCT SPECIFICATION Electrical Characteristics (Continued) Unless otherwise specified, VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1) Symbol Parameter Input Bias Current Output High Voltage Output Low Voltage Source Current Sink Current Open Loop Gain Power Supply Rejection Ratio OVP Comparator Threshold Voltage Hysteresis Tri-Fault Detect Fault Detect HIGH Time to Fault Detect HIGH VFB = VFAULT DETECT LOW to VFB = OPEN. 470pF from VFB to GND 0.4 -0.9 120 2.65 2.75 2 2.85 4 V ms 2.65 175 2.75 250 2.85 325 V mV 11V < VCC < 16.5V VIN = ±0.5V, VOUT = 6V VIN = ±0.5V, VOUT = 1.5V -40 40 60 60 6.0 Conditions Min. Typ. -0.5 6.7 0.65 -104 160 70 75 1.0 Max. Units -1.0 µA V V µA µA dB dB Fault Detect LOW PFC ILIMIT Comparator Threshold Voltage (PFC ILIMIT VTH - Gain Modulator Output) Delay to Output DC ILIMIT Comparator Threshold Voltage Input Bias Current Delay to Output VIN OK Comparator Threshold Voltage Hysteresis GAIN Modulator Gain (Note 3) IAC = 100µA, VRMS = VFB = 0V IAC = 50µA, VRMS = 1.2V, VFB = 0V IAC = 50µA, VRMS = 1.8V, VFB = 0V IAC = 100µA, VRMS = 3.3V, VFB = 0V Bandwidth Output Voltage Oscillator Initial Accuracy Voltage Stability Temperature Stability Total Variation Ramp Valley to Peak Voltage Line, Temp TA = 25°C 11V < VCC < 16.5V IAC = 100µA IAC = 350µA, VRMS = 1V, VFB = 0V 0.5 -1.0 220 150 0.6 -1.1 V V mV 300 1.05 ±1 300 2.55 1.2 1.05 2.40 1.25 0.40 ns V µA ns V V 0.95 1.0 ±0.3 150 2.35 0.8 0.60 1.8 0.85 0.20 0.60 71 2.45 1.0 0.80 2.0 1.0 0.30 10 0.75 76 1 2 MHz 0.9 81 V kHz % % 84 kHz V 68 2.5 4 REV. 1.0.5 9/25/01 PRODUCT SPECIFICATION ML4800 Electrical Characteristics (Continued) Unless otherwise specified, VCC = 15V, RT = 52.3kΩ, CT = 470pF, TA = Operating Temperature Range (Note 1) Symbol Parameter PFC Dead Time CT Discharge Current Reference Output Voltage Line Regulation Load Regulation TA = 25°C, I(VREF) = 1mA 11V tDEADTIME) that the operating frequency can typically be approximated by: 1 f OSC = --------------t RAMP (5) The DC ILIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output of the PWM will be disabled until the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle. VIN OK Comparator EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at: 1 f OSC = 100kHz = --------------t RAMP Solving for RT x CT yields 1.96 x 10-4. Selecting standard components values, CT = 390pF, and RT = 51.1kΩ. The dead time of the oscillator adds to the Maximum PWM Duty Cycle (it is an input to the Duty Cycle Limiter). With zero oscillator dead time, the Maximum PWM Duty Cycle is typically 45%. In many applications, care should be taken that CT not be made so large as to extend the Maximum Duty Cycle beyond 50%. This can be accomplished by using a stable 390pF capacitor for CT. The VIN OK comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on VFB is less than its nominal 2.45V. Once this voltage reaches 2.45V, which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start begins. PWM Control (RAMP 2) When the PWM section is used in current mode, RAMP 2 is generally used as the sampling point for a voltage representing the current in the primary of the PWM’s output transformer, derived either by a current sensing resistor or a current transformer. In voltage mode, it is the input for a ramp voltage generated by a second set of timing components (RRAMP2, CRAMP2), that will have a minimum value of zero volts and should have a peak value of approximately 5V. In voltage mode operation, feedforward from the PFC output buss is an excellent way to derive the timing ramp for the PWM stage. Soft Start PWM SECTION Pulse Width Modulator The PWM section of the ML4800 is straightforward, but there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current-mode or voltage mode operation. In current-mode applications, the PWM ramp (RAMP 2) is usually derived directly from a current sensing resistor or current transformer in the primary of the 10 Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 25µA supplies the charging current for the capacitor, and start-up of the PWM begins at 1.25V. Start-up delay can be programmed by the following equation: 25 µ A C SS = t DELAY × -------------1.25V (6) REV. 1.0.5 9/25/01 PRODUCT SPECIFICATION ML4800 where CSS is the required soft start capacitance, and tDELAY is the desired start-up delay. It is important that the time constant of the PWM soft-start allow the PFC time to generate sufficient output power for the PWM section. The PWM start-up delay should be at least 5ms. Solving for the minimum value of CSS: 25 µ A Css = 5ms × -------------- = 100nF 1.25V (6a) function, it is important to limit the current through the Zener to avoid overheating or destroying it. This can be easily done with a single resistor in series with the Vcc pin, returned to a bias supply of typically 18V to 20V. The resistor’s value must be chosen to meet the operating current requirement of the ML4800 itself (8.5mA, max.) plus the current required by the two gate driver outputs. EXAMPLE: With a VBIAS of 20V, a VCC of 15V and the ML4800 driving a total gate charge of 90nC at 100kHz (e.g., 1 IRF840 MOSFET and 2 IRF820 MOSFETs), the gate driver current required is: I GATEDRIVE = 100kHz × 90nC = 9mA V BIAS – V CC R BIAS = --------------------------------I CC + I G + I Z 20V – 15V R BIAS = -------------------------------------------------- = 250 Ω 6mA + 9mA + 5mA Choose RBIAS = 240Ω. The ML4800 should be locally bypassed with a 1.0µF ceramic capacitor. In most applications, an electrolytic capacitor of between 47µF and 220µF is also required across the part, both for filtering and as part of the start-up bootstrap circuitry. (7) (8) Caution should be exercised when using this minimum soft start capacitance value because premature charging of the SS capacitor and activation of the PWM section can result if VFB is in the hysteresis band of the VIN OK comparator at start-up. The magnitude of VFB at start-up is related both to line voltage and nominal PFC output voltage. Typically, a 1.0µF soft start capacitor will allow time for V FB and PFC out to reach their nominal values prior to activation of the PWM section at line voltages between 90Vrms and 265Vrms. Generating VCC The ML4800 is a voltage-fed part. It requires an external 15V, ±10% (or better) shunt voltage regulator, or some other VCC regulator, to regulate the voltage supplied to the part at 15V nominal. This allows low power dissipation while at the same time delivering 13V nominal gate drive at the PWM OUT and PFC OUT outputs. If using a Zener diode for this L1 + DC I1 VIN SW2 I2 I3 I4 SW1 C1 RL RAMP VEAO REF U3 + EA – DFF RAMP OSC U4 CLK + – U1 R Q D U2 Q CLK VSW1 TIME TIME Figure 4. Typical Trailing Edge Control Scheme REV. 1.0.5 9/25/01 11 ML4800 PRODUCT SPECIFICATION Leading/Trailing Modulation Conventional Pulse Width Modulation (PWM) techniques employ trailing edge modulation in which the switch will turn on right after the trailing edge of the system clock. The error amplifier output voltage is then compared with the modulating ramp. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned OFF. When the switch is ON, the inductor current will ramp up. The effective duty cycle of the trailing edge modulation is determined during the ON time of the switch. Figure 4 shows a typical trailing edge control scheme. In the case of leading edge modulation, the switch is turned OFF right at the leading edge of the system clock. When the modulating ramp reaches the level of the error amplifier output voltage, the switch will be turned ON. The effective duty-cycle of the leading edge modulation is determined during the OFF time of the switch. Figure 5 shows a leading edge control scheme. One of the advantages of this control technique is that it requires only one system clock. Switch 1 (SW1) turns off and switch 2 (SW2) turns on at the same instant to minimize the momentary “no-load” period, thus lowering ripple voltage generated by the switching action. With such synchronized switching, the ripple voltage of the first stage is reduced. Calculation and evaluation have shown that the 120Hz component of the PFC’s output ripple voltage can be reduced by as much as 30% using this method. Typical Applications Figure 6 is the application circuit for a complete 100W power factor corrected power supply, designed using the methods and general topology detailed in Application Note 33. L1 + DC I1 VIN SW2 I2 I3 I4 SW1 C1 RL RAMP VEAO U3 + EA – REF VEAO + – CMP U1 DFF R Q D U2 Q CLK VSW1 TIME RAMP OSC U4 CLK TIME Figure 5. Typical Leading Edge Control Scheme 12 REV. 1.0.5 9/25/01 D12 VBUSS F1 3.15A Q1G IRF840A T2C Q1 R20 22Ω T1B R28 240Ω MBR2545CT Q3G R18 33Ω D11B IRF820A Q3 D6 600V C20 0.47µF R17 3Ω R21 2.2Ω T1A C7 150pF R37 1kΩ 2N3904 Q4 D4 5.1V ML4800 1 IEAO U1 IAC ISENSE VRMS SS VDC RAMP1 RAMP 2 DC ILMIT 9 D8 GND 10 PWM OUT 11 C15 1.0µF C31 330pF D10 C13 0.22µF C8 150µF C9 15nF PFC OUT 12 J8 C10 10µF VCC 13 VREF 14 R11 412kΩ R26 10kΩ VFB 15 VCC VFB VDC 16 2 3 4 5 6 7 8 1N4733A REF R40 470Ω MOC8112 L1 D1 8A FES16JT AC INPUT 85 TO 260V R27 82kΩ IRF840A R24 10kΩ D5 600V D7 16V D11A L2 L3 C4 4.7nF C25 0.1µF R13 383kΩ R1 357kΩ R9 249kΩ R2 357kΩ C26 47µF D2 15V 1N4744A C12 10µF 35V C24 0.47µF C21 1500µF R14 383kΩ REV. 1.0.5 9/25/01 BR1 4A, 600V KBL06 C5 100µF Q2G R19 33Ω Q2 IRF820A 12V 12V, 100W C32 0.47µF C30 1000µF R10 249kΩ PWM ILIMIT R22 2.2Ω R30 1.5kΩ C22 10µF R32 8.66kΩ R38 42.2kΩ R16 10kΩ R4 13.2kΩ R12 68.1k C6 1.5nF R23 220Ω R29 1.2kΩ R34 240Ω R25 10kΩ U2 R44 10kΩ R31 10kΩ C23 10nF R15 4.99kΩ VDC U3 TL431A C11 220pF C28 220pF PRI GND R33 2.26kΩ 12V RET 12V RETURN C19 1.0µF C18 470pF C1 0.47µF PRODUCT SPECIFICATION ISENSE R5 1.2Ω R6 1.2Ω R7 1.2Ω R8 1.2Ω C3 R3 0.22µF 100kΩ C2 0.47µF R39 33Ω RT/CT D14 1N914 D13 1N914 D15 1N914 Figure 6. 100W Power Factor Corrected Power Supply, Designed Using Micro Linear Application Note 33 NOTE: D7, D8, D10; 1N966B D3, D5, D6, D12; UF4005 D4; 1N4733A D2; 1N4744A D11; MBR2545CT L1; PREMIER MAGNETICS TSD-1047 L2; PREMIER MAGNETICS VTP-05007 L3; PREMIER MAGNETICS TSD-904 T1; PREMIER MAGNETICS PMGD-03 T2; PREMIER MAGNETICS TSD-735 UNUSED DESIGNATORS; C14, C16, C17, C27, C29, C33, D3, D9, R42, R43, R36, R35 ML4800 13 ML4800 PRODUCT SPECIFICATION Ordering Information Part Number ML4800CP ML4800CS ML4800IP ML4800IS Temperature Range 0°C to 70°C 0°C to 70°C -40°C to 85°C -40°C to 85°C Package 16-Pin PDIP (P16) 16-Pin Narrow SOIC (S16N) 16-Pin PDIP (P16) 16-Pin Narrow SOIC (S16N) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury of the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 9/25/01 0.0m 001 Stock#DS30004800  2001 Fairchild Semiconductor Corporation