MM74HCT32MXNL

MM74HCT32 Quad 2-Input OR Gate Features General Description ■ TTL, LS pin-out and threshold compatible The MM74HCT32 is a logic function fabricated by using advanced silicon-gate CMOS technology, which provides the inherent benefits of CMOS—low quiescent power and wide power supply range. This device is input and output characteristic and pin-out compatible with standard 74LS logic families. All inputs are protected from static discharge damage by internal diodes to VCC and ground. ■ Fast switching: tPLH, tPHL = 10ns (typ.) ■ Low power: 10µW at DC ■ High fan-out, 10 LS-TTL loads MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. Ordering Information Order Number Package Number Package Description MM74HCT32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HCT32SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT32MTC MM74HCT32N MTC14 N14A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1987 Fairchild Semiconductor Corporation MM74HCT32 Rev. 1.3.0 www.fairchildsemi.com MM74HCT32 — Quad 2-Input OR Gate February 2008 MM74HCT32 — Quad 2-Input OR Gate Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Logic Diagram ©1987 Fairchild Semiconductor Corporation MM74HCT32 Rev. 1.3.0 www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Rating VCC Supply Voltage VIN DC Input Voltage –1.5 to VCC+1.5V DC Output Voltage –0.5 to VCC+0.5V VOUT IIK, IOK –0.5 to +7.0V Clamp Diode Current ±20mA IOUT DC Output Current, per pin ±25mA ICC DC VCC or GND Current, per pin ±50mA TSTG PD Storage Temperature Range –65°C to +150°C Power Dissipation Note 2 600mW S.O. Package only TL 500mW Lead Temperature (Soldering 10 seconds) 260°C Notes: 1. Unless otherwise specified all voltages are referenced to ground. 2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIN, VOUT TA t r, t f Parameter Supply Voltage DC Input or Output Voltage Operating Temperature Range Input Rise or Fall Times ©1987 Fairchild Semiconductor Corporation MM74HCT32 Rev. 1.3.0 Min. Max. Units 4.5 5.5 V 0 VCC V –40 +85 °C 500 ns www.fairchildsemi.com 3 MM74HCT32 — Quad 2-Input OR Gate Absolute Maximum Ratings(1) VCC = 5V ± 10% (unless otherwise specified) TA = –40°C to +85°C TA = 25°C Symbol Parameter Conditions Typ. Guaranteed Limits Units VIH Minimum HIGH Level Input Voltage 2.0 2.0 V VIL Maximum LOW Level Input Voltage 0.8 0.8 V VOH Minimum HIGH Level Output Voltage V VOL Maximum LOW Level Voltage VIN = VIH or VIL, |IOUT| = 20µA VCC VCC – 0.1 VCC – 0.1 VIN = VIH or VIL, |IOUT| = 4.0mA, VCC = 4.5V 4.2 3.98 3.84 VIN = VIH or VIL, |IOUT| = 4.8mA, VCC = 5.5V 5.2 4.98 4.84 0 0.1 0.1 VIN = VIH, |IOUT| = 4.0mA, VCC = 4.5V 0.2 0.26 0.33 VIN = VIH, |IOUT| = 4.8mA, VCC = 5.5V 0.2 0.26 0.33 ± 0.1 ± 1.0 µA VIN = VIH, |IOUT| = 20µA V IIN Maximum Input Current VIN = VCC or GND, VIH or VIL ICC Maximum Quiescent Supply Current VIN = VCC or GND, IOUT = 0µA 2.0 20 µA VIN = 2.4V or 1.2 1.4 mA Guaranteed Limit Units 0.5V(3) Note: 3. This is measured per input with all other inputs held at VCC or ground. AC Electrical Characteristics VCC = 5.0V, tr = tf = 6ns, CL = 15pF, TA = 25C° (unless otherwise noted) Symbol tPLH, tPHL Parameter Conditions Typ. Maximum Propagation Delay 10 ns AC Electrical Characteristics VCC = 5.0V ± 10%, tr = tf = 6ns, CL = 15pF (unless otherwise noted) TA = 25°C Symbol Parameter tPLH, tPHL Maximum Propagation Delay tTHL, tTLH Maximum Output Rise & Fall Time CPD Power Dissipation Capacitance CIN Input Capacitance Conditions (4) Typ. TA = –40°C to +85°C Guaranteed Limits 12 20 25 8 15 19 48 5 Units ns ns pF 10 10 pF Note: 4. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f +ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. ©1987 Fairchild Semiconductor Corporation MM74HCT32 Rev. 1.3.0 www.fairchildsemi.com 4 MM74HCT32 — Quad 2-Input OR Gate DC Electrical Characteristics 8.75 8.50 0.65 A 7.62 14 8 B 5.60 4.00 3.80 6.00 PIN ONE INDICATOR 1 1.70 7 0.51 0.35 1.27 0.25 (0.33) 1.75 MAX 1.50 1.25 1.27 LAND PATTERN RECOMMENDATION M C B A SEE DETAIL A 0.25 0.10 C 0.25 0.19 0.10 C NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13 0.50 X 45° 0.25 R0.10 R0.10 8° 0° 0.90 0.50 (1.04) SEATING PLANE DETAIL A SCALE: 20:1 Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1987 Fairchild Semiconductor Corporation MM74HCT32 Rev. 1.3.0 www.fairchildsemi.com 5 MM74HCT32 — Quad 2-Input OR Gate Physical Dimensions MM74HCT32 — Quad 2-Input OR Gate Physical Dimensions (Continued) Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1987 Fairchild Semiconductor Corporation MM74HCT32 Rev. 1.3.0 www.fairchildsemi.com 6 MM74HCT32 — Quad 2-Input OR Gate Physical Dimensions (Continued) 0.65 0.43 TYP 1.65 6.10 0.45 12.00° TOP & BOTTOM R0.09 min A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6 1.00 R0.09min Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1987 Fairchild Semiconductor Corporation MM74HCT32 Rev. 1.3.0 www.fairchildsemi.com 7 MM74HCT32 — Quad 2-Input OR Gate Physical Dimensions (Continued) 19.56 18.80 14 8 6.60 6.09 1 7 (1.74) 8.12 7.62 1.77 1.14 3.56 3.30 0.35 0.20 5.33 MAX 0.38 MIN 3.81 3.17 0.58 0.35 8.82 2.54 NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7 Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1987 Fairchild Semiconductor Corporation MM74HCT32 Rev. 1.3.0 www.fairchildsemi.com 8 ACEx® Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EZSWITCH™ * ™ PDP-SPM™ Power220® POWEREDGE® Power-SPM™ PowerTrench® Programmable Active Droop™ QFET® QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 FPS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® ® Fairchild® Fairchild Semiconductor® FACT Quiet Series™ FACT® FAST® FastvCore™ FlashWriter® * ® SupreMOS™ SyncFET™ ® The Power Franchise® TinyBoost™ TinyBuck™ TinyLogic® TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ µSerDes™ UHC® Ultra FRFET™ UniFET™ VCX™ * EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I33 ©1987 Fairchild Semiconductor Corporation MM74HCT32 Rev. 1.3.0 www.fairchildsemi.com 9 MM74HCT32 — Quad 2-Input OR Gate TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.