SSN1N45B

SSN1N45B SSN1N45B 450V N-Channel MOSFET General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for electronic ballasts based on half bridge configuration. Features • • • • • • 0.5A, 450V, RDS(on) = 4.25Ω @VGS = 10 V Low gate charge ( typical 6.5 nC) Low Crss ( typical 6.5 pF) 100% avalanche tested Improved dv/dt capability Gate-Source Voltage ± 50V guaranteed D ! ● ◀ ▲ ● ● G! TO-92 GDS SSN Series ! S Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) Drain Current - Pulsed (Note 1) SSN1N45B 450 0.5 0.32 4.0 ± 50 (Note 2) (Note 1) (Note 1) (Note 3) Units V A A A V mJ A mJ V/ns W W W/°C °C °C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA = 25°C) Power Dissipation (TL = 25°C) 108 0.5 0.25 5.5 0.9 2.5 0.02 -55 to +150 300 TJ, Tstg TL - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds Thermal Characteristics Symbol RθJL RθJA Parameter Thermal Resistance, Junction-to-Lead Thermal Resistance, Junction-to-Ambient (Note 6a) (Note 6b) Typ --- Max 50 140 Units °C/W °C/W ©2002 Fairchild Semiconductor Corporation Rev. A, November 2002 SSN1N45B Electrical Characteristics Symbol Parameter TC = 25°C unless otherwise noted Test Conditions Min Typ Max Units Off Characteristics BVDSS ∆BVDSS / ∆TJ IDSS IGSSF IGSSR Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse VGS = 0 V, ID = 250 µA ID = 250 µA, Referenced to 25°C VDS = 450 V, VGS = 0 V VDS = 360 V, TC = 125°C VGS = 50 V, VDS = 0 V VGS = -50 V, VDS = 0 V 450 ------0.5 ------10 100 100 -100 V V/°C µA µA nA nA On Characteristics VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, ID = 250 µA VDS = VGS, ID = 250 mA VGS = 10 V, ID = 0.25 A VDS = 50 V, ID = 0.25 A 2.3 3.5 --3.0 4.2 3.4 0.7 3.7 4.9 4.25 -V V Ω S Dynamic Characteristics Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz ---185 29 6.5 240 40 8.5 pF pF pF Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 360 V, ID = 0.5 A, VGS = 10 V (Note 4,5) VDD = 225 V, ID = 0.5 A, RG = 25 Ω (Note 4,5) -------- 7.5 21 23 36 6.5 0.9 3.2 25 50 55 80 8.5 --- ns ns ns ns nC nC nC Drain-Source Diode Characteristics and Maximum Ratings IS ISM VSD trr Qrr Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 0.5 A Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS = 0 V, IS = 0.5 A, dIF / dt = 100 A/µs (Note 4) ------ ---102 0.26 0.5 4.0 1.4 --- A A V ns µC Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 75mH, IAS = 1.6A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C 3. ISD ≤ 0.5A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2% 5. Essentially independent of operating temperature 6. a) Reference point of the RθJL is the drain lead b) When mounted on 3”x4.5” FR-4 PCB without any pad copper in a still air environment (RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance. RθCA is determined by the user’s board design) ©2002 Fairchild Semiconductor Corporation Rev. A, November 2002 SSN1N45B Typical Characteristics 10 0 ID , Drain Current [A] VGS 15.0 V 10.0 V 8.0 V 6.0 V 5.5 V 5.0 V Bottom : 4.5 V Top : ID, Drain Current [A] 10 0 150℃ 25℃ -55℃ 10 -1 ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ ※ Notes : 1. VDS = 50V 2. 250μ s Pulse Test 10 -1 10 0 10 1 10 -1 2 4 6 8 10 VDS, Drain-Source Voltage [V] VGS , Gate-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 12 10 RDS(ON) [Ω ], Drain-Source On-Resistance 8 VGS = 10V VGS = 20V IDR, Reverse Drain Current [A] 10 0 6 4 150℃ 25℃ 2 ※ Note : TJ = 25℃ ※ Notes : 1. VGS = 0V 2. 250μ s Pulse Test 0 0 1 2 3 4 5 10 -1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ID, Drain Current [A] VSD, Source-Drain voltage [V] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation with Source Current and Temperature 400 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 12 VDS = 90V 10 300 VDS = 225V VDS = 360V Ciss VGS, Gate-Source Voltage [V] 8 Capacitance [pF] 200 Coss 6 100 Crss ※ Note ; 1. VGS = 0 V 2. f = 1 MHz 4 2 ※ Note : ID = 0.5 A 0 -1 10 10 0 10 1 0 0 1 2 3 4 5 6 7 VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC] Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics ©2002 Fairchild Semiconductor Corporation Rev. A, November 2002 SSN1N45B Typical Characteristics (Continued) 1.2 3.0 2.5 BV DSS , (Norm alized) Drain-Source Breakdown Voltage RDS(ON) , (Normalized) Drain-Source On-Resistance 1.1 2.0 1.0 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 0.25 A 0.9 ※ Notes : 1. VGS = 0 V 2. ID = 250 μ A 0.5 0.8 -100 -50 0 50 100 o 150 200 0.0 -100 -50 0 50 100 o 150 200 TJ, Junction Temperature [ C] TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 0.6 Operation in This Area is Limited by R DS(on) 10 1 0.5 ID, Drain Current [A] 10 0 10 -1 DC ※ Notes : 10 -2 1. TC = 25 C 2. TJ = 150 C 3. Single Pulse o o 10 -3 10 0 10 1 10 2 10 3 ID, Drain Current [A] 100 µs 1 ms 10 ms 100 ms 1s 0.4 0.3 0.2 0.1 0.0 25 50 75 100 125 150 VDS, Drain-Source Voltage [V] TC, Case Temperature [℃] Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current vs. Case Temperature 10 2 Z (t), T h e rm a l R e s p o n s e D = 0 .5 10 1 0 .2 0 .1 0 .0 5 PDM t1 t2 s i n g l e p u ls e ※ N o te s : 1 . Z θ J L (t) = 5 0 ℃ /W M a x . 2 . D u ty F a c to r, D = t 1 /t 2 3 . T J M - T L = P D M * Z θ J L (t) 10 0 0 .0 2 0 .0 1 θJ L 10 -1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 t 1 , S q u a r e W a v e P u ls e D u ra tio n [s e c ] Figure 11. Transient Thermal Response Curve ©2002 Fairchild Semiconductor Corporation Rev. A, November 2002 SSN1N45B Gate Charge Test Circuit & Waveform 50KΩ 12V 200nF 300nF Same Type as DUT VDS VGS Qg 10V Qgs Qgd VGS DUT 3mA Charge Resistive Switching Test Circuit & Waveforms VDS VGS RG RL VDD VDS 90% 10V DUT VGS 10% td(on) t on tr td(off) t off tf Unclamped Inductive Switching Test Circuit & Waveforms L VDS ID RG DUT tp BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD BVDSS IAS VDD VDD tp ID (t) VDS (t) Time 10V ©2002 Fairchild Semiconductor Corporation Rev. A, November 2002 SSN1N45B Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ I SD L Driver RG Same Type as DUT VDD VGS • dv/dt controlled by RG • ISD controlled by pulse period VGS ( Driver ) Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) IRM di/dt Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2002 Fairchild Semiconductor Corporation Rev. A, November 2002 SSN1N45B Package Dimensions TO-92 4.58 –0.15 +0.25 0.46 14.47 ±0.40 ±0.10 4.58 ±0.20 1.27TYP [1.27 ±0.20] 3.60 ±0.20 1.27TYP [1.27 ±0.20] 0.38 –0.05 +0.10 3.86MAX 1.02 ±0.10 0.38 –0.05 +0.10 (R2.29) (0.25) Dimensions in Millimeters ©2002 Fairchild Semiconductor Corporation Rev. A, November 2002 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT™ ActiveArray™ FACT Quiet series™ Bottomless™ FAST® FASTr™ CoolFET™ CROSSVOLT™ FRFET™ GlobalOptoisolator™ DOME™ EcoSPARK™ GTO™ E2CMOS™ HiSeC™ EnSigna™ I2C™ Across the board. Around the world.™ The Power Franchise™ Programmable Active Droop™ DISCLAIMER ImpliedDisconnect™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC® OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench® QFET™ QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ SILENT SWITCHER® SMART START™ SPM™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET® VCX™ FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production ©2002 Fairchild Semiconductor Corporation Rev. I1