17511A

Freescale Semiconductor Technical Data Document Number: MPC17511A Rev. 5.0, 9/2008 1.0 A 6.8 V H-Bridge Motor Driver IC The 17511A is a monolithic H-Bridge designed to be used in portable electronic applications to control small DC motors or bipolar step motors. End applications include head positioners (CDROM or disk drive), camera focus motors, and camera shutter solenoids. The 17511A can operate efficiently with supply voltages as low as 2.0V to as high as 6.8V. Its low RDS(ON) H-Bridge output MOSFETs (0.46 Ω typical) can provide continuos motor drive currents of 1.0A and handle peak currents up to 3.0A. It is easily interfaced to low-cost MCUs via parallel 3.0V- or 5.0V- compatible logic. The device can be pulse width modulated (PWM-ed) at up to 200 kHz. This device contains an integrated charge pump and level shifter (for gate drive voltages), integrated shoot-through current protection (cross-conduction suppression logic and timing), and undervoltage detection and shutdown circuitry. The 17511A has four operating modes: Forward, Reverse, Brake, and Tri-Stated (High Impedance). Features • 2.0V to 6.8V Continuous Operation • Output Current 1.0 A(DC), 3.0A (Peak) • MOSFETs < 600 mΩ RDS(ON) @ 25°C Guaranteed • 3.0V/ 5.0V TTL- / CMOS-Compatible Inputs • PWM Frequencies up to 200 kHz • Undervoltage Shutdown • Cross-Conduction Suppression • Low Power Consumption • Pb-Free Packaging Designated by Suffix Codes EV and EP 17511A H-BRIDGE MOTOR DRIVER IC EV SUFFIX (PB-FREE) 98ASA10614D 16-PIN VMFP EP SUFFIX (PB-FREE) 98ARL10577D 24-PIN QFN ORDERING INFORMATION Device MPC17511AEV MPC17511AEV/EL MPC17511AEP MPC17511AEP/ R2 -20°C to 65°C 24 QFN Temperature Range (TA) Package 16 VMFP 5.0V 5.0V 17511A VDD C1L C1H C2L C2H CRES VM GOUT OUT1 Motor MCU EN GIN IN1 IN2 OUT2 GND Figure 1. 17511A Simplified Application Diagram Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2008. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM C2L Charge Pump C2H C1H C1L CRES GOUT VDD LowVoltage Shutdown VM IN1 OUT1 IN2 VDD Control Logic Level Shifter Predriver OUT2 GIN VDD PGND EN LGND Figure 2. 17511A Simplified Internal Block Diagram 17511A 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS C2L C1H C1L VM VDD IN1 IN2 EN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C2H CRES GOUT OUT2 PGND OUT1 GIN LGND Figure 3. VMFP Pin Connections Table 1. VMFP Pin Function Description Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name C2L C1H C1L VM VDD IN1 IN2 EN LGND GIN OUT1 PGND OUT2 GOUT CRES C2H Formal Name Charge Pump 2L Charge Pump 1H Charge Pump 1L Motor Drive Power Supply Logic Supply Input Control 1 Input Control 2 Enable Control Logic Ground Gate Driver Input H-Bridge Output 1 Power Ground H-Bridge Output 2 Gate Driver Output Charge Pump Output Capacitor Connection Charge Pump 2H Definition Charge pump bucket capacitor 2 (negative pole). Charge pump bucket capacitor 1 (positive pole). Charge pump bucket capacitor 1 (negative pole). Driver power supply voltage input pin. Control circuit power supply pin. Control signal input 1 Control signal input 2. Enable control signal input pin. Logic ground pin. LOW = True control signal for GOUT pin. Driver output 1 (right half of H-Bridge). Driver ground pin. Driver output 2 (left half of H-Bridge). Output gate driver signal to external MOSFET switch. Charge pump reservoir capacitor pin. Charge pump bucket capacitor 2 (positive pole). 17511A Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS VM VM VM VM NC NC 1 2 3 4 5 6 24 23 22 21 20 19 CRES C1H C2H C1L C2L GOUT 18 17 16 15 14 13 NC OUT2 PGND PGND OUT1 NC 7 VDD 8 IN1 9 10 11 12 IN2 EN LGND GIN Figure 4. QFN Pin Connections Table 2. QFN Pin Function Description Pin Number 1, 2, 3, 4 5, 6, 13, 18 7 8 9 10 11 12 14 15, 16 17 19 20 21 22 23 24 Pin Name VM NC VDD IN1 IN2 EN LGND GIN OUT1 PGND OUT2 GOUT CRES C2H C2L C1H C1L Formal Name Motor Drive Power Supply No Connect Logic Supply Logic Input Control 1 Logic Input Control 2 Enable Control Logic Ground Gate Driver Input Output 1 Power Ground Output 2 Gate Driver Output Pre-Driver Power Supply Charge Pump 2H Charge Pump 2L Charge Pump 1H Charge Pump 1L Definition Driver power supply voltage input pin. This pin is not used. Control circuit power supply pin. Control signal input 1. Control signal input 2. Enable control signal input pin. Logic ground pin. LOW = True control signal for GOUT pin. Driver output 1 (right half of H-Bridge). Driver ground pin. Driver output 2 (left half of H-Bridge). Output gate driver signal to external MOSFET switch. Pre-driver circuit power supply pin. Charge pump bucket capacitor 2 (positive pole). Charge pump bucket capacitor 2 (negative pole). Charge pump bucket capacitor 1 (positive pole). Charge pump bucket capacitor 1 (negative pole). 17511A 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding the ratings may cause a malfunction or permanent damage to the device. Rating Motor Supply Voltage Charge Pump Output Voltage Logic Supply Voltage Signal Input Voltage (EN, IN1, IN2, GIN) Driver Output Current Continuous Peak (1) ESD Voltage (2) Human Body Model Machine Model Storage Temperature Range Operating Ambient Temperature Operating Junction Temperature Thermal Resistance 24 Pin QFN 16 Pin VMFP Power Dissipation (4) 24 Pin QFN 16 Pin VMFP Soldering Temperature (5) (6), (7) (3) Symbol VM VCRES VDD VIN IO IOPK VESD1 VESD2 TSTG TA TJ RθJA Value -0.5 to 8.0 -0.5 to 14.0 -0.5 to 7.0 -0.5 to VDD + 0.5 1.0 3.0 Unit V V V V A V ±1800 ± 100 -65 to 150 -20 to 65 -20 to 150 °C °C °C °C/W 50 150 PD 2500 830 TSOLDER TPPRT 260 Note 7 °C °C mW Peak Package Reflow Temperature During Reflow Notes 1. TA = 25°C, 10 ms pulse width at 200 ms intervals. 2. 3. 4. 5. 6. 7. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). QFN24: 45 x 30 x 1 [mm] glass EPOXY board mount. (See: recommended heat pattern) VMFP16: 37 x 50 x 1.6 [mm] glass EPOXY board mount. When the exposed pad is bonded, Rsj will not be performed. Maximum at TA = 25°C. When the exposed pad is bonded, Rsj will not be performed. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 17511A Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions TA = 25°C, VM = VDD = 5.0V, GND = 0V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic POWER Driver Circuit Power Supply Voltage Logic Supply Voltage Capacitor for Charge Pump Standby Power Supply Current Motor Supply Standby Current Logic Supply Standby Current Operating Power Supply Current Logic Supply Current (9) Charge Pump Circuit Supply Current Low VDD Detection Voltage (10) Driver Output ON Resistance (11) GATE DRIVE Gate Drive Voltage (12) No Current Load Gate Drive Ability (Internally Supplied) I CRES = -1.0 mA VC (8) Symbol Min Typ Max Unit VM VDD C1, C2, C3 I I VMSTBY 2.0 2.7 0.01 5.0 5.0 0.1 6.8 5.7 1.0 V V μF μA mA – – – – 1.0 1.0 VDDSTBY VDD IC I – – 1.5 – – – 2.0 0.46 3.0 0.7 2.5 0.60 mA mA V Ω RES VDDDET RDS(ON) VC VC RES V 12 13 13.5 V 10 VC 11.2 – VC V RESLOAD Gate Drive Output IOUT = -50 μA lIN = 50 μA CONTROL LOGIC Logic Input Voltage Logic Input Function (2.7V < VDD < 5.7V) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current Pull-Up Resistance (EN, GIN) Notes 8. 9. 10. 11. 12. I I VDDSTBY includes current to the predriver circuit. VDD includes current to the predriver circuit. VIH VIL IIH IIL RPU VIN VGOUTHIGH VGOUTLOW RES- 0.5 RES- 0.1 RES LGND LGND + 0.1 LGND + 0.5 0 – VDD – VDD x 0.3 1.0 – 200 V VDD x 0.7 – – -1.0 50 – – – – 100 V V μA μA kΩ Detection voltage is defined as when the output becomes high-impedance after VDD drops below the detection threshold. When the V V gate voltage CRES is applied from an external source, CRES = 7.5V. IO = 1.0A source + sink. Input logic signal not present. 17511A 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions TA = 25°C, VM = VDD = 5.0V, GND = 0V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic INPUT (EN, IN1, IN2, GIN) Pulse Input Frequency Input Pulse Rise Time Input Pulse Fall Time OUTPUT Propagation Delay Time Turn-ON Time Turn-OFF Time GOUT Propagation Delay Time Turn-ON Time Turn-OFF Time Charge Pump Circuit Rise Time (17) (16) (13) Symbol Min Typ Max Unit fIN tR tF – – – – – – 200 1.0 1.0 (14) (14) kHz μs μs (15) μs tPLH tPHL tSON tSOFF tVCRESON – – 0.55 0.55 1.0 1.0 μs – – 0.15 0.15 0.5 0.5 ms – 0.1 – 3.0 10 ms Low-Voltage Detection Time Notes 13. 14. 15. 16. 17. Time is defined between 10% and 90%. That is, the input waveform slope must be steeper than this. Time is defined between 90% and 10%. When C1 = C2 = C3 = 0.1 μF. Time to charge CRES to 11V after application of VDD. t VDDDET – 17511A Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS EN, IN1, IN2 (GIN) VDDDETON 50% 2.5 V/3.5 V 50% VDDDETOFF tPLH (tSON) OUT1, OUT2 (GOUT) 90% 10% (tSOFF) IM tPHL VDD 0.8 V/ 1.5 V t VDDDET t 90% VDDDET 0% ( VCRES /0.02 Ω RG NC NC NC NC 0.01 μF C1L C1H C2L C2H CRES EN GIN IN1 IN2 VDD VM GOUT OUT1 Motor OUT2 GND Solenoid MCU NC = No Connect Figure 7. 17511A Typical Application Diagram CEMF SNUBBING TECHNIQUES Care must be taken to protect the IC from potentially damaging CEMF spikes induced when commutating currents in inductive loads. Typical practice is to provide snubbing of voltage transients via placing a capacitor or zener at the supply pin (VM) (see Figure 8). 5.0 V 5.0 V 17511A VM VDD C1L C1H OUT1 C2L C2H CRES OUT2 5.0 V 5.0 V 17511A VM VDD C1L C1H OUT1 C2L C2H CRES OUT2 GND GND Figure 8. CEMF Snubbing Techniques 17511A Analog Integrated Circuit Device Data Freescale Semiconductor 11 PACKAGING SOLDERING PACKAGING SOLDERING THERMAL PERFORMANCE Below are the recommended heat patterns for the QFN24 Exposed Pad thermal package. Obverse Figure 9. Recomended Heat Patterns for QFN24 EP Reverse 17511A 12 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EV (PB-FREE) SUFFIX 16-PIN VMFP PLASTIC PACKAGE 98ASA10614D ISSUE B 17511A Analog Integrated Circuit Device Data Freescale Semiconductor 13 PACKAGING PACKAGE DIMENSIONS PACKAGE DIMENSIONS (CONTINUED) EP (PB-FREE) SUFFIX 24-PIN QFN NON-LEADED PACKAGE 98ARL10577D ISSUE B 17511A 14 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE DIMENSIONS PACKAGE DIMENSIONS (CONTINUED) 17511A Analog Integrated Circuit Device Data Freescale Semiconductor 15 REVISION HISTORY REVISION HISTORY REVISION 2.0 DATE 4/2007 DESCRIPTION OF CHANGES • • • • • • Implemented Revision History page Converted to Freescale format Added Peak Package Reflow Temperature During Reflow (solder reflow) parameter and Note with instructions from www.freescale.com to Maximum Ratings Table 3 Replaced 16 pin package drawing with 98ASA10614D, REV. B and replaced 24 pin package drawing with 98ARL10577D, REV. B. Revised Siplified Application Diagram on page 1; Corrected typo - VM voltage from 15V to 5V. Further Defined Thermal Resistance and Power Disapation in Table 2, Page 5 for both packages. 3.0 4.0 5.0 11/2007 2/2008 8/2008 17511A 16 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. 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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2008. All rights reserved. MPC17511A Rev. 5.0 9/2008