MPC8309EC

Freescale Semiconductor Technical Data Document Number: MPC8309EC Rev. 0, 03/2011 MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications This document provides an overview of the MPC8309 PowerQUICC II Pro processor features. The MPC8309 is a cost-effective, highly integrated communications processor that addresses the requirements of several networking applications, including residential gateways, modem/routers, industrial control, and test and measurement applications. The MPC8309 extends current PowerQUICC offerings, adding higher CPU performance, additional functionality, and faster interfaces, while addressing the requirements related to time-to-market, price, power consumption, and board real estate. This document describes the electrical characteristics of MPC8309. To locate published errata or updates for this document, refer to the MPC8309 product summary page on our website listed on the back cover of this document or contact your local Freescale sales office. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 14 DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Ethernet and MII Management . . . . . . . . . . . . . . . . . 23 TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 HDLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 eSDHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 53 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 System Design Information . . . . . . . . . . . . . . . . . . . 76 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79 Document Revision History . . . . . . . . . . . . . . . . . . . 81 © 2011 Freescale Semiconductor, Inc. All rights reserved. Overview 1 Overview The MPC8309 incorporates the e300c3 (MPC603e-based) core built on Power Architecture® technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The MPC8309 also includes a 32-bit PCI controller, two DMA engines and a 16/32-bit DDR2 memory controller with 8-bit ECC. A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8309. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the device—the unified communication controllers (UCCs). A block diagram of the MPC8309 is shown in Figure 1. 2x DUART I2C Timers GPIO SPI RTC e300c3 Core with Power Management 16-KB I-Cache Interrupt Controller FPU 16-KB D-Cache ULPI USB 2.0 HS Host/Device/OTG Enhanced Local Bus DDR2 Controller QUICC Engine™ Block Accelerators Baud Rate Generators 16 KB Multi-User RAM 48 KB Instruction RAM Single 32-bit RISC CP Serial DMA UCC1 UCC2 UCC3 UCC5 UCC7 4 FlexCAN IO Sequencer eSDHC DMA Engine 2 DMA Engine 1 PCI Controller Time Slot Assigner Serial Interface 2x TDM Ports 2x HDLC 2 RMII/MII 1 RMII/MII 2x IEEE 1588 Figure 1. MPC8309 Block Diagram Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps Ethernet and HDLC. In summary, the MPC8309 provides users with a highly integrated, fully programmable communications processor. This helps to ensure that a low-cost system solution can be quickly developed and offers flexibility to accommodate new standards and evolving system requirements. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 2 Freescale Semiconductor Overview 1.1 Features The major features of the device are as follows: • e300c3 Power Architecture processor core — Enhanced version of the MPC603e core — High-performance, superscalar processor core with a four-stage pipeline and low interrupt latency times — Floating-point, dual integer units, load/store, system register, and branch processing units — 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities — Dynamic power management — Enhanced hardware program debug features — Software-compatible with Freescale processor families implementing Power Architecture technology — Separate PLL that is clocked by the system bus clock — Performance monitor • QUICC Engine block — 32-bit RISC controller for flexible support of the communications peripherals with the following features: – One clock per instruction – Separate PLL for operating frequency that is independent of system’s bus and e300 core frequency for power and performance optimization – 32-bit instruction object code – Executes code from internal IRAM – 32-bit arithmetic logic unit (ALU) data path – Modular architecture allowing for easy functional enhancements – Slave bus for CPU access of registers and multiuser RAM space – 48 Kbytes of instruction RAM – 16 Kbytes of multiuser data RAM – Serial DMA channel for receive and transmit on all serial channels — Five unified communication controllers (UCCs) supporting the following protocols and interfaces: – 10/100 Mbps Ethernet/IEEE Std. 802.3® through MII and RMII interfaces. – IEEE Std. 1588™ support – HDLC/Transparent (bit rate up to QUICC Engine operating frequency / 8) – HDLC Bus (bit rate up to 10 Mbps) – Asynchronous HDLC (bit rate up to 2 Mbps) – Two TDM interfaces supporting up to 128 QUICC multichannel controller channels, each running at 64 kbps MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 3 Overview • • • For more information on QUICC Engine sub-modules, see QUICC Engine Block Reference Manual with Protocol Interworking. DDR SDRAM memory controller — Programmable timing supporting DDR2 SDRAM — Integrated SDRAM clock generation — Supports 8-bit ECC — 16/32-bit data interface, up to 333-MHz data rate — 14 address lines — The following SDRAM configurations are supported: – Up to two physical banks (chip selects), 512-Mbyte addressable space for 32 bit data interface64-Mbit to 2-Gbit devices with x8/x16/x32 data ports (no direct x4 support) — One 16-bit device or two 8-bit devices on a 16-bit bus, or two 16-bit devices or four 8-bit devices on a 32-bit busSupport for up to 16 simultaneous open pages for DDR2 — Two clock pair to support up to 4 DRAM devices — Supports auto refresh — On-the-fly power management using CKE Enhanced local bus controller (eLBC) — Multiplexed 26-bit address and 8-/16-bit data operating at up to 66 MHz — Eight chip selects supporting eight external slaves – Four chip selects dedicated – Four chip selects offered as multiplexed option — Supports boot from parallel NOR Flash and parallel NAND Flash — Supports programmable clock ratio dividers — Up to eight-beat burst transfers — 16- and 8-bit ports, seperate LWE for each 8 bit — Three protocol engines available on a per chip select basis: – General-purpose chip select machine (GPCM) – Three user programmable machines (UPMs) – NAND Flash control machine (FCM) — Variable memory block sizes for FCM, GPCM, and UPM mode — Default boot ROM chip select with configurable bus width (8 or 16) — Provides two Write Enable signals to allow single byte write access to external 16-bit eLBC slave devices Integrated programmable interrupt controller (IPIC) — Functional and programming compatibility with the MPC8260 interrupt controller — Support for external and internal discrete interrupt sources — Programmable highest priority request — Six groups of interrupts with programmable priority MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 4 Freescale Semiconductor Overview • • — External and internal interrupts directed to host processor — Unique vector number for each interrupt source PCI interface — Designed to comply with PCI Local Bus Specification, Revision 2.3 — 32-bit PCI interface operating at up to 66 MHz — PCI 3.3-V compatible — Not 5-V compatible — Support for host and agent modes — Support for PCI-to-memory and memory-to-PCI streaming — Memory prefetching of PCI read accesses and support for delayed read transactions — Support for posting of processor-to-PCI and PCI-to-memory writes — On-chip arbitration, supporting three masters on PCI — Arbiter support for two-level priority request/grant signal pairs — Support for accesses to all PCI address spaces — Support for parity — Selectable hardware-enforced coherency — Address translation units for address mapping between host and peripheral — Mapping from an external 32-/64-bit address space to the internal 32-bit local space — Support for dual address cycle (DAC) (as a target only) — Internal configuration registers accessible from PCI — Selectable snooping for inbound transactions — Four outbound Translation Address Windows – Support for mapping 32-bit internal local memory space to an external 32-bit PCI address space and translating that address within the PCI space — Four inbound Translation Address Windows corresponding to defined PCI BARs – The first BAR is 32-bits and dedicated to on-chip register access – The second BAR is 32-bits for general use – The remaining two BARs may be 32- or 64-bits and are also for general use Enhanced secure digital host controller (eSDHC) — Compatible with the SD Host Controller Standard Specification Version 2.0 with test event register support — Compatible with the MMC System Specification Version 4.2 — Compatible with the SD Memory Card Specification Version 2.0 and supports the high capacity SD memory card — Compatible with the SD Input/Output (SDIO) Card Specification, Version 2.0 — Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC, MMCplus, and RS-MMC cards — Card bus clock frequency up to 33.25 MHz. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 5 Overview • • • • • — Supports 1-/4-bit SD and SDIO modes, 1-/4-bit modes – Up to 133 Mbps data transfer for SD/SDIO/MMC cards using 4 parallel data lines — Supports block sizes of 1 ~ 4096 bytes Universal serial bus (USB) dual-role controller — Designed to comply with Universal Serial Bus Revision 2.0 Specification — Supports operation as a stand-alone USB host controller — Supports operation as a stand-alone USB device — Supports high-speed (480-Mbps), full-speed (12-Mbps), and low-speed (1.5-Mbps) operations. Low speed is only supported in host mode. FlexCAN module — Full implementation of the CAN protocol specification version 2.0B — Up to 64 flexible message buffers of zero to eight bytes data length — Powerful Rx FIFO ID filtering, capable of matching incoming IDs — Selectable backwards compatibility with previous FlexCAN module version — Programmable loop-back mode supporting self-test operation — Global network time, synchronized by a specific message — Independent of the transmission medium (an external transceiver is required) — Short latency time due to an arbitration scheme for high-priority messages Dual I2C interfaces — Two-wire interface — Multiple-master support — Master or slave I2C mode support — On-chip digital filtering rejects spikes on the bus — I2C1 can be used as the boot sequencer DMA Engine1 — Support for the DMA engine with the following features: – Sixteen DMA channels – All data movement via dual-address transfers: read from source, write to destination – Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations – Channel activation via one of two methods (for both the methods, one activation per execution of the minor loop is required): – Explicit software initiation – Initiation via a channel-to-channel linking mechanism for continuous transfers (independent channel linking at end of minor loop and/or major loop) – Support for fixed-priority and round-robin channel arbitration – Channel completion reported via optional interrupt requests — Support for scatter/gather DMA processing IO Sequencer MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 6 Freescale Semiconductor Electrical Characteristics • • • • • • • • Direct memory access (DMA) controller (DMA Engine 2) — Four independent fully programmable DMA channels — Concurrent execution across multiple channels with programmable bandwidth control — Misaligned transfer capability for source/destination address — Data chaining and direct mode — Interrupt on completed segment, error, and chain DUART — Supports 2 DUART — Each has two2-wire interfaces (RxD, TxD) – The same can be configured as one 4-wire interface (RxD, TxD, RTS, CTS) — Programming model compatible with the original 16450 UART and the PC16550D Serial peripheral interface (SPI) — Master or slave support Power management controller (PMC) — Supports core doze/nap/sleep/ power management — Exits low power state and returns to full-on mode when – The core internal time base unit invokes a request to exit low power state – The power management controller detects that the system is not idle and there are outstanding transactions on the internal bus or an external interrupt. Parallel I/O — General-purpose I/O (GPIO) – 56 parallel I/O pins multiplexed on various chip interfaces – Interrupt capability System timers — Periodic interrupt timer — Software watchdog timer — Eight general-purpose timers Real time clock (RTC) module — Maintains a one-second count, unique over a period of thousand of years — Two possible clock sources: – External RTC clock (RTC_PIT_CLK) – CSB bus clock IEEE Std. 1149.1™ compliant JTAG boundary scan 2 Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8309. The MPC8309 is currently targeted to these specifications. Some of these specifications are MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 7 Electrical Characteristics independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. 2.1 Overall DC Electrical Characteristics This section covers the ratings, conditions, and other characteristics. 2.1.1 Absolute Maximum Ratings Table 1. Absolute Maximum Ratings1 Characteristic Symbol VDD AVDD1 AVDD2 AVDD3 GVDD OVDD Max Value –0.3 to 1.26 –0.3 to 1.26 Unit V V Notes — — Table 1 provides the absolute maximum ratings. Core supply voltage PLL supply voltage DDR2 DRAM I/O voltage PCI, Local bus, DUART, system control and power management, I2C, SPI, MII, RMII, MII management, eSDHC, FlexCAN,USB and JTAG I/O voltage Input voltage DDR2 DRAM signals DDR2 DRAM reference Local bus, DUART, SYS_CLK_IN, system control and power management, I2C, SPI, and JTAG signals PCI Storage temperature range –0.3 to 1.98 –0.3 to 3.6 V V — 2 MVIN MVREF OVIN –0.3 to (GVDD + 0.3) –0.3 to (GVDD + 0.3) –0.3 to (OVDD + 0.3) V V V 3 3 4 OVIN TSTG –0.3 to (OVDD + 0.3) –55 to 150 V C — Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. OVDD here refers to NVDDA, NVDDB,NVDDC, NVDDF, NVDDG, and NVDDH from the ball map. 3. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. 4. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during power-on reset and power-down sequences. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 8 Freescale Semiconductor Electrical Characteristics 2.1.2 Power Supply Voltage Specification Table 2 provides the recommended operating conditions for the MPC8309. Note that these values are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic Core supply voltage PLL supply voltage Symbol VDD AVDD1 AVDD2 AVDD3 GVDD OVDD Recommended Value 1.0 V ± 50 mV 1.0 V ± 50 mV Unit V V Notes 1 1 DDR2 DRAM I/O voltage PCI, Local bus, DUART, system control and power management, I2C, SPI, MII, RMII, MII management, eSDHC, FlexCAN,USB and JTAG I/O voltage Junction temperature 1.8 V ± 100 mV 3.3 V ± 300 mV V V 1 1, 3 TA/TJ 0 to 105 C 2 Note: 1. GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative direction. 2. Minimum temperature is specified with TA(Ambient Temperature); maximum temperature is specified with TJ(Junction Temperature). 3. OVDD here refers to NVDDA, NVDDB,NVDDC, NVDDF, NVDDG, and NVDDH from the ball map. Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8309 G/OVDD + 20% G/OVDD + 5% VIH G/OVDD GND GND – 0.3 V VIL GND – 0.7 V Not to Exceed 10% of tinterface1 Note: 1. tinterface refers to the clock period associated with the bus clock interface. Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 9 Electrical Characteristics 2.1.3 Output Driver Characteristics Table 3. Output Drive Capability Driver Type Output Impedance () 42 25 18 42 42 GVDD = 1.8 OVDD = 3.3 OVDD = 3.3 Supply Voltage (V) OVDD = 3.3 Table 3 provides information on the characteristics of the output driver strengths. Local bus interface utilities signals PCI Signal DDR2 signal DUART, system control, I2C, SPI, JTAG GPIO signals 2.1.4 Input Capacitance Specification Table 4. Input Capacitance Specification Parameter/Condition Symbol CI CICLK_IN Min 6 10 Max 8 — Unit pF pF Notes — 1 Table 4 describes the input capacitance for the SYS_CLK_IN pin in the MPC8309. Input capacitance for all pins except SYS_CLK_IN and QE_CLK_IN Input capacitance for SYS_CLK_IN and QE_CLK_IN Note: 1. The external clock generator should be able to drive 10 pF. 2.2 Power Sequencing The device does not require the core supply voltage (VDD) and IO supply voltages (GVDD and OVDD) to be applied in any particular order. Note that during power ramp-up, before the power supplies are stable and if the I/O voltages are supplied before the core voltage, there might be a period of time that all input and output pins are actively driven and cause contention and excessive current. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage (VDD) before the I/O voltage (GVDD and OVDD) and assert PORESET before the power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90% of its nominal value before the I/O supplies reach 0.7 V; see Figure 3. Once both the power supplies (I/O voltage and core voltage) are stable, wait for a minimum of 32 clock cycles before negating PORESET. NOTE There is no specific power down sequence requirement for the device. I/O voltage supplies (GVDD and OVDD) do not have any ordering requirements with respect to one another. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 10 Freescale Semiconductor Power Characteristics V I/O Voltage (GVDD and OVDD) Core Voltage (VDD) 90% 0.7 V 0 PORESET >= 32  tSYS_CLK_IN t Figure 3. MPC8309 Power-Up Sequencing Example 3 Power Characteristics Table 5. Core Frequency (MHz) 266 333 400 417 QUICC Engine Frequency (MHz) 200 200 200 233 The typical power dissipation for this family of MPC8309 devices is shown in Table 5. MPC8309 Power Dissipation CSB Frequency (MHz) 133 133 133 167 Typical 0.341 0.361 0.381 0.429 Maximum 0.920 0.938 0.969 1.003 Unit W W W W Notes 1, 2,3 1,2,3 1,2,3 1,2,3 Notes: 1. The values do not include I/O supply power (OVDD and GVDD), but it does include VDD and AVDD power . For I/O power values, see Table 6. 2. Typical power is based on a nominal voltage of VDD = 1.0 V, ambient temperature, and the core running a Dhrystone benchmark application. The measurements were taken on the evaluation board using WC process silicon. 3. Maximum power is based on a voltage of VDD = 1.05 V, WC process, a junction TJ = 105C, and an smoke test code. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 11 Power Characteristics Table 6 shows the estimated typical I/O power dissipation for the device. Table 6. Typical I/O Power Dissipation Interface DDR I/O 65% utilization 1.8 V Rs = 20  Rt = 50  1 pair of clocks Local bus I/O load = 25 pF 1 pair of clocks QUICC Engine block and other I/Os Parameter 266 MHz, 1  16 bits 0.149 GVDD (1.8 V) OVDD (3.3 V) — Unit W Comments — 66 MHz, 26 bits TDM serial, HDLC/TRAN serial, DUART, MII, RMII, Ethernet management, USB, PCI, SPI , Timer output FlexCAN eSDHC — 0.415 W 1 Note: 1. Typical IO power is based on a nominal voltage of VDD = 3.3V, ambient temperature, and the core running a Dhrystone benchmark application. The measurements were taken on the evaluation board using WC process silicon. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 12 Freescale Semiconductor Clock Input Timing 4 Clock Input Timing NOTE The rise/fall time on QUICC Engine input pins should not exceed 5 ns. This should be enforced especially on clock signals. Rise time refers to signal transitions from 10% to 90% of OVDD; fall time refers to transitions from 90% to 10% of OVDD. This section provides the clock input DC and AC electrical characteristics for the MPC8309. 4.1 DC Electrical Characteristics Table 7 provides the clock input (SYS_CLK_IN/PCI_SYNC_IN) DC specifications for the MPC8309. These specifications are also applicable for QE_CLK_IN. Table 7. SYS_CLK_IN DC Electrical Characteristics Parameter Input high voltage Input low voltage SYS_CLK_IN input current SYS_CLK_IN input current SYS_CLK_IN input current Condition — — 0 V  VIN  OVDD 0 V  VIN  0.5 V or OVDD – 0.5 V  VIN OVDD 0.5 V  VIN  OVDD – 0.5 V Symbol VIH VIL IIN IIN IIN Min 2.4 –0.3 — — — Max OVDD + 0.3 0.4 ±5 ±5 ±50 Unit V V A A A 4.2 AC Electrical Characteristics The primary clock source for the MPC8309 can be one of two inputs, SYS_CLK_IN or PCI_SYNC_IN, depending on whether the device is configured in PCI host or agent mode. Table 8 provides the clock input (SYS_CLK_IN/PCI_SYNC_IN) AC timing specifications for the MPC8309. These specifications are also applicable for QE_CLK_IN. Table 8. SYS_CLK_IN AC Timing Specifications Parameter/Condition SYS_CLK_IN frequency SYS_CLK_IN cycle time SYS_CLK_IN rise and fall time PCI_SYNC_IN rise and fall time Symbol fSYS_CLK_IN tSYS_CLK_IN tKH, tKL tPCH, tPCL Min 24 15 1.1 1.1 Typical — — — — Max 66.67 41.6 2.8 2.8 Unit MHz ns ns ns Notes 1 — 2 2 MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 13 RESET Initialization Table 8. SYS_CLK_IN AC Timing Specifications SYS_CLK_IN duty cycle SYS_CLK_IN jitter tKHK/tSYS_CLK_ IN 40 — — — 60 ±150 % ps 3 4, 5 — Notes: 1. Caution: The system, core and QUICC Engine block must not exceed their respective maximum or minimum operating frequencies. 2. Rise and fall times for SYS_CLK_IN are measured at 0.33 and 2.97 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter—short term and long term—and is guaranteed by design. 5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter. 6. Spread spectrum is allowed upto 1% down-spread @ 33kHz (max rate). 5 RESET Initialization This section describes the AC electrical specifications for the reset initialization timing requirements of the MPC8309. Table 9 provides the reset initialization AC timing specifications for the reset component(s). Table 9. RESET Initialization Timing Specifications Parameter/Condition Required assertion time of HRESET to activate reset flow Required assertion time of PORESET with stable clock applied to SYS_CLK_IN or PCI_SYNC_IN (in agent mode) HRESET assertion (output) Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]) with respect to negation of PORESET Input hold time for POR config signals with respect to negation of HRESET Min 32 32 512 4 0 Max — — — — — Unit tSYS_CLK_IN tSYS_CLK_IN tSYS_CLK_IN tSYS_CLK_IN ns Notes 1 1 1 1, 2 1, 2 Notes: 1. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. For more details, see the MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual. 2. POR configuration signals consists of CFG_RESET_SOURCE[0:3]. Table 10 provides the PLL lock times. Table 10. PLL Lock Times Parameter/Condition PLL lock times Min — Max 100 Unit s Notes — 5.1 Reset Signals DC Electrical Characteristics Table 11 provides the DC electrical characteristics for the MPC8309 reset signals mentioned in Table 9. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 14 Freescale Semiconductor DDR2 SDRAM Table 11. Reset Signals DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –6.0 mA IOL = 6.0 mA IOL = 3.2 mA — — 0 V  VIN  OVDD Min 2.4 — — 2.0 –0.3 — Max — 0.5 0.4 OVDD + 0.3 0.8 ±5 Unit V V V V V A Notes 1 1 1 1 — — Note: 1. This specification applies when operating from 3.3 V supply. 6 DDR2 SDRAM This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface of the MPC8309. Note that DDR2 SDRAM is GVDD(typ) = 1.8 V. 6.1 DDR2 SDRAM DC Electrical Characteristics Table 12 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MPC8309 when GVDD(typ) = 1.8 V. Table 12. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.35 V) Output low current (VOUT = 0.280 V) Symbol GVDD MVREF VTT VIH VIL IOZ IOH IOL Min 1.7 0.49  GVDD MVREF – 0.04 MVREF+ 0.125 –0.3 –9.9 –13.4 13.4 Max 1.9 0.51  GVDD MVREF + 0.04 GVDD + 0.3 MVREF – 0.125 9.9 — — Unit V V V V V A mA mA Notes 1 2 3 — — 4 — — Notes: 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MVREF is expected to be equal to 0.5  GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed ±2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V  VOUT GVDD. Table 13 provides the DDR2 capacitance when GVDD(typ) = 1.8 V. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 15 DDR2 SDRAM Table 13. DDR2 SDRAM Capacitance for GVDD(typ) = 1.8 V Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Symbol CIO CDIO Min 6 — Max 8 0.5 Unit pF pF Notes 1 1 Note: 1. This parameter is sampled. GVDD = 1.8 V ± 0.100 V, f = 1 MHz, TA = 25 °C, VOUT = GVDD  2, VOUT (peak-to-peak) = 0.2 V. 6.2 DDR2 SDRAM AC Electrical Characteristics This section provides the AC electrical characteristics for the DDR2 SDRAM interface. 6.2.1 DDR2 SDRAM Input AC Timing Specifications Table 14. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface Table 14 provides the input AC timing specifications for the DDR2 SDRAM (GVDD(typ) = 1.8 V). At recommended operating conditions with GVDD of 1.8 V± 100mV. Parameter AC input low voltage AC input high voltage Symbol VIL VIH Min — MVREF + 0.25 Max MVREF – 0.25 — Unit V V Notes — — Table 15 provides the input AC timing specifications for the DDR2 SDRAM interface. Table 15. DDR2 SDRAM Input AC Timing Specifications At recommended operating conditions with GVDD of 1.8V ± 100mV. Parameter Controller skew for MDQS—MDQ/MDM 266 MHz Symbol tCISKEW Min Max Unit ps Notes 1, 2 –750 750 Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is captured with MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be determined by the equation: tDISKEW = ±(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the absolute value of tCISKEW. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 16 Freescale Semiconductor DDR2 SDRAM Figure 4 shows the input timing diagram for the DDR controller. MCK[n] MCK[n] tMCK MDQS[n] MDQ[x] tDISKEW D0 D1 tDISKEW Figure 4. DDR Input Timing Diagram 6.2.2 DDR2 SDRAM Output AC Timing Specifications Table 16. DDR2 SDRAM Output AC Timing Specifications Table 16 provides the output AC timing specifications for the DDR2 SDRAM interfaces. At recommended operating conditions with GVDD of 1.8V ± 100mV. Parameter MCK cycle time, (MCK/MCK crossing) ADDR/CMD output setup with respect to MCK 333 MHz 266 MHz ADDR/CMD output hold with respect to MCK 333 MHz 266 MHz MCS output setup with respect to MCK 333 MHz 266 MHz MCS output hold with respect to MCK 333 MHz 266 MHz MCK to MDQS Skew Symbol1 tMCK tDDKHAS Min 5.988 Max 8 Unit ns ns Notes 2 3 2.4 2.5 tDDKHAX 2.4 2.5 tDDKHCS 2.4 2.5 tDDKHCX 2.4 2.5 tDDKHMH –0.6 — ns — ns — ns — 0.6 ns 4 3 3 3 MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 17 DDR2 SDRAM Table 16. DDR2 SDRAM Output AC Timing Specifications (continued) At recommended operating conditions with GVDD of 1.8V ± 100mV. Parameter MDQ/MDM output setup with respect to MDQS 333 MHz 266 MHz MDQ/MDM output hold with respect to MDQS 333 MHz 266 MHz MDQS preamble start MDQS epilogue end Symbol1 tDDKHDS, tDDKLDS Min Max Unit ns Notes 5 0.8 0.9 tDDKHDX, tDDKLDX 900 1100 tDDKHMP tDDKHME 0.75 x tMCK 0.4 x tMCK — ps — — 0.6 x tMCK ns ns 6 6 5 Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MDM/MDQS. For the ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied cycle. 4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. This is typically set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. 5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. tDDKHMP follows the symbol conventions described in note 1. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 18 Freescale Semiconductor DDR2 SDRAM Figure 5 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). MCK MCK tMCK tDDKHMH(max) = 0.6 ns MDQS tDDKHMH(min) = –0.6 ns MDQS Figure 5. Timing Diagram for tDDKHMH Figure 6 shows the DDR2 SDRAM output timing diagram. MCK[n] MCK[n] tMCK tDDKHAS ,tDDKHCS tDDKHAX ,tDDKHCX ADDR/CMD Write A0 tDDKHMP tDDKHMH MDQS[n] tDDKHDS tDDKLDS MDQ[x]/ MECC[x] tDDKHDX D0 D1 tDDKLDX tDDKHME NOOP Figure 6. DDR2 SDRAM Output Timing Diagram MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 19 Local Bus 7 7.1 Local Bus Local Bus DC Electrical Characteristics Table 17. Local Bus DC Electrical Characteristics Parameter Symbol VIH VIL VOH VOL IIN Min 2 –0.3 OVDD – 0.2 — — Max OVDD + 0.3 0.8 — 0.2 ±5 Unit V V V V A This section describes the DC and AC electrical specifications for the local bus interface of the MPC8309. Table 17 provides the DC electrical characteristics for the local bus interface. High-level input voltage Low-level input voltage High-level output voltage, IOH = –100 A Low-level output voltage, IOL = 100 A Input current 7.2 Local Bus AC Electrical Specifications Table 18. Local Bus General Timing Parameters Parameter Symbol1 tLBK tLBIVKH tLBIXKH tLBKHOV tLBKHOZ Min 15 7 1.0 — — Max — — — 3 4 Unit ns ns ns ns ns Notes 2 3, 4 3, 4 3 5 Table 18 describes the general timing parameters of the local bus interface of the MPC8309. Local bus cycle time Input setup to local bus clock (LCLKn) Input hold from local bus clock (LCLKn) Local bus clock (LCLKn) to output valid Local bus clock (LCLKn) to output high impedance for LAD/LDP Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). 2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of LCLK0 (for all other inputs). 3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4  OVDD of the signal in question for 3.3-V signaling levels. 4. Input timings are measured at the pin. 5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 20 Freescale Semiconductor Local Bus Figure 7 provides the AC test load for the local bus. Output Z0 = 50  RL = 50  OVDD/2 Figure 7. Local Bus AC Test Load Figure 8 through Figure 10 show the local bus signals. These figures has been given indicate timing parameters only and do not reflect actual functional operation of interface. LCLK[n] tLBIXKH tLBIVKH Input Signals: LAD[0:15] tLBIVKH Input Signal: LGTA tLBIXKH tLBKHOV Output Signals: LBCTL/LBCKE/LOE tLBKHOV Output Signals: LAD[0:15] tLBOTOT LALE tLBKHOZ tLBIXKH Figure 8. Local Bus Signals MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 21 Local Bus LCLK T1 T3 tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH Input Signals: LAD[0:15]/LDP[0:3] tLBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] tLBKHOZ tLBIXKH tLBIXKH tLBKHOZ Figure 9. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 22 Freescale Semiconductor Ethernet and MII Management LCLK T1 T2 T3 T4 tLBKHOV GPCM Mode Output Signals: LCS[0:3]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT tLBIVKH Input Signals: LAD[0:15] tLBKHOV UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] tLBKHOZ tLBIXKH tLBIXKH tLBKHOZ Figure 10. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 8 8.1 Ethernet and MII Management Ethernet Controller (10/100 Mbps)—MII/RMII Electrical Characteristics This section provides the AC and DC electrical characteristics for Ethernet interfaces. The electrical characteristics specified here apply to all MII (media independent interface) and RMII (reduced media independent interface), except MDIO (management data input/output) and MDC (management data clock). The MII and RMII are defined for 3.3 V. The electrical characteristics for MDIO and MDC are specified in Section 8.3, “Ethernet Management Interface Electrical Characteristics.” 8.1.1 DC Electrical Characteristics All MII and RMII drivers and receivers comply with the DC parametric attributes specified in Table 19. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 23 Ethernet and MII Management Table 19. MII and RMII DC Electrical Characteristics Parameter Supply voltage 3.3 V Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol OVDD VOH VOL VIH VIL IIN Conditions — IOH = –4.0 mA IOL = 4.0 mA — — OVDD = Min OVDD = Min — — Min 3 2.40 GND 2.0 –0.3 — Max 3.6 OVDD + 0.3 0.50 OVDD + 0.3 0.90 ±5 Unit V V V V V A 0 V  VIN  OVDD 8.2 MII and RMII AC Timing Specifications The AC timing specifications for MII and RMII are presented in this section. 8.2.1 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. 8.2.1.1 MII Transmit AC Timing Specifications Table 20. MII Transmit AC Timing Specifications Table 20 provides the MII transmit AC timing specifications. At recommended operating conditions with OVDD of 3.3 V ± 300mV. Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise VIL(min) to VIH(max) TX_CLK data clock fall VIH(max) to VIL(min) Symbol1 tMTX tMTX tMTXH/tMTX tMTKHDX tMTXR tMTXF Min — — 35 1 1.0 1.0 Typical 400 40 — 5 — — Max — — 65 15 4.0 4.0 Unit ns ns % ns ns ns Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 24 Freescale Semiconductor Ethernet and MII Management Figure 14 provides the AC test load. Output Z0 = 50  RL = 50  OVDD/2 Figure 11. AC Test Load Figure 12 shows the MII transmit AC timing diagram. tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR Figure 12. MII Transmit AC Timing Diagram 8.2.1.2 MII Receive AC Timing Specifications Table 21. MII Receive AC Timing Specifications Table 21 provides the MII receive AC timing specifications. At recommended operating conditions with OVDD of 3.3 V ± 300mV. Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise VIL(min) to VIH(max) RX_CLK clock fall time VIH(max) to VIL(min) Symbol1 tMRX tMRX tMRXH/tMRX tMRDVKH tMRDXKH tMRXR tMRXF Min — — 35 10.0 10.0 1.0 1.0 Typical 400 40 — — — — — Max — — 65 — — 4.0 4.0 Unit ns ns % ns ns ns ns Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 25 Ethernet and MII Management Figure 13 shows the MII receive AC timing diagram. tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKH tMRXF Valid Data tMRXR Figure 13. MII Receive AC Timing Diagram 8.2.2 RMII AC Timing Specifications This section describes the RMII transmit and receive AC timing specifications. 8.2.2.1 RMII Transmit AC Timing Specifications Table 22. RMII Transmit AC Timing Specifications Table 20 provides the RMII transmit AC timing specifications. At recommended operating conditions with OVDD of 3.3 V ± 300mV. Parameter/Condition REF_CLK clock REF_CLK duty cycle REF_CLK to RMII data TXD[1:0], TX_EN delay REF_CLK data clock rise VIL(min) to VIH(max) REF_CLK data clock fall VIH(max) to VIL(min) Symbol1 tRMX tRMXH/tRMX tRMTKHDX tRMXR tRMXF Min — 35 2 1.0 1.0 Typical 20 — — — — Max — 65 13 4.0 4.0 Unit ns % ns ns ns Note: 1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMTKHDX symbolizes RMII transmit timing (RMT) for the time tRMX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of tRMX represents the RMII(RM) reference (X) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 14 provides the AC test load. Output Z0 = 50  RL = 50  OVDD/2 Figure 14. AC Test Load MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 26 Freescale Semiconductor Ethernet and MII Management Figure 15 shows the RMII transmit AC timing diagram. tRMX REF_CLK tRMXH TXD[1:0] TX_EN tRMTKHDX tRMXF tRMXR Figure 15. RMII Transmit AC Timing Diagram 8.2.2.2 RMII Receive AC Timing Specifications Table 23. RMII Receive AC Timing Specifications Table 21 provides the RMII receive AC timing specifications. At recommended operating conditions with OVDD of 3.3 V ± 300mV. Parameter/Condition REF_CLK clock period REF_CLK duty cycle RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK REF_CLK clock rise VIL(min) to VIH(max) REF_CLK clock fall time VIH(max) to VIL(min) Symbol1 tRMX tRMXH/tRMX tRMRDVKH tRMRDXKH tRMXR tRMXF Min — 35 4.0 2.0 1.0 1.0 Typical 20 — — — — — Max — 65 — — 4.0 4.0 Unit ns % ns ns ns ns Note: 1. The symbols used for timing specifications follow the pattern of t(first three letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tRMRDVKH symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) reach the valid state (V) relative to the tRMX clock reference (K) going to the high (H) state or setup time. Also, tRMRDXKL symbolizes RMII receive timing (RMR) with respect to the time data input signals (D) went invalid (X) relative to the tRMX clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of tRMX represents the RMII (RM) reference (X) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 27 Ethernet and MII Management Figure 16 shows the RMII receive AC timing diagram. tRMX REF_CLK tRMXH RXD[1:0] CRS_DV RX_ER tRMRDVKH tRMRDXKH tRMXF Valid Data tRMXR Figure 16. RMII Receive AC Timing Diagram 8.3 Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for MII, and RMII are specified in Section 8.1, “Ethernet Controller (10/100 Mbps)—MII/RMII Electrical Characteristics.” 8.3.1 MII Management DC Electrical Characteristics MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 24. Table 24. MII Management DC Electrical Characteristics When Powered at 3.3 V Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage Input low voltage Input current Symbol OVDD VOH VOL VIH VIL IIN Conditions — IOH = –1.0 mA IOL = 1.0 mA — — 0 V  VIN  OVDD OVDD = Min OVDD = Min Min 3 2.40 GND 2.00 — — Max 3.6 OVDD + 0.3 0.50 — 0.80 ±5 Unit V V V V V A 8.3.2 MII Management AC Electrical Specifications Table 25. MII Management AC Timing Specifications Table 25 provides the MII management AC timing specifications. At recommended operating conditions with OVDD is 3.3 V ± 300mV. Parameter/Condition MDC frequency MDC period MDC clock pulse width high Symbol1 fMDC tMDC tMDCH Min — — 32 Typical 2.5 400 — Max — — — Unit MHz ns ns Notes — — — MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 28 Freescale Semiconductor Ethernet and MII Management Table 25. MII Management AC Timing Specifications (continued) At recommended operating conditions with OVDD is 3.3 V ± 300mV. Parameter/Condition MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MDC fall time Symbol1 tMDKHDX tMDDVKH tMDDXKH tMDCR tMDHF Min 10 8.5 0 — — Typical — — — — — Max 70 — — 10 10 Unit ns ns ns ns ns Notes — — — — — Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Figure 17 shows the MII management AC timing diagram. tMDC MDC tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX tMDCF tMDCR Figure 17. MII Management Interface Timing Diagram MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 29 Ethernet and MII Management 8.3.3 IEEE 1588 DC Specifications Table 26. IEEE 1588 DC Electrical Characteristics Characteristic Symbol VOH VOL VOL VIH VIL IIN Condition IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2mA — — 0V ≤ VIN ≤ OVDD Min 2.4 — — 2.0 - 0.3 — Max — 0.5 0.4 OVDD + 0.3 0.8 ±5 unit V V V V V μA The IEEE 1588 DC timing specifications are given in Table 27. Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current 8.3.4 IEEE 1588 AC Specifications Table 27. IEEE 1588 AC Timing Specifications The IEEE 1588 AC timing specifications are given in Table 27. At recommended operating conditions with OVDD of 3.3 V ± 300mV. Parameter/Condition QE_1588_CLK clock period QE_1588_CLK duty cycle QE_1588_CLK peak-to-peak jitter Rise time QE_1588_CLK (20%–80%) Fall time QE_1588_CLK (80%–20%) QE_1588_CLK_OUT clock period QE_1588_CLK_OUT duty cycle QE_1588_PULSE_OUT QE_1588_TRIG_IN pulse width Symbol tT1588CLK tT1588CLKH/tT1588CLK tT1588CLKINJ tT1588CLKINR tT1588CLKINF tT1588CLKOUT tT1588CLKOTH /tT1588CLKOUT tT1588OV tT1588TRIGH Min 2.5 40 — 1.0 1.0 2  tT1588CLK 30 0.5 2  tT1588CLK_MAX Typ — 50 — — — — 50 — — Max TRX_CLK  9 60 250 2.0 2.0 — 70 3.0 — Unit ns % ps ns ns ns % ns ns Notes 1, 3 — — — — — — — 2 Notes: 1.TRX_CLK is the max clock period of QUICC engine receiving clock selected by TMR_CTRL[CKSEL]. See the MPC PowerQUICC II Pro Integrated Processor Family Reference Manual, for a description of TMR_CTRL registers. 2. It need to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC PowerQUICC II Pro Integrated Processor Family Reference Manual, for a description of TMR_CTRL registers. 3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For example, for 10/100 Mbps modes, the maximum value of tT1588CLK is 3600 and 280ns, respectively. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 30 Freescale Semiconductor TDM/SI Figure 18 provides the data and command output timing diagram. tT1588CLKOUT tT1588CLKOUTH TSEC_1588_CLK_OUT tT1588OV TSEC_1588_PULSE_OUT TSEC_1588_TRIG_OUT Note: The output delay is count starting rising edge if tT1588CLKOUT is non-inverting. Otherwise, it is count starting falling edge. Figure 18. IEEE 1588 Output AC Timing Figure 19 provides the data and command input timing diagram. tT1588CLK tT1588CLKH TSEC_1588_CLK TSEC_1588_TRIG_IN tT1588TRIGH Figure 19. IEEE 1588 Input AC Timing 9 TDM/SI This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial interface of the MPC8309. 9.1 TDM/SI DC Electrical Characteristics Table 28. TDM/SI DC Electrical Characteristics Characteristic Symbol VOH VOL VIH VIL IIN Condition IOH = –2.0 mA IOL = 3.2 mA — — 0 V  VIN  OVDD Min 2.4 — 2.0 –0.3 — Max — 0.5 OVDD + 0.3 0.8 ±5 Unit V V V V A Table 28 provides the DC electrical characteristics for the MPC8309 TDM/SI. Output high voltage Output low voltage Input high voltage Input low voltage Input current MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 31 TDM/SI 9.2 TDM/SI AC Timing Specifications Table 29. TDM/SI AC Timing Specifications1 Characteristic Symbol2 tSEKHOV tSEKHOX tSEIVKH tSEIXKH Min 2 2 5 2 Max 14 10 — — Unit ns ns ns ns Table 29 provides the TDM/SI input and output AC timing specifications. TDM/SI outputs—External clock delay TDM/SI outputs—External clock High Impedance TDM/SI inputs—External clock input setup time TDM/SI inputs—External clock input hold time Notes: 1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSEKHOX symbolizes the TDM/SI outputs external timing (SE) for the time tTDM/SI memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Figure 20 provides the AC test load for the TDM/SI. Output Z0 = 50  RL = 50  OVDD/2 Figure 20. TDM/SI AC Test Load MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 32 Freescale Semiconductor HDLC Figure 21 represents the AC timing from Table 29. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. TDM/SICLK (Input) tSEIVKH tSEIXKH Input Signals: TDM/SI (See Note) Output Signals: TDM/SI (See Note) tSEKHOV tSEKHOX Note: The clock edge is selectable on TDM/SI. Figure 21. TDM/SI AC Timing (External Clock) Diagram 10 HDLC This section describes the DC and AC electrical specifications for the high level data link control (HDLC), of the MPC8309. 10.1 HDLC DC Electrical Characteristics Table 30. HDLC DC Electrical Characteristics Characteristic Symbol VOH VOL VIH VIL IIN Condition IOH = –2.0 mA IOL = 3.2 mA — — 0 V  VIN OVDD Min 2.4 — 2.0 –0.3 — Max — 0.5 OVDD + 0.3 0.8 ±5 Unit V V V V A Table 30 provides the DC electrical characteristics for the MPC8309 HDLC protocol. Output high voltage Output low voltage Input high voltage Input low voltage Input current 10.2 HDLC AC Timing Specifications Table 31. HDLC AC Timing Specifications1 Characteristic Symbol2 tHIKHOV tHEKHOV tHIKHOX Min 0 1 0 Max 9 12 5.5 Unit ns ns ns Table 31 provides the input and output AC timing specifications for HDLC protocol. Outputs—Internal clock delay Outputs—External clock delay Outputs—Internal clock high impedance MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 33 HDLC Table 31. HDLC AC Timing Specifications1 (continued) Characteristic Outputs—External clock high impedance Inputs—Internal clock input setup time Inputs—External clock input setup time Inputs—Internal clock input hold time Inputs—External clock input hold time Symbol2 tHEKHOX tHIIVKH tHEIVKH tHIIXKH tHEIXKH Min 1 9 4 0 1 Max 8 — — — — Unit ns ns ns ns ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Figure 22 provides the AC test load. Output Z0 = 50  RL = 50  OVDD/2 Figure 22. AC Test Load Figure 23 and Figure 24 represent the AC timing from Table 31. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 23 shows the timing with external clock. Serial CLK (Input) tHEIVKH Input Signals: (See Note) tHEKHOV Output Signals: (See Note) tHEKHOX Note: The clock edge is selectable. tHEIXKH Figure 23. AC Timing (External Clock) Diagram MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 34 Freescale Semiconductor PCI Figure 24 shows the timing with internal clock. Serial CLK (Output) tHIIVKH Input Signals: (See Note) tHIKHOV Output Signals: (See Note) Note: The clock edge is selectable. tHIKHOX tHIIXKH Figure 24. AC Timing (Internal Clock) Diagram 11 PCI This section describes the DC and AC electrical specifications for the PCI bus of the MPC8309. 11.1 PCI DC Electrical Characteristics Table 32. PCI DC Electrical Characteristics1,2 Parameter Symbol VIH VIL VOH VOL IIN Test Condition VOUT VOH (min) or VOUT  VOL (max) OVDD = min, IOH = –100 A OVDD = min, IOL = 100 A 0 V VIN OVDD Min 2 –0.3 OVDD – 0.2 — — Max OVDD + 0.3 0.8 — 0.2 ±5 Unit V V V V A Table 32 provides the DC electrical characteristics for the PCI interface of the MPC8309. High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Notes: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. 2. Ranges listed do not meet the full range of the DC specifications of the PCI 2.3 Local Bus Specifications. 11.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus of the MPC8309. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8309 is configured as a host or agent device. Table 33 shows the PCI AC timing specifications at 66 MHz. . Table 34 shows the PCI AC timing specifications at 33 MHz. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 35 PCI Table 33. PCI AC Timing Specifications at 66 MHz Parameter Clock to output valid Output hold from clock Clock to output high impedence Input setup to clock Input hold from clock Symbol1 tPCKHOV Min — 1 — 3.0 0 Max 6.0 — 14 — — Unit ns ns ns ns ns Notes 2 2 2, 3 2, 4 2, 4 tPCKHOX tPCKHOZ tPCIVKH tPCIXKH Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications. 3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. Table 34. PCI AC Timing Specifications at 33 MHz Parameter Clock to output valid Output hold from clock Clock to output high impedence Input setup to clock Input hold from clock Symbol1 tPCKHOV Min — 2 — 3.0 0 Max 11 — 14 — — Unit ns ns ns ns ns Notes 2 2 2, 3 2, 4 2, 4 tPCKHOX tPCKHOZ tPCIVKH tPCIXKH Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications. 3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. Figure 25 provides the AC test load for PCI. Output Z0 = 50  RL = 50  OVDD/2 Figure 25. PCI AC Test Load MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 36 Freescale Semiconductor USB Figure 26 shows the PCI input AC timing conditions. CLK tPCIVKH tPCIXKH Input Figure 26. PCI Input AC Timing Measurement Conditions Figure 27 shows the PCI output AC timing conditions. CLK tPCKHOV Output Delay tPCKHOZ High-Impedance Output tPCKHOX Figure 27. PCI Output AC Timing Measurement Condition 12 USB 12.1 USB Controller This section provides the AC and DC electrical specifications for the USB (ULPI) interface. 12.1.1 USB DC Electrical Characteristics Table 35. USB DC Electrical Characteristics Parameter Symbol VIH VIL IIN VOH VOL Min 2.0 –0.3 — OVDD – 0.2 — Max OVDD + 0.3 0.8 ±5 — 0.2 Unit V V A V V Table 35 provides the DC electrical characteristics for the USB interface. High-level input voltage Low-level input voltage Input current High-level output voltage, IOH = –100 A Low-level output voltage, IOL = 100 A 12.1.2 USB AC Electrical Specifications Table 36 describes the general timing parameters of the USB interface. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 37 USB Table 36. USB General Timing Parameters Parameter USB clock cycle time Input setup to USB clock—all inputs input hold to USB clock—all inputs USB clock to output valid—all outputs (except USBDR_STP_USBDR_STP) USB clock to output valid—USBDR_STP Output hold from USB clock—all outputs Symbol1 tUSCK tUSIVKH tUSIXKH tUSKHOV tUSKHOV tUSKHOX Min 15 4 1 — — 2 Max — — — 7 7.5 — Unit ns ns ns ns ns ns Notes Note: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (USB) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes us timing (USB) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. Figure 28 and Figure 29 provide the AC test load and signals for the USB, respectively. Output Z0 = 50  OVDD/2 RL = 50  Figure 28. USB AC Test Load USBDR_CLK tUSIVKH Input Signals tUSIXKH tUSKHOV Output Signals tUSKHOX Figure 29. USB Signals MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 38 Freescale Semiconductor DUART 13 DUART This section describes the DC and AC electrical specifications for the DUART interface of the MPC8309. 13.1 DUART DC Electrical Characteristics Table 37. DUART DC Electrical Characteristics Parameter Symbol VIH VIL VOH VOL IIN Min 2 –0.3 OVDD – 0.2 — — Max OVDD + 0.3 0.8 — 0.2 ±5 Unit V V V V A Table 37 provides the DC electrical characteristics for the DUART interface of the MPC8309. High-level input voltage Low-level input voltage OVDD High-level output voltage, IOH = –100 A Low-level output voltage, IOL = 100 A Input current (0 V VIN OVDD )1 Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2. 13.2 DUART AC Electrical Specifications Table 38. DUART AC Timing Specifications Parameter Value 256 >1,000,000 16 Unit baud baud — 1 2 Notes Table 38 provides the AC timing parameters for the DUART interface of the MPC8309. Minimum baud rate Maximum baud rate Oversample rate Notes: 1. Actual attainable baud rate is limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 39 eSDHC 14 eSDHC This section describes the DC and AC electrical specifications for the eSDHC interface of the device. 14.1 eSDHC DC Electrical Characteristics Table 39. eSDHC Interface DC Electrical Characteristics Table 39 provides the DC electrical characteristics for the eSDHC interface. At recommended operating conditions with OVDD = 3.3 V Characteristic Input high voltage Input low voltage Output high voltage Output low voltage Output high voltage Output low voltage Input/output leakage current Symbol VIH VIL VOH VOL VOH VOL IIN/IOZ Condition — — IOH = –100 A at OVDD min IOL = 100 A at OVDD min IOH = –100 mA IOL = 2 mA — Min 0.625  OVDD — 0.75  OVDD — OVDD – 0.2 — –10 Max — 0.25  OVDD — 0.125  OVDD — 0.3 10 Unit V V V V V V A Notes 1 1 — — 2 2 — Note: 1. Note that the min VILand max VIH values are based on the respective min and max OVIN values found in Table 2.. 2. Open drain mode for MMC cards only. 14.2 eSDHC AC Timing Specifications Table 40. eSDHC AC Timing Specifications Table 40 provides the eSDHC AC timing specifications as defined in Figure 30 and Figure 31. At recommended operating conditions with OVDD = 3.3 V Parameter SD_CLK clock frequency: SD/SDIO Full-speed/High-speed mode MMC Full-speed/High-speed mode SD_CLK clock low time—Full-speed/High-speed mode SD_CLK clock high time—Full-speed/High-speed mode SD_CLK clock rise and fall times Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK Symbol1 fSHSCK Min 0 Max 25/33.25 20/52 — — 3 — Unit MHz Notes 2, 4 tSHSCKL tSHSCKH tSHSCKR/ tSHSCKF tSHSIVKH 10/7 10/7 — 5 ns ns ns ns 4 4 4 4 MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 40 Freescale Semiconductor eSDHC Table 40. eSDHC AC Timing Specifications (continued) At recommended operating conditions with OVDD = 3.3 V Parameter Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK Output delay time: SD_CLK to SD_CMD, SD_DATx valid Symbol1 tSHSIXKH tSHSKHOV Min 2.5 –3 Max — 3 Unit ns ns Notes 3, 4 4 Notes: 1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. In full-speed mode, the clock freqency value can be 0–25 MHz for an SD/SDIO card and 0–20 MHz for an MMC card. In high-speed mode, the clock freqency value can be 0–33.25 MHz for an SD/SDIO card and 0–52 MHz for an MMC card. 3. To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. 4. CCARD  10 pF, (1 card), and CL = CBUS + CHOST + CCARD 40 pF Figure 30 provides the eSDHC clock input timing diagram. eSDHC External Clock operational mode VM VM VM tSHSCKL tSHSCK VM = Midpoint Voltage (OVDD/2) tSHSCKR tSHSCKF tSHSCKH Figure 30. eSDHC Clock Input Timing Diagram Figure 31 provides the data and command input/output timing diagram. SD_CK External Clock VM VM tSHSIVKH SD_DAT/CMD Inputs VM tSHSIXKH VM SD_DAT/CMD Outputs tSHSKHOV VM = Midpoint Voltage (OVDD/2) Figure 31. eSDHC Data and Command Input/Output Timing Diagram Referenced to Clock MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 41 FlexCAN 15 FlexCAN This section describes the DC and AC electrical specifications for the FlexCAN interface. 15.1 FlexCAN DC Electrical Characteristics Table 41. FlexCAN DC Electrical Characteristics (3.3V) Table 41 provides the DC electrical characteristics for the FlexCAN interface. For recommended operating conditions, see Table 2 Parameter Input high voltage Input low voltage Input current (OVIN = 0 V or OVIN = OVDD) Output high voltage (OVDD = min, IOH = –2 mA) Output low voltage (OVDD = min, IOL = 2 mA) Symbol VIH VIL IIN VOH VOL Min 2 — — 2.4 — Max — 0.8 ±5 — 0.4 Unit V V A V V Notes 1 1 2 — — Note: 1. Min VILand max VIH values are based on the respective min and max OVIN values found in Table 2. 2. OVIN represents the input voltage of the supply. It is referenced in Table 2. 15.2 FlexCAN AC Timing Specifications Table 42. FlexCAN AC Timing Specifications Table 42 provides the AC timing specifications for the FlexCAN interface. For recommended operating conditions, see Table 2 Parameter Baud rate Min 10 Max 1000 Unit Kbps Notes — MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 42 Freescale Semiconductor I2 C 16 I2C This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8309. 16.1 I2C DC Electrical Characteristics Table 43. I2C DC Electrical Characteristics Table 43 provides the DC electrical characteristics for the I2C interface of the MPC8309. At recommended operating conditions with OVDD of 3.3 V ± 300mV. Parameter Input high voltage level Input low voltage level Low level output voltage Output fall time from VIH(min) to VIL(max) with a bus capacitance from 10 to 400 pF Pulse width of spikes which must be suppressed by the input filter Capacitance for each I/O pin Input current (0 V VIN OVDD) Symbol VIH VIL VOL tI2KLKV tI2KHKL CI IIN Min 0.7  OVDD –0.3 0 20 + 0.1  CB 0 — — Max OVDD + 0.3 0.3  OVDD 0.4 250 50 10 ±5 Unit V V V ns ns pF A Notes — — 1 2 3 — 4 Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. CB = capacitance of one bus line in pF. 3. Refer to the MPC8309 PowerQUICC II Pro Integrated Communications Processor Reference Manual for information on the digital filter used. 4. I/O pins obstructs the SDA and SCL lines if OVDD is switched off. 16.2 I2C AC Electrical Specifications Table 44. I2C AC Electrical Specifications Table 44 provides the AC timing parameters for the I2C interface of the MPC8309. All values refer to VIH (min) and VIL (max) levels (see Table 43). Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: I2C bus devices Symbol1 fI2C tI2CL tI2CH tI2SVKH tI2SXKL tI2DVKH tI2DXKL tI2CR Min 0 1.3 0.6 0.6 0.6 100 300 20 + 0.1 CB4 Max 400 — — — — — 0.93 300 Unit kHz s s s s ns s ns Rise time of both SDA and SCL signals MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 43 I2 C Table 44. I2C AC Electrical Specifications (continued) All values refer to VIH (min) and VIL (max) levels (see Table 43). Parameter Fall time of both SDA and SCL signals Setup time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) Symbol1 Min 20 + 0.1 CB4 0.6 1.3 0.1  OVDD 0.2  OVDD Max 300 — — — — Unit ns s s V V tI2CF tI2PVKH tI2KHDX VNL VNH Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. MPC8309 provides a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3. The maximum tI2DVKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. CB = capacitance of one bus line in pF. Figure 32 provides the AC test load for the I2C. Output Z0 = 50  RL = 50  OVDD/2 Figure 32. I2C AC Test Load Figure 33 shows the AC timing diagram for the I2C bus. SDA tI2CF tI2CL SCL tI2SXKL S tI2DXKL 2 tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF tI2CH Sr tI2SVKH tI2PVKH P S Figure 33. I C Bus AC Timing Diagram MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 44 Freescale Semiconductor Timers 17 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8309. 17.1 Timer DC Electrical Characteristics Table 45 provides the DC electrical characteristics for the MPC8309 timer pins, including TIN, TOUT, TGATE, and RTC_PIT_CLK. Table 45. Timer DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –6.0 mA IOL = 6.0 mA IOL = 3.2 mA — — 0 V  VIN  OVDD Min 2.4 — — 2.0 –0.3 — Max — 0.5 0.4 OVDD + 0.3 0.8 ±5 Unit V V V V V A 17.2 Timer AC Timing Specifications Table 46. Timer Input AC Timing Specifications1 Characteristic Symbol2 tTIWID Min 20 Unit ns Table 46 provides the timer input and output AC timing specifications. Timers inputs—minimum pulse width Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN. Timings are measured at the pin. 2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by any external synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation. Figure 34 provides the AC test load for the timers. Output Z0 = 50  RL = 50  OVDD/2 Figure 34. Timers AC Test Load MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 45 GPIO 18 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8309. 18.1 GPIO DC Electrical Characteristics Table 47. GPIO DC Electrical Characteristics Characteristic Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –6.0 mA IOL = 6.0 mA IOL = 3.2 mA — — 0 V VIN OVDD Min 2.4 — — 2.0 –0.3 — Max — 0.5 0.4 OVDD + 0.3 0.8 ±5 Unit V V V V V A Notes 1 1 1 1 — — Table 11 provides the DC electrical characteristics for the MPC8309 GPIO. Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Note: 1. This specification applies when operating from 3.3-V supply. 18.2 GPIO AC Timing Specifications Table 48. GPIO Input AC Timing Specifications1 Characteristic Symbol2 tPIWID Min 20 Unit ns Table 48 provides the GPIO input and output AC timing specifications. GPIO inputs—minimum pulse width Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN. Timings are measured at the pin. 2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation. Figure 35 provides the AC test load for the GPIO. Output Z0 = 50  RL = 50  OVDD/2 Figure 35. GPIO AC Test Load MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 46 Freescale Semiconductor IPIC 19 IPIC This section describes the DC and AC electrical specifications for the external interrupt pins of the MPC8309. 19.1 IPIC DC Electrical Characteristics Table 49. IPIC DC Electrical Characteristics1,2 Characteristic Symbol VIH VIL IIN VOH VOL VOL Condition — — — IOL = -8.0 mA IOL = 6.0 mA IOL = 3.2 mA Min 2.0 –0.3 — 2.4 — — Max OVDD + 0.3 0.8 ±5 — 0.5 0.4 Unit V V A V V V Table 49 provides the DC electrical characteristics for the external interrupt pins of the MPC8309. Input high voltage Input low voltage Input current Output High Voltage Output low voltage Output low voltage Notes: 1. This table applies for pins IRQ, MCP_OUT, and QE ports Interrupts. 2. MCP_OUT is open drain pins, thus VOH is not relevant for those pins. 19.2 IPIC AC Timing Specifications Table 50. IPIC Input AC Timing Specifications1 Characteristic Symbol2 tPIWID Min 20 Unit ns Table 50 provides the IPIC input and output AC timing specifications. IPIC inputs—minimum pulse width Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLK_IN. Timings are measured at the pin. 2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working in edge triggered mode. 20 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8309. 20.1 SPI DC Electrical Characteristics Table 51 provides the DC electrical characteristics for the MPC8309 SPI. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 47 SPI Table 51. SPI DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Symbol VOH VOL VOL VIH VIL IIN Condition IOH = –6.0 mA IOL = 6.0 mA IOL = 3.2 mA — — 0 V  VIN  OVDD Min 2.4 — — 2.0 –0.3 — Max — 0.5 0.4 OVDD + 0.3 0.8 ±5 Unit V V V V V A 20.2 SPI AC Timing Specifications Table 52. SPI AC Timing Specifications1 Characteristic Symbol2 tNIKHOV tNEKHOV tNIIVKH tNIIXKH tNEIVKH tNEIXKH Min 0.5 2 6 0 4 2 Max 6 8 — — — — Unit ns ns ns ns ns ns Table 52 and provide the SPI input and output AC timing specifications. SPI outputs—Master mode (internal clock) delay SPI outputs—Slave mode (external clock) delay SPI inputs—Master mode (internal clock) input setup time SPI inputs—Master mode (internal clock) input hold time SPI inputs—Slave mode (external clock) input setup time SPI inputs—Slave mode (external clock) input hold time Notes: 1. Output specifications are measured from the 50% level of the rising edge of SPICLK to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid (V). 3. All units of output delay must be enabled for 8309_output_port spimosi_lpgl0(SPI Master Mode) 4. delay units must not be enabled for Slave Mode. Figure 36 provides the AC test load for the SPI. Output Z0 = 50  RL = 50  OVDD/2 Figure 36. SPI AC Test Load Figure 37 and Figure 38 represent the AC timing from Table 52. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 48 Freescale Semiconductor JTAG Figure 37 shows the SPI timing in slave mode (external clock). SPICLK (Input) tNEIVKH tNEIXKH Input Signals: SPIMOSI (See Note) Output Signals: SPIMISO (See Note) tNEKHOV Note: The clock edge is selectable on SPI. Figure 37. SPI AC Timing in Slave Mode (External Clock) Diagram Figure 38 shows the SPI timing in master mode (internal clock). SPICLK (Output) tNIIVKH tNIIXKH Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note) tNIKHOV Note: The clock edge is selectable on SPI. Figure 38. SPI AC Timing in Master Mode (Internal Clock) Diagram 21 JTAG This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1™ (JTAG) interface of the MPC8309. 21.1 JTAG DC Electrical Characteristics Table 53 provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the MPC8309. Table 53. JTAG Interface DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Symbol VOH VOL VOL Condition IOH = –6.0 mA IOL = 6.0 mA IOL = 3.2 mA Min 2.4 — — Max — 0.5 0.4 Unit V V V MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 49 JTAG Table 53. JTAG Interface DC Electrical Characteristics (continued) Characteristic Input high voltage Input low voltage Input current Symbol VIH VIL IIN Condition — — 0 V  VIN  OVDD Min 2.0 –0.3 — Max OVDD + 0.3 0.8 ±5 Unit V V A 21.2 JTAG AC Electrical Characteristics This section describes the AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the MPC8309. Table 54 provides the JTAG AC timing specifications as defined in Figure 40 through Figure 43. Table 54. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)1 At recommended operating conditions (see Table 2). Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data TMS, TDI Input hold times: Boundary-scan data TMS, TDI Valid times: Boundary-scan data TDO Symbol2 fJTG t JTG tJTKHKL tJTGR, tJTGF tTRST tJTDVKH tJTIVKH tJTDXKH tJTIXKH tJTKLDV tJTKLOV Min 0 30 11 0 25 4 4 10 10 2 2 Max 33.3 — — 2 — — — Unit MHz ns ns ns ns ns Notes — — — — 3 4 ns — — ns 15 15 5 4 MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 50 Freescale Semiconductor JTAG Table 54. JTAG AC Timing Specifications (Independent of SYS_CLK_IN)1 (continued) At recommended operating conditions (see Table 2). Parameter Output hold times: Boundary-scan data TDO JTAG external clock to output high impedance: Boundary-scan data TDO Symbol2 tJTKLDX tJTKLOX tJTKLDZ tJTKLOZ Min 2 2 2 2 Max — — Unit ns Notes 5 ns 19 9 5, 6 6 Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-load (see Figure 39). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect to tTCLK. 5. Non-JTAG signal output timing with respect to tTCLK. 6. Guaranteed by design and characterization. Figure 39 provides the AC test load for TDO and the boundary-scan outputs of the MPC8309. Output Z0 = 50  RL = 50  OVDD/2 Figure 39. AC Test Load for the JTAG Interface Figure 40 provides the JTAG clock input timing diagram. JTAG External Clock VM tJTKHKL tJTG VM = Midpoint Voltage (OVDD/2) VM VM tJTGR tJTGF Figure 40. JTAG Clock Input Timing Diagram Figure 41 provides the TRST timing diagram. TRST VM tTRST VM = Midpoint Voltage (OVDD/2) VM Figure 41. TRST Timing Diagram MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 51 JTAG Figure 42 provides the boundary-scan timing diagram. JTAG External Clock VM tJTDVKH tJTDXKH Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM Figure 42. Boundary-Scan Timing Diagram Figure 43 provides the test access port timing diagram. JTAG External Clock VM tJTIVKH tJTIXKH TDI, TMS tJTKLOV tJTKLOX TDO tJTKLOZ TDO Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM Figure 43. Test Access Port Timing Diagram MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 52 Freescale Semiconductor Package and Pin Listings 22 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8309 is available in a thermally enhanced MAPBGA (mold array process-ball grid array); see Section 22.1, “Package Parameters for the MPC8309,” and Section 22.2, “Mechanical Dimensions of the MPC8309 MAPBGA,” for information on the MAPBGA. 22.1 Package Parameters for the MPC8309 The package parameters are as provided in the following list. Package outline 19 mm 19 mm Package Type MAPBGA Interconnects 489 Pitch 0.80 mm Module height (typical) 1.48 mm; Min = 1.31mm and Max 1.61mm Solder Balls 96 Sn / 3.5 Ag / 0.5 Cu (VM package) Ball diameter (typical) 0.40 mm 22.2 Mechanical Dimensions of the MPC8309 MAPBGA Figure 44 shows the mechanical dimensions and bottom surface nomenclature of the MPC8309, 489-MAPBGA package. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 53 Package and Pin Listings Figure 44. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8309 MAPBGA Notes: 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 54 Freescale Semiconductor Package and Pin Listings 22.3 Pinout Listings Following table shows the pin list of the MPC8309. Table 55. MPC8309 Pinout Listing Signal Terminal Pad Dir Power Supply Notes DDR Memory Controller Interface MEMC_MDQ0 MEMC_MDQ1 MEMC_MDQ2 MEMC_MDQ3 MEMC_MDQ4 MEMC_MDQ5 MEMC_MDQ6 MEMC_MDQ7 MEMC_MDQ8 MEMC_MDQ9 MEMC_MDQ10 MEMC_MDQ11 MEMC_MDQ12 MEMC_MDQ13 MEMC_MDQ14 MEMC_MDQ15 MEMC_MDQ16 MEMC_MDQ17 MEMC_MDQ18 MEMC_MDQ19 MEMC_MDQ20 MEMC_MDQ21 MEMC_MDQ22 MEMC_MDQ23 MEMC_MDQ24 MEMC_MDQ25 MEMC_MDQ26 MEMC_MDQ27 MEMC_MDQ28 U5 AA1 W3 R5 W2 U3 U2 T3 H3 H4 G3 F3 G5 F4 F5 E3 V4 Y2 Y1 U4 V1 R4 U1 T2 J5 G2 G1 F1 E2 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD - MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 55 Package and Pin Listings MEMC_MDQ29 MEMC_MDQ30 MEMC_MDQ31 MEMC_MECC0 MEMC_MECC1 MEMC_MECC2 MEMC_MECC3 MEMC_MECC4 MEMC_MECC5 MEMC_MECC6 MEMC_MECC7 MEMC_MDM0 MEMC_MDM1 MEMC_MDM2 MEMC_MDM3 MEMC_MDM8 MEMC_MDQS0 MEMC_MDQS1 MEMC_MDQS2 MEMC_MDQS3 MEMC_MDQS8 MEMC_MBA0 MEMC_MBA1 MEMC_MBA2 MEMC_MA0 MEMC_MA1 MEMC_MA2 MEMC_MA3 MEMC_MA4 MEMC_MA5 MEMC_MA6 MEMC_MA7 MEMC_MA8 MEMC_MA9 MEMC_MA10 MEMC_MA11 MEMC_MA12 D2 C2 C1 Y5 AA4 Y4 AA3 AC2 AB2 Y3 AB1 W1 E1 V3 D1 W5 T5 H5 P5 E5 V5 K2 K3 N5 L3 L5 L2 L1 M3 M4 M1 N1 N2 N3 L4 P2 N4 IO IO IO IO IO IO IO IO IO IO IO O O O O O IO IO IO IO IO O O O O O O O O O O O O O O O O GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD - MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 56 Freescale Semiconductor Package and Pin Listings MEMC_MA13 MEMC_MWE_B MEMC_MRAS_B MEMC_MCAS_B MEMC_MCS_B0 MEMC_MCS_B1 MEMC_MCKE MEMC_MCK0 MEMC_MCK1 MEMC_MCK_B0 MEMC_MCK_B1 MEMC_MODT0 MEMC_MODT1 MEMC_MVREF P1 J1 K1 J3 J4 K5 P4 R1 R3 T1 P3 H1 H2 M6 Local Bus Controller Interface O O O O O O O O O O O O O GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD - LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LA16/ECID_TMODE_IN LA17 LA18 LA19 LA20 LA21 B5 A4 C7 D9 A5 E10 A6 C8 D10 A7 B7 C9 E11 B8 A8 C10 C11 B10 D12 A9 E12 B11 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO O O O O O OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD - MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 57 Package and Pin Listings LA22 LA23 LA24 LA25 LCLK0 A11 A10 C12 A12 E13 O O O O O OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD - LCS_B0 LCS_B1 LCS_B2 LCS_B3 LWE_B0/LFWE_B0/LBS_B0 LWE_B1/LBS_B1 LBCTL LGPL0/LFCLE LGPL1/LFALE LGPL2/LOE_B/LFRE_B LGPL3/LFWP_B LGPL4/LGTA_B/LUPWAIT/LFRB_B LGPL5 LALE D13 C13 A13 B13 A14 B14 A15 C14 C15 B16 A16 E14 B17 A17 DUART O O O O O O O O O O O IO O O 2 2 2 2 2 2 - UART1_SOUT1 UART1_SIN1 UART1_SOUT2/UART1_RTS_B1/ UART1_SIN2/UART1_CTS_B1/ AB7 AC6 W10 Y9 I2C O I O I OVDD OVDD OVDD OVDD - IIC_SDA1 IIC_SCL1 IIC_SDA2 /CKSTOP_OUT_B/ IIC_SCL2/CKSTOP_IN_B/ A20 B20 D19 C20 Interrupts IO IO IO IO OVDD OVDD OVDD OVDD 1 1 1 1 IRQ_B0_MCP_IN_B IRQ_B1/MCP_OUT_B/ IRQ_B2/CKSTOP_IN_B/ IRQ_B3/CKSTOP_OUT_B/INTA_B/ A21 A22 E18 E19 SPI IO IO I IO OVDD OVDD OVDD OVDD - SPIMOSI B19 IO OVDD - MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 58 Freescale Semiconductor Package and Pin Listings SPIMISO SPICLK SPISEL SPISEL_BOOT_B E16 E17 A19 D18 JTAG IO IO I OVDD OVDD OVDD OVDD - TCK TDI TDO TMS TRST_B A2 C5 A3 D7 E9 Test Interface I I O I I OVDD OVDD OVDD OVDD OVDD 2 2 2 TEST_MODE C6 System Control Signals I OVDD - HRESET_B PORESET_B W23 W22 Clock Interface IO I OVDD OVDD 1 - QE_CLK_IN SYS_CLK_IN SYS_XTAL_IN SYS_XTAL_OUT PCI_SYNC_IN PCI_SYNC_OUT CFG_CLKIN_DIV_B RTC_PIT_CLOCK R22 R23 P23 P19 T23 R20 U23 V23 Miscellaneous Signals I I I O I O I I OVDD OVDD OVDD OVDD OVDD OVDD OVDD - QUIESCE_B THERM0 D6 E8 GPIO O OVDD OVDD - GPIO_0/SD_CLK/MSRCID0 (DDR ID) GPIO_1/SD_CMD/MSRCID1 (DDR ID) GPIO_2/SD_CD/MSRCID2 (DDR ID) GPIO_3/SD_WP/MSRCID3 (DDR ID) GPIO_4/SD_DAT0/MSRCID4 (DDR ID) GPIO_5/SD_DAT1/MDVAL (DDR ID) GPIO_6/SD_DAT2/QE_EXT_REQ_3 GPIO_7/SD_DAT3/QE_EXT_REQ_1 GPIO_8/RXCAN1/LSRCID0/LCS_B4 E4 E6 D3 E7 D4 C4 B2 B3 C16 IO IO IO IO IO IO IO IO IO OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD - MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 59 Package and Pin Listings GPIO_9/TXCAN1/LSRCID1/LCS_B5 GPIO_10/RXCAN2/LSRCID2/LCS_B6 GPIO_11/TXCAN2/LSRCID3/LCS_B7 GPIO_12/RXCAN3/LSRCID4/LCLK1 GPIO_13/TXCAN3/LDVAL/ GPIO_14/RXCAN4 GPIO_15/TXCAN4 C17 E15 A18 D15 C18 D16 C19 USB IO IO IO IO IO IO IO OVDD OVDD OVDD OVDD OVDD OVDD OVDD - USBDR_PWRFAULT/CE_PIO_1/ USBDR_CLK/UART2_SIN2/UART2_CTS_B1/ USBDR_DIR/URM_TRIG/ USBDR_NXT/UART2_SIN1/UC1_URM/QE_EXT _REQ_4 USBDR_TXDRXD0/GPIO_32/QE_TRB_O USBDR_TXDRXD1/GPIO_33/QE_TRB_I USBDR_TXDRXD2/GPIO_34/QE_BRG_1 USBDR_TXDRXD3/GPIO_35/QE_BRG_2 USBDR_TXDRXD4/GPIO_36/QE_BRG_3 USBDR_TXDRXD5/GPIO_37/QE_BRG_4 USBDR_TXDRXD6/GPIO_38/QE_BRG_9 USBDR_TXDRXD7/GPIO_39/QE_BRG_11 USBDR_PCTL0/UART2_SOUT1/UC2_URM/LB_ POR_CFG_BOOT_ECC USBDR_PCTL1/UART2_SOUT2/UART2_RTS_B 1/LB_POR_BOOT_ERR USBDR_STP/UC3_URM/QE_EXT_REQ_2 AA6 AC9 AA7 AC5 I I I I OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 1 - Y6 W9 AB5 AA5 Y8 AC4 AC3 AB3 W8 IO IO IO IO IO IO IO IO O - W7 O - W6 PCI O - PCI_INTA_B PCI_RESET_OUT_B PCI_AD0/BOOT_ROM_ADDR[2] PCI_AD1/BOOT_ROM_ADDR[3] PCI_AD2/BOOT_ROM_ADDR[4] PCI_AD3/BOOT_ROM_ADDR[5] PCI_AD4/BOOT_ROM_ADDR[6] PCI_AD5/BOOT_ROM_ADDR[7] PCI_AD6/CE_PIO_0/BOOT_ROM_ADDR[8] PCI_AD7/BOOT_ROM_ADDR[9] B22 F19 B23 C21 E20 G19 C23 H19 D21 F20 O O IO IO IO IO IO IO IO IO OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD - MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 60 Freescale Semiconductor Package and Pin Listings PCI_AD8/BOOT_ROM_ADDR[10] PCI_AD9/BOOT_ROM_ADDR[11] PCI_AD10/BOOT_ROM_ADDR[12] PCI_AD11/BOOT_ROM_RDATA[0] PCI_AD12/BOOT_ROM_RDATA[1] PCI_AD13/BOOT_ROM_RDATA[2] PCI_AD14/BOOT_ROM_RDATA[3] PCI_AD15/BOOT_ROM_RDATA[4] PCI_AD16/BOOT_ROM_RDATA[5] PCI_AD17/BOOT_ROM_RDATA[6] PCI_AD18/BOOT_ROM_RDATA[7] PCI_AD19/BOOT_ROM_RDATA[8] PCI_AD20/BOOT_ROM_RDATA[9] PCI_AD21/BOOT_ROM_RDATA[10] PCI_AD22/BOOT_ROM_RDATA[11] PCI_AD23/BOOT_ROM_RDATA[12] PCI_AD24/BOOT_ROM_RDATA[13] PCI_AD25/BOOT_ROM_RDATA[14] PCI_AD26/UC5_URM/BOOT_ROM_RDATA[15] PCI_AD27BOOT_ROM_RDATA[16] PCI_AD28/UC7_URM/BOOT_ROM_RDATA[17] PCI_AD29/BOOT_ROM_RDATA[18] PCI_AD30/BOOT_ROM_RDATA[19] PCI_AD31/BOOT_ROM_RDATA[20] PCI_C_BE_B0 / BOOT_ROM_RDATA[21] PCI_C_BE_B1 / BOOT_ROM_RDATA[22] PCI_C_BE_B2 / BOOT_ROM_RDATA[23] PCI_C_BE_B3 / /BOOT_ROM_RDATA[24] PCI_PAR/BOOT_ROM_RDATA[25] PCI_FRAME_B / BOOT_ROM_RDATA[26] PCI_TRDY_B / BOOT_ROM_RDATA[27] PCI_IRDY_B / BOOT_ROM_RDATA[28] PCI_STOP_B / BOOT_ROM_RDATA[29] PCI_DEVSEL_B / BOOT_ROM_RDATA[30] PCI_IDSEL / BOOT_ROM_RDATA[31] PCI_SERR_B / BOOT_ROM_MOD_EN PCI_PERR_B / BOOT_ROM_RWB E21 H20 D22 D23 J19 F21 G21 E22 E23 J20 F23 G23 K19 H21 L19 G22 H23 J21 H22 J23 K18 K21 K22 K23 L20 L23 L22 L21 M19 M20 M23 M21 N23 N22 N21 N19 P20 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD - MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 61 Package and Pin Listings PCI_REQ_B0 / BOOT_ROM_XFR_WAIT PCI_REQ_B1/CPCI_HS_ES/BOOT_ROM_XFR_ ERR PCI_REQ_B2 PCI_GNT_B0 PCI_GNT_B1/CPCI_HS_LED/ PCI_GNT_B2/CPCI_HS_ENUM/ M66EN PCI_CLK0 PCI_CLK1 PCI_CLK2 P21 P22 IO IO OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD - T22 T21 U22 U21 V21 T19 U19 R19 Ethernet Management IO IO O IO I O O O - FEC_MDC FEC_MDIO W18 W17 FEC/GTM/GPIO O IO OVDD OVDD - FEC1_COL/GTM1_TIN1/GPIO_16/ FEC1_CRS/GTM1_TGATE1_B/GPIO_17/ FEC1_RX_CLK[CLK9]/GPIO_18/ FEC1_RX_DV/GTM1_TIN2/GPIO_19/PLLCZ_C ORE_CLKIN FEC1_RX_ER/GTM1_TGATE2_B/GPIO_20/JTA G_BISE FEC1_RXD0/GPIO_21/JTAG_PRPGPS FEC1_RXD1/GTM1_TIN3/GPIO_22/JTAG_BISR _TDO_EN FEC1_RXD2/GTM1_TGATE3_B/GPIO_23/TPR_ SYS_AAD[0] FEC1_RXD3/GPIO_24/TPR_SYS_AAD[1] FEC1_TX_CLK[CLK10]/GTM1_TIN4/GPIO_25/T PR_SYS_AAD[2] FEC1_TX_EN/GTM1_TGATE4_B/GPIO_26/TPR _SYS_AAD[3] FEC1_TX_ER/GTM1_TOUT4_B/GPIO_27/TPR_ SYS_AAD[4] FEC1_TXD0/GTM1_TOUT1_B/GPIO_28/TPR_S YS_AAD[5] FEC1_TXD1/GTM1_TOUT2_B/GPIO_29/TPR_S YS_AAD[6] FEC1_TXD2/GTM1_TOUT3_B/GPIO_30/TPR_S YS_AAD[7] Y18 AA19 W16 AC22 AA18 AB20 Y17 AB19 AC21 W15 AC19 AC20 AA17 AC18 IO IO IO IO IO IO IO IO IO IO IO IO IO IO OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD - AA16 IO - MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 62 Freescale Semiconductor Package and Pin Listings FEC1_TXD3/GPIO_31/TPR_SYS_AAD[8] FEC2_COL/GTM2_TIN1/GPIO_32/TPR_SYS_A AD[9] FEC2_CRS/GTM2_TGATE1_B/GPIO_33/TPR_S YS_AAD[10] FEC2_RX_CLK[CLK7]/GPIO_34/TPR_SYS_AAD [11] FEC2_RX_DV/GTM2_TIN2/GPIO_35/TPR_SYS _AAD[12] FEC2_RX_ER/GTM2_TGATE2_B/GPIO_36/TPR _SYS_AAD[13] FEC2_RXD0/GPIO_37/TPR_SYS_AAD[14] FEC2_RXD1/GTM2_TIN3/GPIO_38/TPR_SYS_ AAD[15] FEC2_RXD2/GTM2_TGATE3_B/GPIO_39/TPR_ SYS_SYNC FEC2_RXD3/GPIO_40/TPR_SYS_DACK FEC2_TX_CLK[CLK8]/GTM2_TIN4/GPIO_41/ FEC2_TX_EN/GTM2_TGATE4_B/GPIO_42/CLO CK_XLB_CLOCK_OUT FEC2_TX_ER/GTM2_TOUT4_B/GPIO_43/ FEC2_TXD0/GTM2_TOUT1_B/GPIO_44/PD_XL B2MG_DDR_CLOCK FEC2_TXD1/GTM2_TOUT2_B/GPIO_45/ FEC2_TXD2/GTM2_TOUT3_B/GPIO_46/ FEC2_TXD3/GPIO_47/ FEC3_COL/GPIO_48/ FEC3_CRS/GPIO_49/ FEC3_RX_CLK[CLK11]/GPIO_50/ FEC3_RX_DV/FEC1_TMR_TX_ESFD/GPIO_51/ FEC3_RX_ER/FEC1_TMR_RX_ESFD/GPIO_52/ FEC3_RXD0/FEC3_TMR_TX_ESFD/GPIO_53/ FEC3_RXD1/FEC3_TMR_RX_ESFD/GPIO_54/ FEC3_RXD2/TSEC_TMR_TRIG1/GPIO_55/ FEC3_RXD3/TSEC_TMR_TRIG2/GPIO_56/ FEC3_TX_CLK[CLK12]/TSEC_TMR_CLK/GPIO _57/ FEC3_TX_EN/TSEC_TMR_GCLK/GPIO_58/ AB17 Y15 IO IO OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD - AC17 IO - W14 IO - AB16 IO - Y14 IO - AA15 AC15 IO IO - AC16 IO - AA14 W13 AB14 IO IO IO - AC14 Y12 IO IO - AA13 AB13 AC13 AC12 W11 W12 AA12 AB11 AA11 AC11 Y11 AB10 AC10 IO IO IO IO IO IO IO IO IO IO IO IO IO - AA10 IO - MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 63 Package and Pin Listings FEC3_TX_ER/TSEC_TMR_PP1/GPIO_59/ FEC3_TXD0/TSEC_TMR_PP2/GPIO_60/ FEC3_TXD1/TSEC_TMR_PP3/GPIO_61/ FEC3_TXD2/TSEC_TMR_ALARM1/GPIO_62/ FEC3_TXD3/TSEC_TMR_ALARM2/GPIO_63/ AC8 AB8 AA9 AA8 AC7 HDLC/TDM/GPIO IO IO IO IO IO OVDD OVDD OVDD OVDD OVDD - HDLC1_TXCLK[CLK16]/GPIO_0/QE_BRG_5/TD M1_TCK[CLK4] HDLC1_RXCLK[CLK15]/GPIO_1/TDM1_RCK [CLK3]/ HDLC1_TXD/GPIO_2/TDM1_TD/CFG_RESET_ SOURCE[0] HDLC1_RXD/GPIO_3/TDM1_RD/ HDLC1_CD_B/GPIO_4/TDM1_TFS/ HDLC1_CTS_B/GPIO_5/TDM1_RFS/ HDLC1_RTS_B/GPIO_6/TDM1_STROBE_B/CF G_RESET_SOURCE[1] HDLC2_TXCLK[CLK13]/GPIO_16/QE_BRG_7/T DM2_TCK[CLK6] HDLC2_RXCLK[CLK14]/GPIO_17/TDM2_RCK [CLK5]/QE_BRG_8 HDLC2_TXD/GPIO_18/TDM2_TD/CFG_RESET _SOURCE[2] HDLC2_RXD/GPIO_19/TDM2_RD/ HDLC2_CD_B/GPIO_20/TDM2_TFS/ HDLC2_CTS_B/GPIO_21/TDM2_RFS/ HDLC2_RTS_B/GPIO_22/TDM2_STROBE_B/C FG_RESET_SOURCE[3] AA20 AA21 AB22 AB23 W19 V19 AA23 IO IO IO IO IO IO IO OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 1 - Y20 IO - Y22 IO - W20 IO 1 W21 V20 Y23 U20 Power IO IO IO IO - AVDD1 AVDD2 AVDD3 GVDD L16 M16 N8 F6, G6, H6, J6, K6, L6, N6, P6, R6, T6, U6, V6, V7 - - - MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 64 Freescale Semiconductor Package and Pin Listings NVDD F7, F8, F9, F10, F11, F12, F13,F14, F15, F16, F17, F18, G18,H18, J18, L18, M18, N18, P18,R18, T18, U18, V8, V9, V10, V11, V12, V13, V14, V15, V16, V17, V18 H8,H9,H10,H11,H12,M8, H13,N16,H14,H15,H16, P16,P8,L8,K16,J16,K8,J 8,R8,T16,R16,T8,T9,T11 ,T10,T12,T13,T14,T15 - - - VDD - - - VSS A1, C3, F22, J14, K14, M15, L15, N20, R9, Y21, T20, AB21, B1, C22,G4, K15, J15, M2, M22, P9, R10, V2, AA2, AC1, B4,D5, G20, J22, K20, M5, N9, P10, R11, V22, AA22,AC23, B6, D8, J2, K4, M9,L9, N10, P11, R12, W4, AB4, D11, B9, J9, K9, L10,M10, N11, P12, R13, Y7,AB6, B12, D14, J10, K10, L11, M11, P13, N12, R14, Y10,AB9, B15, D17, J11, K11, D20, B18, J12, K12, L13, L12, L14, K13, J13, F2, B21, M14, M13, M12, Y19, Y16, AB15, AB12, Y13, N13, N14, N15, P14, P15, R2, AB18, R15, R21, T4 A23 - - - NC - - - Notes 1. This pin is an open drain signal. A weak pull-up resistor should be placed on this pin to OVDD 2 This pin has weak pull-up that is always enabled. 4. OVDD here refers to NVDDA, NVDDB,NVDDC, NVDDF, NVDDG, and NVDDH from the ball map. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 65 Clocking 23 Clocking Figure 45 shows the internal distribution of clocks within the MPC8309. Figure 45. MPC8309 Clock Subsystem MPC8309 Rest of the System /n e300c3 core Core PLL core_clk csb_clk to DDR memory controller DDR Clock Divider /2 ddr_clk Clock Unit System PLL SYS_XTAL_OUT CRYSTAL SYS_XTAL_IN SYS_CLK_IN csb_clk to rest of the device MEMC_MCK MEMC_MCK DDR Memory Device lbc_clk /n to local bus LBC Clock Divider LCLK[0:1] Local Bus Memory Device PCI_SYNC_IN PCI_SYNC_OUT PCI Clock Divider CFG_CLKIN_DIV PCI_CLK[0:2] QE_CLK_IN QE PLL CLK Gen qe_clk QE Block The primary clock source for the MPC8309 can be one of three inputs,Crystal(SYS_XTAL_IN ), SYS_CLK_IN or PCI_SYNC_IN, depending on whether the device is configured in PCI host or PCI agent mode, respectively. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 66 Freescale Semiconductor Clocking 23.1 Clocking in PCI Host Mode When the MPC8309 is configured as a PCI host device (RCWH[PCIHOST] = 1), SYS_CLK_IN is its primary input clock. SYS_CLK_IN feeds the PCI clock divider (2) and the PCI_SYNC_OUT and PCI_CLK multiplexors. The CFG_CLKIN_DIV configuration input selects whether SYS_CLK_IN or SYS_CLK_IN/2 is driven out on the PCI_SYNC_OUT signal. PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the system. 23.1.1 PCI Clock Outputs (PCI_CLK[0:2]) When the MPC8309 is configured as a PCI host, it provides three separate clock output signals, PCI_CLK[0:2], for external PCI agents. When the device comes out of reset, the PCI clock outputs are disabled and are actively driven to a steady low state. Each of the individual clock outputs can be enabled (enable toggling of the clock) by setting its corresponding OCCR[PCICOEn] bit. All output clocks are phase-aligned to each other. 23.2 Clocking in PCI Agent Mode When the MPC8309 is configured as a PCI agent device, PCI_SYNC_IN is the primary input clock. In agent mode, the SYS_CLK_IN signal should be tied to GND, and the clock output signals, PCI_CLKn and PCI_SYNC_OUT, are not used. 23.3 System Clock Domains As shown in Figure 45, the primary clock input (frequency) is multiplied up by the system phase-locked loop (PLL) and the clock unit to create four major clock domains: • The coherent system bus clock (csb_clk) • The QUICC Engine clock (qe_clk) • The internal clock for the DDR controller (ddr_clk) • The internal clock for the local bus controller (lbc_clk) The csb_clk frequency is derived from the following equation: csb_clk = [PCI_SYNC_IN × (1 + ~CFG_CLKIN_DIV)] × SPMF In PCI host mode, PCI_SYNC_IN = SYS_CLK_IN (1 + ~CFG_CLKIN_DIV) . Eqn. 2 Eqn. 1 The csb_clk serves as the clock input to the e300 core. A second PLL inside the core multiplies up the csb_clk frequency to create the internal clock for the core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL) which is loaded at power-on reset or by one of the hard-coded reset options.For more information, see the Reset MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 67 Clocking Configuration chapter in the MPC8309 PowerQUICC II Pro Communications Processor Reference Manual. The qe_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF]) and the QUICC Engine PLL division factor (RCWL[CEPDF]) as the following equation: qe_clk = (QE_CLK_IN × CEPMF)  (1 + CEPDF) Eqn. 3 For more information, see the QUICC Engine PLL Multiplication Factor section and the “QUICC Engine PLL Division Factor” section in the MPC8309 PowerQUICC II Pro Communications Processor Reference Manual for more information. The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk. Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the same frequency as ddr_clk. The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCCR[CLKDIV]. For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8309 PowerQUICC II Pro Communications Processor Reference Manual. In addition, some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. Table 56 specifies which units have a configurable clock frequency. For detailed description, refer to the “System Clock Control Register (SCCR)” section in the MPC8309 PowerQUICC II Pro Communications Processor Reference Manual. Table 56. Configurable Clock Units Unit I2C,SDHC, USB, DMA Complex Default Frequency csb_clk Options Off, csb_clk, csb_clk/2, csb_clk/3 NOTE Setting the clock ratio of these units must be performed prior to any access to them. Table 57 provides the maximum operating frequencies for the MPC8309 MAPBGA under recommended operating conditions (see Table 2). Table 57. Operating Frequencies for MAPBGA Characteristic1 e300 core frequency (core_clk) Coherent system bus frequency (csb_clk) Max Operating Frequency 417 167 Unit MHz MHz MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 68 Freescale Semiconductor Clocking Table 57. Operating Frequencies for MAPBGA (continued) Characteristic1 QUICC Engine frequency (qe_clk) DDR2 memory bus frequency (MCLK) Local bus frequency 1 2 Max Operating Frequency 233 167 66 Unit MHz MHz MHz (LCLKn)3 The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk, MCLK, LCLK, and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. 2 The DDR2 data rate is 2× the DDR2 memory bus frequency. 3 The local bus frequency is 1/2, 1/4, or 1/8 of the lb_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1× or 2× the csb_clk frequency (depending on RCWL[LBCM]). 23.4 System PLL Configuration The system PLL is controlled by the RCWL[SPMF] parameter. Table 58 shows the multiplication factor encodings for the system PLL. NOTE System PLL VCO frequency = 2 × (CSB frequency) × (System PLL VCO divider). The VCO divider needs to be set properly so that the System PLL VCO frequency is in the range of 450–750 MHz. Table 58. System PLL Multiplication Factors RCWL[SPMF] 0000 0001 0010 0011 0100 0101 0110 0111–1111 System PLL Multiplication Factor Reserved Reserved ×2 ×3 ×4 ×5 ×6 Reserved As described in Section 23, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal coherent system bus clock (csb_clk). Table 59 shows the expected frequency values for the CSB frequency for selected csb_clk to SYS_CLK_IN ratios. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 69 Clocking Table 59. CSB Frequency Options PCI_SYNC_IN(MHz) SPMF csb_clk : sys_clk_in Ratio 25 33.33 csb_clk Frequency (MHz) 0010 0011 0100 0101 0110 2:1 3:1 4:1 5:1 6:1 125 133 167 133 66.67 23.5 Core PLL Configuration RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 60 shows the encodings for RCWL[COREPLL]. COREPLL values not listed in Table 60 should be considered reserved. Table 60. e300 Core PLL Configuration RCWL[COREPLL] core_clk : csb_clk Ratio 0-1 nn 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 0000 0001 0001 0001 0001 0001 0001 0001 0001 0010 0010 0010 0010 0010 0010 0010 0010 0011 2-5 6 n 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 PLL bypassed (PLL off, csb_clk clocks core directly) 1:1 1:1 1:1 1:1 1.5:1 1.5:1 1.5:1 1.5:1 2:1 2:1 2:1 2:1 2.5:1 2.5:1 2.5:1 2.5:1 3:1 PLL bypassed (PLL off, csb_clk clocks core directly) 2 4 8 8 2 4 8 8 2 4 8 8 2 4 8 8 2 VCO Divider MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 70 Freescale Semiconductor Clocking Table 60. e300 Core PLL Configuration (continued) RCWL[COREPLL] core_clk : csb_clk Ratio 0-1 01 10 11 0011 0011 0011 2-5 6 0 0 0 3:1 3:1 3:1 4 8 8 VCO Divider NOTE Core VCO frequency = core frequency  VCO divider. The VCO divider (RCWL[COREPLL[0:1]]), must be set properly so that the core VCO frequency is in the range of 400–800 MHz. 23.6 QUICC Engine PLL Configuration The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. Table 61 shows the multiplication factor encodings for the QUICC Engine PLL. Table 61. QUICC Engine PLL Multiplication Factors RCWL[CEPMF] 00000–00001 00010 00011 00100 00101 00110 00111 01000 01001–11111 RCWL[CEPDF] 0 0 0 0 0 0 0 0 0 QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/ (1 + RCWL[CEPDF) Reserved 2 3 4 5 6 7 8 Reserved The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in Table 62. Table 62. QUICC Engine PLL VCO Divider RCWL[CEVCOD] 00 01 10 11 VCO Divider 2 4 8 Reserved MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 71 Clocking NOTE The VCO divider (RCWL[CEVCOD]) must be set properly so that the QUICC Engine VCO frequency is in the range of 300–600 MHz. The QUICC Engine frequency is not restricted by the CSB and core frequencies. The CSB, core, and QUICC Engine frequencies should be selected according to the performance requirements. The QUICC Engine VCO frequency is derived from the following equations: qe_clk = (primary clock input × CEPMF)  (1 + CEPDF) QUICC Engine VCO Frequency = qe_clk × VCO divider × (1 + CEPDF) 23.7 Suggested PLL Configurations To simplify the PLL configurations, the MPC8309 might be separated into two clock domains. The first domain contains the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock domains are independent, and each of their PLLs are configured separately. Table 63 shows suggested PLL configurations for 33 and 66 MHz input clocks. Table 63. Suggested PLL Configurations Core PLL 0000100 0000101 0000100 0000101 0000101 0000101 0000110 0000110 0000110 0000101 Input Clock Frequency (MHz) 33.33 25 66.67 33.33 25 66.67 33.33 25 66.67 33.33 CSB Frequency (MHz) 133.33 100 133.33 133.33 125 133.33 133.33 125 133.33 166.67 Core Frequency (MHz) 266.66 250 266.66 333.33 312.5 333.33 399.96 375 399.96 416.67 QUICC Engine Frequency (MHz) 200 200 200 200 200 200 200 200 200 233 Conf No. SPMF CEPMF CEDF 1 2 3 4 5 6 7 8 9 10 0100 0100 0010 0100 0101 0010 0100 0101 0010 0101 0110 1000 0011 0110 1000 0011 0110 1000 0011 0111 0 0 0 0 0 0 0 0 0 0 MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 72 Freescale Semiconductor Thermal 24 Thermal This section describes the thermal specifications of the MPC8309. 24.1 Thermal Characteristics Table 64 provides the package thermal characteristics for the 369, 19  19 mm MAPBGA of the MPC8309. Table 64. Package Thermal Characteristics for MAPBGA Characteristic Junction-to-ambient natural convection Junction-to-ambient natural convection Junction-to-ambient (@200 ft/min) Junction-to-ambient (@200 ft/min) Junction-to-board Junction-to-case Junction-to-package top Board type Single-layer board (1s) Four-layer board (2s2p) Single-layer board (1s) Four-layer board (2s2p) — — Natural convection Symbol RJA RJA RJMA RJMA RJB RJC JT Value 40 25 33 22 15 9 2 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W Notes 1, 2 1, 2 ,3 1, 3 1, 3 4 5 6 Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 24.1.1 Thermal Management Information For the following sections, PD = (VDD  IDD) + PI/O, where PI/O is the power dissipation of the I/O drivers. 24.1.2 Estimation of Junction Temperature with Junction-to-Ambient Thermal Resistance TJ = TA + (RJA  PD) An estimation of the chip junction temperature, TJ, can be obtained from the equation: Eqn. 1 where: TJ = junction temperature (C) MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 73 Thermal TA = ambient temperature for the package (C) RJA = junction-to-ambient thermal resistance (C/W) PD = power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. As a general statement, the value obtained on a single layer board is appropriate for a tightly packed printed-circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity TJ – TA) are possible. 24.1.3 Estimation of Junction Temperature with Junction-to-Board Thermal Resistance The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: TJ = TB + (RJB  PD) Eqn. 2 where: TJ = junction temperature (C) TB = board temperature at the package perimeter (C) RJB = junction-to-board thermal resistance (C/W) per JESD51-8 PD = power dissipation in package (W) When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. 24.1.4 Experimental Determination of Junction Temperature To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT  PD) Eqn. 3 where: TJ = junction temperature (C) MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 74 Freescale Semiconductor Thermal TT = thermocouple temperature on top of package (C) JT = thermal characterization parameter (C/W) PD = power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 24.1.5 Heat Sinks and Junction-to-Case Thermal Resistance In some application environments, a heat sink is required to provide the necessary thermal management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case to ambient thermal resistance as shown in the following equation: RJA = RJC + RCA Eqn. 4 where: RJA = junction-to-ambient thermal resistance (C/W) RJC = junction-to-case thermal resistance (C/W) RCA = case-to-ambient thermal resistance (C/W) RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed-circuit board, or change the thermal dissipation on the printed-circuit board surrounding the device. To illustrate the thermal performance of the devices with heat sinks, the thermal performance has been simulated with a few commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling and the convection cooling of the air moving through the application. Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request. 24.2 Heat Sink Attachment When attaching heat sinks to these devices, an interface material is required. The best method is to use thermal grease and a spring clip. The spring clip should connect to the printed-circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 75 System Design Information lifetime of the package. Recommended maximum force on the top of the package is 10 lb (4.5 kg) force. If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic surfaces and its performance verified under the application requirements. 24.2.1 Experimental Determination of the Junction Temperature with a Heat Sink When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance using the following equation: TJ = TC + (RJC  PD) Eqn. 5 where: TC = case temperature of the package (C) RJC = junction-to-case thermal resistance (C/W) PD = power dissipation (W) 25 System Design Information This section provides electrical and thermal design recommendations for successful application of the MPC8309. 25.1 System Clocking The MPC8309 includes three PLLs. • The system PLL (AVDD2) generates the system clock from the externally supplied SYS_CLK_IN input. The frequency ratio between the system and SYS_CLK_IN is selected using the system PLL ratio configuration bits as described in Section 23.4, “System PLL Configuration.” • The e300 core PLL (AVDD3) generates the core clock as a slave to the system clock. The frequency ratio between the e300 core clock and the system clock is selected using the e300 PLL ratio configuration bits as described in Section 23.5, “Core PLL Configuration.” • The QUICC Engine PLL (AVDD1) which uses the same reference as the system PLL. The QUICC Engine block generates or uses external sources for all required serial interface clocks. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 76 Freescale Semiconductor System Design Information 25.2 PLL Power Supply Filtering Each of the PLLs listed above is provided with power through independent power supply pins. The voltage level at each AVDDn pin should always be equivalent to VDD, and preferably these voltages are derived directly from VDD through a low frequency filter scheme such as the following. There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent filter circuits as illustrated in Figure 46, one to each of the three AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of package, without the inductance of vias. Figure 46 shows the PLL power supply filter circuit. VDD 10 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors (