HMC900LP5E

HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Features low Noise Figure: 12 dB High linearity: Output IP3 +30 dBm Pre-programmed and/or Programmable Bandwidth: 3.5 MHz to 50 MHz. (Please see “HMC900lP5e Ordering Information”) Integrated aDC Driver amplifier exceptional 3 dB Bandwidth accuracy: ±2.5% 6th order Butterworth Magnitude & Phase Response automatic Filter Calibration externally Controlled Common Mode Output level simplifies Interface Filter Bypass Option: 100 MHz Bandwidth Read/Write serial Port Interface (sPI) 32 lead 5x5 mm sMT Package 25 mm2 Typical Applications The HMC900lP5e is ideal for various modulation systems: • Baseband filtering before a/D or after D/a converters for point-to-point fixed wireless or base station transceivers (gsM/gPRs, WCDMa & TD-sCDMa) • Integrated direct conversion receiver (DCR) when mated with mixer and Vga • software defined radio applications • anti-aliasing and reconstruction filters • Test and measurement equipment 3 IF / BaseBaND sIgNal PROCessINg Functional Diagram General Description The HMC900lP5e is a 6th order, programmable bandwidth, fully calibrated, dual low pass filter. It features 0 or 10 dB input gain setting and supports arbitrary bandwidths from 3.5 MHz to 50 MHz, and when calibrated, is accurate to +/-2.5% of the desired bandwidth. It includes a 100 MHz bandwidth filter bypass option while retaining gain setting and common mode control. Housed in a compact 5x5 mm sMT QFN package, the HMC900lP5e requires minimal external components and provides a low cost alternative to more complicated switched discrete filter architectures. The integrated aDC driver and externally controlled common mode output level further simplify system implementations. Filter calibration for the HMC900lP5e is accomplished with any reference clock rate from 20 to 80 MHz. One time programmable (OTP) memory offers unsurpassed flexibility allowing the user “set and forget” parameters like gain and bandwidth setting. Matched filter paths provide excellent quadrature balance, making the HMC900lP5e ideal for I/Q communications applications. The 6th order Butterworth transfer function delivers superior stop band rejection while maintaining both a flat passband and minimal group delay variation. 3-1 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Table 1. Electrical Specifications Ta = +25°C, VDDI, VDDQ, VDDCal, VDDBg, DVDD = 5V +/-5%, gND = 0V, 400 Ω load unless otherwise stated. Parameter Analog Performance Passband gain [1] 3dB corner frequency (fc) Programmable to any frequency in this range 3dB corner frequency variation 3dB corner frequency variation vs temperature Max passband gain error[2] Max passband group delay variation (group delay * 3dB frequency fc ) e.g. for 1.0 dB BW of 40 MHz (fc ~ 44.9 MHz): max group delay variation = 0.400/ 44.9 MHz = 8.9 ns min gain setting max gain setting [1] Conditions Min. Typ. Max. Units 0 10 3.5 75 100 ± 20 ±2.5 ± 3.5 ±0.03 ±0.5 0.250 0.350 0.400 0.400 22 22 25 25 8 8 8 8 25 17 19 12 50 dB dB MHz MHz % % % / °C dB Bypass mode uncalibrated calibrated over -40°C to +85°C vs ideal 6th order lPF H(s) at 0.1dB BW (~0.73 fc) at 0.5dB BW (~0.83 fc) at 1.0dB BW (~ 0.89 fc) at 3.0dB BW (at fc) min gain, fc = 3.5 MHz min gain, fc = 28 MHz max gain fc = 3.5 MHz max gain, fc = 28 MHz min gain, fc = 3.5 MHz max gain, fc = 3.5 MHz min gain fc = 28 MHz max gain, fc = 28 MHz min gain max gain min gain max gain half scale tones at 0.8fc and 0.6fc fc = 20 MHz fc = 50 MHz[2] half scale tones at 1.2fc and 1.6fc. IM3 product at 0.8fc fc = 20 MHz fc = 50 MHz [2] half scale tones at 2fc and 3fc. IM3 product at 0.5fc fc = 20 MHz fc = 50 MHz [2] half scale tones at 0.8fc and 0.6fc fc = 20 MHz fc = 50 MHz half scale tones at 1.2fc and 1.6fc. IM3 product at 0.8fc fc = 20 MHz fc = 50 MHz [2] half scale tones at 2fc and 3fc. IM3 product at fc fc = 20 MHz fc = 50 MHz[2] half scale tones at 0.8fc and 0.6fc IM2 product at 0.2fc fc = 20 MHz fc = 50 MHz [2] 3 nV/rtHz nV/rtHz nV/rtHz nV/rtHz nV/rtHz nV/rtHz nV/rtHz nV/rtHz dB dB dB dB Output Noise (f = 1 MHz) Output noise (f > 10*fc) Noise Figure (100 Ω source) Noise Figure (1 kΩ source) Input referred Passband IM3 -60 -50 dBc dBc Input referred Out of Band IM3 -60 -50 dBc dBc Input referred Out of Band IM3 -50 -45 dBc dBc Output IP3 (inband) 25 17 30 20 dBm dBm Output IP3 (out of band) 25 17 30 20 dBm dBm Output IP3 (out of band) 25 17 30 20 dBm dBm Output IP2 (inband) 55 55 60 60 dBm dBm For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com 3-2 IF / BaseBaND sIgNal PROCessINg HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Table 1. Electrical Specifications, TA = +25°C (Continued) Parameter Output IP2 (out of band)[2] sideband suppression (Uncalibrated) I/Q Channel Balance magnitude phase I/Q Channel Isolation Analog I/O Differential Input Impedance Full scale Differential Input (400 Ω Differential load) min gain max gain min gain max gain 1 400 Ω Differential load 100 Ω Differential load 0.5 Vdd/2-1 Use doubler mode for clocks between 20 MHz and 40 MHz Vdd/2 1000 2 0.613 0.5 0.156 4 2 0.5 Vdd-0.5 Vdd/2+1 Ω Vppd Vppd Vppd Vppd V Vppd Vppd V V 60 Conditions half scale tones at 1.2fc and 1.6fc. IM2 product at 0.4fc complex signal measured at 0.8fc vs -0.8fc Min. 60 40 Typ. 65 45 Max. Units dBm dB dB o 0.04 0.5 80 dB 3 IF / BaseBaND sIgNal PROCessINg Full scale Differential Input (100 Ω Differential load) Input Common Mode Voltage Range Full scale Differential Output Full scale Differential Output Output Voltage Range Output Common Mode Voltage Range Digital I/O CalCK Frequency CalCK Duty Cycle sClK Frequency Digital Input low level (VIl) Digital Input High level (VIH) Digital Output low level (VOl) Digital Output High level (VOH) Power supply supply Current Power on Reset 20 40 40 50 20 80 60 30 0.4 MHz % MHz V V 1.5 0.4 Vdd - 0.4 analog & Digital supplies 4.75 5 130 250 5.25 V V ma us [1] The attenuation of the filter transfer function can be calculated directly at any frequency f as: attenuation = 10*log10(1+(f/f0)^(2*6)), where f0 is the 3dB bandwidth or corner frequency for the filter. similarly, for a given maximum attenuation and 3dB bandwidth, f0, the frequency at which the attenuation is achieved can be calculated as: f=(10 ^(attenuation/10) -1)^ (1/(2*6)) * f0. Note that for a 6th order Butterworth filter the 1dB bandwidth is at ~89% of the filter bandwidth and 0.5dB bandwidth is at 84% of the filter bandwidth. [2] specified distortion is measured with in “high linearity” mode with opamp_bias[1:2]=2 and drvr_bias[1:0] = 2. see Reg 02h. Table 2. Test Conditions Unless otherwise specified, the following test conditions were used Parameter Temperature Filter Bandwidth setting gain setting bias settings (opamp_bias[1:0]/ drvr_bias[1:0]) Input signal level Input/Output Common Mode level Output load supply Condition +25 °C 20 MHz 0 dB 01/10 2 Vppd 2.5V 200Ω / Output analog: +5V, Digital +5V 3-3 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Figure 2. Filter Noise Figure vs Bandwidth[1] 26 24 Figure 1. Filter Attenuation (all Bandwidths) 0 -20 3.5 MHz FILTER GAIN (dB) 0 dB Gain -40 Bypass 3.5MHz 5MHz 7MHz 10MHz 14MHz 20MHz 28MHz 35MHz 50MHz 1 FREQUENCY (MHz) NOISE FIGURE (dB) 22 20 -60 +27C +85C -40C 10 dB Gain 50 MHz 18 -80 16 -100 0.1 14 10 100 3.5 5 7 10 14 20 28 35 50 FILTER BANDWIDTH (MHz) 3 50 MHz 0.3 100 0.2 0.1 FILTER GAIN (dB) 0 -0.1 -0.2 -0.3 -0.4 -0.5 1 3.5 MHz 3.5MHz 7MHz 5MHz 10MHz 14MHz 20MHz 28MHz 35MHz 50MHz 50 MHz 3.5MHz 5MHz 7MHz 10MHz 14MHz 20MHz 28MHz 35MHz 50MHz 10 3.5 MHz 10 FREQUENCY (MHz) 100 0.001 0.01 0.1 1 FREQUENCY (MHz) 10 100 Figure 5. Filter 3 dB Cutoff vs Temperature, 10 MHz Bandwidth 5 +27C +85C -40C FILTER GAIN (dB) 0 Figure 6. Filter Side Band Rejection vs Bandwidth 55 SIDEBAND REJECTION (dBc) 0dB 10dB 50 -3dB -5 45 -10 5 6 7 8 9 10 20 40 3.5 5 7 10 14 20 28 35 50 FREQUENCY (MHz) FILTER BANDWIDTH (MHz) [1] Measured with 100 Ω source impedance For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com 3-4 IF / BaseBaND sIgNal PROCessINg Figure 3. Filter Passband Gain Response Figure 4. Filter Output Noise OUTPUT NOISE (nV/rtHz) HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Figure 8. In-band OIP3 [1] and OIP2 [1] vs Temperature, 0 dB Gain (high linearity) 45 OUTPUT IP2 75 40 OUTPUT IP3 (dBm) 70 Figure 7. In-band OIP3 [1] & OIP2 [1] vs Temperature, 0 dB Gain (standard bias) 45 OUTPUT IP2 40 OUTPUT IP3 (dBm) 70 OUTPUT IP2 (dBm) 75 35 65 35 OUTPUT IP2 (dBm) 65 30 OUTPUT IP3 60 30 OUTPUT IP3 60 25 55 25 55 20 -40C -40C +27C 85C +85C 27C 3.5 5 7 10 14 20 28 FILTER BANDWIDTH (MHz) 35 50 50 20 -40C -40C +27C 85C +85C 27C 5 7 10 14 20 28 35 50 50 15 45 15 3.5 45 FILTER BANDWIDTH (MHz) 3 IF / BaseBaND sIgNal PROCessINg Figure 9. In-band OIP3 [1] and OIP2 [1] vs Bandwidth (standard bias) 45 70 40 OUTPUT IP2 60 65 Figure 10. In-band OIP3 [1] and OIP2 [1] vs Bandwidth (high linearity) 45 70 40 OUTPUT IP2 60 65 OUTPUT IP3 (dBm) 35 OUTPUT IP3 (dBm) 35 OUTPUT IP2 (dBm) OUTPUT IP2 (dBm) 30 OUTPUT IP3 25 55 30 OUTPUT IP3 25 55 50 0dB 0dB 10dB 10dB 50 20 45 20 0dB 10dB 10dB 5 7 10 14 20 28 35 50 45 15 3.5 40 5 7 10 14 20 28 35 50 FILTER BANDWIDTH (MHz) 15 3.5 40 FILTER BANDWIDTH (MHz) Figure 11. Out-of-band OIP3 [1] and OIP2 [1] vs Bandwidth (standard bias) 50 45 40 OUTPUT IP2 (dBm) 70 35 30 25 20 15 3.5 0dB 10dB 10dB 60 OUTPUT IP2 80 Figure 12. Out-of-band OIP3 [1] and OIP2 [1] vs Bandwidth (high linearity) 55 50 OUTPUT IP2 45 75 OUTPUT IP2 (dBm) 70 65 60 55 50 45 5 7 10 14 20 28 35 50 FILTER BANDWIDTH (MHz) 85 80 OUTPUT IP3 (dBm) OUTPUT IP3 (dBm) 40 35 30 25 OUTPUT IP3 50 OUTPUT IP3 20 0dB 0dB 10dB 10dB 40 5 7 10 14 20 28 35 50 FILTER BANDWIDTH (MHz) 15 3.5 [1] OIP3 and OIP2 measured into 400 Ω differential load. OIP3 and OIP2 can be translated from dBm into dBVrms as follows: IPx [dBVrms] = IPx [dBm] -4 dB 3-5 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Figure 14. 50 MHz Filter Magnitude and Group Delay 2 NORMALIZED GROUP DELAY (ns) 20 NORMALIZED GROUP DELAY (ns) 0 Gain 10 15 Figure 13. 3.5 MHz Filter Magnitude and Group Delay 5 Gain 0 50 100 -2 GAIN (dB) GAIN (dB) -5 Group Delay -10 0 -4 5 -6 0 -50 -8 Group Delay -5 -15 0.1 1 FREQUENCY (MHz) -100 10 -10 1 10 FREQUENCY (MHz) -10 100 100 40 20 fundamental level 50 Vout (dBVrms) fundamental level Vout (dBVrms) 0 -20 -40 -60 -80 0 Measuring Instrument -50 Noise Floor extrapolated OIP2 = 94 dBV extrapolated OIP3 = 30 dBV -100 second productl level -100 third productl level -150 -20 0 20 40 Vin (dBVrms/tone) 60 80 100 -120 -20 -10 0 10 20 30 Vin (dBVrms/tone) Figure 17. Filter I/Q Channel Isolation 0 3.5MHz 5MHz 7MHz 10MHz 14MHz 20MHz 28MHz 35MHz 50MHz -20 I/Q FILTER ISOLATION (dBc) -40 -60 -80 -100 1 10 FREQUENCY (MHz) [1] 14 MHz Coarse BW, Op-amp bias 01 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com 3-6 IF / BaseBaND sIgNal PROCessINg Figure 15. HMC900LP5E OIP2 at 10 MHz & 10.1 MHz [1] Figure 16. HMC900LP5E OIP3 at 10 MHz & 10.1 MHz [1] 3 HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Table 3. Absolute Maximum Ratings Nominal 5V supply to gND VDDCal, VDDI, VDDQ, VDDBg, DVDD Common Mode Inputs Pins (CMI, CMQ) Input and Output Pins IIP, IIN, IQP, IQN, OIP, OIN, OQP, OQN Digital Pins seN, sDI, sCK, sDO, CalCK sDO min load impedance Operating Temperature Range -0.3 to 5.5V Reflow soldering Peak Temperature Time at Peak Temperature esD sensitivity (HBM) 260 °C 40 µs 1kV Class 1C -0.3 to 5.5V -0.3 to 5.5V -0.3 to 5.5V 1kΩ -40 to +85 °C -65 to +125 °C 125 °C 10 °C/W stresses above those listed under absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3 IF / BaseBaND sIgNal PROCessINg storage Temperature Maximum Junction Temperature Thermal Resistance (RTH) (junction to ground paddle) eleCTROsTaTIC seNsITIVe DeVICe OBseRVe HaNDlINg PReCaUTIONs Outline Drawing NOTes: [1] PaCKage BODY MaTeRIal: lOW sTRess INJeCTION MOlDeD PlasTIC sIlICa aND sIlICON IMPRegNaTeD. [2] leaD aND gROUND PaDDle MaTeRIal: COPPeR allOY. [3] leaD aND gROUND PaDDle PlaTINg: 100% MaTTe TIN. [4] DIMeNsIONs aRe IN INCHes [MIllIMeTeRs]. [5] leaD sPaCINg TOleRaNCe Is NON-CUMUlaTIVe. [6] PaD BURR leNgTH sHall Be 0.15mm MaX. PaD BURR HeIgHT sHall Be 0.25m MaX. [7] PaCKage WaRP sHall NOT eXCeeD 0.05mm [8] all gROUND leaDs aND gROUND PaDDle MUsT Be sOlDeReD TO PCB RF gOUND. [9] ReFeR TO HITTITe aPPlICaTION NOTe FOR sUggesTeD PCB laND PaTTeRN. Table 4. Package Information Part Number HMC900lP5e Package Body Material RoHs-compliant low stress Injection Molded Plastic lead Finish 100% matte sn Msl Rating [1] Msl1 Package Marking [2] H900 XXXX [1] Max peak reflow temperature of 260 °C [2] 4-Digit lot number XXXX 3-7 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Table 5. Pin Descriptions Pin Number 1, 3, 8 - 10, 17, 24, 25, 32 2, 4 Function N/C Description The pins are not connected internally; however, all data shown herein was measured with these pins connected to RF/DC ground externally. Quadrature (Q) Channel 5V supply. Must be locally decoupled to gND Interface schematic VDDQ 5 CMQ Quadrature (Q) channel output common mode level 6, 7 OQP, OQN Quadrature (Q) channel positive and negative differential outputs 3 IF / BaseBaND sIgNal PROCessINg 3-8 11 CalCK Calibration clock input 12, 14, 15 sClK, sDI, seN sPI Data clock, data input and enable respectively. 13 sDO sPI Data Output 16 DVDD Digital 5V supply. Must be locally decoupled to gND. 18, 19 OIN, OIP Inphase (I) channel negative and positive differential outputs respectively For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Table 5. Pin Descriptions (Continued) Pin Number Function Description Interface schematic 20 CMI Inphase (I) channel output common mode level 21, 23 22 VDDi VDDCal Inphase (I) Channel 5V supply. Must be locally decoupled to gND Calibration 5V supply. Must be locally decoupled to gND 3 IF / BaseBaND sIgNal PROCessINg 26, 27 IIP, IIN Inphase (I) channel positive and negative differential inputs respectively 28 VDDBg Bias 5V supply. Must be locally decoupled to gND. 29 VBg 1.2V Bandgap output (testing only) 30, 31 IQN, IQP Quadrature (Q) channel negative and positive differential inputs respectively 3-9 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Evaluation PCB 3 IF / BaseBaND sIgNal PROCessINg 3 - 10 The circuit board used in the application should use RF circuit design techniques. signal lines should have 50 Ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. a sufficient number of via holes should be used to connect the top and bottom ground planes. The evaluation circuit board shown is available from Hittite upon request. Table 6. Evaluation Order Information Item evaluation PCB Only Contents HMC900lP5e evaluation PCB HMC900lP5e evaluation PCB UsB Interface Board 6’ UsB a Male to UsB B Female Cable CD ROM (Contains User Manual, evaluation PCB schematic, evaluation software) Part Number 131200-HMC900lP5e evaluation Kit 130521-HMC900lP5e For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Evaluation PCB Schematic To view evaluation PCB schematic please visit w ww.hittite.com and choose HMC900lP5e from the “search by Part Number” pull down menu to view the product splash page. Evaluation Setup 3 IF / BaseBaND sIgNal PROCessINg Figure 18. Characterization Setup Block Diagram 3 - 11 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER HMC900LP5E Usage Information The HMC900lP5e addresses different filter applications such as fixed frequency or variable bandwidth implementations dependent on the part selected (see “HMC900lP5e Ordering Information”) and the control provided to the HMC900lP5e. These modes provide the user with different filter options depending on the system implementation. an overview of these trade-offs are shown below. Table 7. HMC900LP5E Modes of Operation Function Fixed Bandwidth Filter Default Bandwidth and gain setting after Power On Reset (POR) Typical Corner Frequency accuracy at Default Bandwidth Variable Bandwidth Filter Default Bandwidth and gain setting after Power On Reset (POR) Typical Corner Frequency accuracy at Default Bandwidth Typical Corner Frequency accuracy at all other Bandwidths Unprogrammed HMC900LP5E-00000 Pre-programmed HMC900LP5E-BBBGL SPI Req’d CALCK Req’d Comments Yes Default Bandwidth and gain as defined by register defaults. (3.5 MHz /0dB gain) +/- 20 % Yes Default Bandwidth and gain as defined by register defaults. (3.5 MHz /0dB gain) +/- 20 % Yes Bandwidth and gain as defined by pre-programming at factory. +/- 2.5 % Yes Bandwidth and gain as defined by pre-programming at factory. +/- 2.5 % Yes No Pre-programmed gain and bandwidth are defined when ordering the part. see “HMC900lP5e Ordering Information”. accuracy is with respect to bandwidth after POR. Full control over HMC900lP5e requires access via the digital serial port (sPI). Pre-programmed gain and bandwidth are defined when ordering the part. see “HMC900lP5e Ordering Information”. accuracy is with respect to bandwidth after POR. accuracy is with respect to the desired bandwidth. see “Filter Bandwidth setting” for information regarding changing the bandwidth after when calibration is not possible. Full control over HMC900lP5e requires access via the digital serial port (sPI). Filter calibration requires valid calibration clock (via CalCK pin). see “RC Calibration Circuit” Pre-programmed gain and bandwidth are defined when ordering the part. see “HMC900lP5e Ordering Information”. accuracy is with respect to bandwidth after POR. accuracy is with respect to calibrated bandwidth. User Calibration requires access to the HMC900lP5e via the digital serial port (sPI) and requires a valid calibration clock (via CalCK pin). accuracy is with respect to the desired bandwidth. User Calibration requires access to the HMC900lP5e via the digital serial port (sPI) and requires a valid calibration clock (via pin CalCK). see “Filter Bandwidth setting” for information regarding changing the bandwidth after calibration when further calibration is not possible. No No 3 IF / BaseBaND sIgNal PROCessINg 3 - 12 +/- 20 % +/- 5.0 % Variable Bandwidth Filter (with ability to execute User Calibration to calibrate filter bandwidth) Default Bandwidth and gain setting after Power On Reset (POR) Typical Corner Frequency accuracy after POR (before User Calibration) Yes Yes Default Bandwidth and gain as defined by register defaults. (3.5 MHz /0dB gain) +/- 20 % Bandwidth and gain as defined by pre-programming at factory. +/- 2.5 % Typical Corner Frequency accuracy after User Calibration at calibrated bandwidth Yes +/- 2.5 % +/- 2.5 % Yes Typical Corner Frequency accuracy after User Calibration at non calibrated bandwidths +/- 5.0 % +/- 5.0 % For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER HMC900LP5E Application Information The HMC900lP5e provides an attractive alternative to other discrete filter solutions due to it’s unmatched flexibility in supporting a wide range of bandwidths in today’s complex multi-carrier systems and multi-standard systems. Typical architectures supporting multiple bandwidths have required either large board real estate or compromised filter selection which come at the expense of price or performance. The HMC900lP5e overcomes this limitation by allowing the system designer to optimize the bandwidth for the required signal. The HMC900lP5e overcomes the matching problem that discrete filters present with respect to baseband signal processing. The matched dual filter paths provide excellent gain and phase balance between the two channels eliminating the image problem which results from poor matching. The HMC900lP5e provides selectable gain and a flexible output driver further increase system integration and reduce board area. 3 IF / BaseBaND sIgNal PROCessINg Figure 19. Typical Receive Path Block Diagram showing HMC900LP5E Figure 20. Typical Transmit Path Block Diagram 3 - 13 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER HMC900LP5E Ordering Information The HMC900lP5e is available as product that is either un-programmed or pre-programmed. Programming is available to a variety of filter bandwidths (defined in this context as the 3dB bandwidth). Other options available for pre-programmed product include the single path gain and bias state as described below. gain and bias settings are described in Reg 02h. When placing an order for the HMC900lP5e please observe the following guidelines. 1. 2. To order the un-programmed standard part please place order using the part number HMC900lP5e-00000. To order a pre-programmed HMC900lP5e please determine the part number as described below and then contact Hittite sales at sales@hittite.com or call (978) 250-3343. 2.1 Minimum quantity order for the pre-programmed HMC900lP5e-BBBgl is 500 pieces. 3. Pre-Programmed part number description: HMC900lP5e-BBBgl. 3.1 ‘BBB’ represents a three digit number from the following table that represents the desired bandwidth setting (3 dB bandwidth) from 3.5 MHz to 50 MHz (for example BBB = 035 specifies a 3.5 MHz corner frequency). 3.2 ‘g’ represents the gain setting of either 0 dB (g = 0) or 10 dB (g = 1). 3.3 ‘l’ represents the linearity setting of either standard (l = 0) or high linearity (l = 1). Note that the high linearity setting is recommended only for bandwidth settings above 30 MHz.[1] For example, to order the HMC900lP5e pre-programmed for 50 MHz 3 dB frequency, 10 dB gain, and standard linearity setting please specify part number HMC900lP5e-50010. 3 IF / BaseBaND sIgNal PROCessINg 3 - 14 Table 8. Custom Part Frequency Options BBB frequency for custom part (actual frequency is BBB x 0.1 MHz) 035 036 037 038 039 040 041 042 043 044 045 046 047 048 049 050 052 053 054 056 057 058 060 061 063 064 066 068 069 070 071 073 075 076 078 080 082 084 086 088 091 093 095 098 100 102 105 108 110 113 116 119 121 124 128 131 134 137 140 141 144 148 151 155 159 163 167 171 175 179 180 184 188 193 198 203 208 213 218 224 229 235 240 246 253 259 265 272 278 280 285 292 300 307 315 322 330 338 347 355 364 373 382 392 400 401 411 422 432 443 454 465 476 488 500 [1] The Output IP2 and Output IP3 for the two linearity settings are shown in Figure 8 and Figure 9. High linearity setting improves linearity for bandwidths greater than 30 MHz at the cost of increased current consumption (additional 25 ma). For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Theory of Operation The HMC900lP5e consists of the following functional blocks 1. Input gain stage 2. 6th Order lPF 3. Output Driver 4. RC Calibration Circuit 5. Bias Circuit 6. One Time Programmable Memory 7. serial Port interface 8. Built in self Test (RC-BIsT) Input Gain Stage 3 IF / BaseBaND sIgNal PROCessINg The HMC900lP5e input stage consists of a programmable 0 or 10 dB gain stage which in turn drives the 6th order lPF. a block diagram showing input impedance of the I channel is presented below, Q channel is similar. Figure 21. Input Stage Block Diagram 6th Order Low Pass Filter (LPF) The lPF allows for coarse bandwidth tuning by varying the capacitive elements in the filter, while the fine bandwidth tuning is accomplished by varying the resistors. Note that all opamps in the lPF are class aB for minimum power consumption in the filter while maintaining excellent distortion characteristics even in large signal swing conditions. The attenuation due to the lPF can be calculated for any frequency, f, from the standard Butterworth transfer function for a 6th order filter. specifically the attenuation of the filter, in dB, can be calculated as: attenuation = 10*log10(1+(f/fc)^ (2*6)) where fc is the 3 dB bandwidth or corner frequency for the filter. Note that for a 6th order Butterworth filter the 1 dB bandwidth is 90% of fc, and the 0.3 dB bandwidth is 80% of fc. 3 - 15 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Filter Bandwidth Setting The 3 dB bandwidth of the HMC900lP5e is programmable anywhere within the range from 3.5 to 50 MHz. This is accomplished via a two step process which involves 1) running calibration, and 2) programming the appropriate coarse and fine bandwidth codes. Once the settings for a given device are found, they can be stored permanently in the non volatile memory (see “One Time Programmable Memory (OTP)”.) To program the bandwidth of the HMC900lP5e to a desired bandwidth, fwanted, the procedure is as follows: 1. Run a calibration routine. Run a filter calibration cycle to determine the particular calibration code for the device under test (see “RC Calibration Circuit”.) Once complete, the actual calibration measurement must be read from the sPI (see Reg 09h.) 2. Calculate the desired coarse bandwidth and fine bandwidth codes. a. From the calibration result we define a coarse tune factor, ctune as: ctune=Cal_count/10370000 b. Normalize the desired frequency fBW_norm_coarse = fwanted * ctune c. lookup the coarse tune code based on fBW_norm_coarse from Table 9. 3 IF / BaseBaND sIgNal PROCessINg 3 - 16 Table 9. Normalized Bandwidth Look up Table fBW_norm_coarse coarse_bandwidth_code[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 min (MHz) 2.764 3.948 5.527 7.896 11.055 15.792 22.109 27.637 39.480 typ (MHz) 3.500 5.000 7.000 10.000 14.000 20.000 28.000 35.000 50.000 max (MHz) 4.235 6.050 8.470 12.100 16.940 24.200 33.880 42.351 60.500 d. Calculate the fine tuning factor, fine_tune_ratio, for bandwidth based on the typical value of the coarse bandwidth center frequency, fBW_norm_coarse_typ fine_tune_ratio = fBW_norm_coarse / fBW_norm_coarse_typ e. lookup the fine tune code based on fine_tune_ratio from Table 10: For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Table 10. Calibration Code Look up Table fine_tune_ratio fine_bandwidth_code [3:0] 0000 0001 0010 0011 0100 0101 0110 min (MHz/MHz) 0.790 0.818 0.846 0.878 0.909 0.943 0.976 1.012 10.48 1.087 1.128 1.169 typ (MHz/MHz) 0.803 0.832 0.862 0.893 0.926 0.959 0.994 1.030 1.068 1.107 1.148 1.189 max (MHz/MHz) 0.818 0.846 0.878 0.909 0.943 0.976 1.012 1.048 1.087 1.128 1.169 1.210 3 IF / BaseBaND sIgNal PROCessINg 0111 1000 1001 1010 1011 3. Program the sPI for the given device with the coarse and fine bandwidth code, and instruct the device to use the provided instructions. a. Write coarse_bandwidth_code[3:0] to Reg 02h bits [9:6] b. Write fine_bandwidth_code[3:0] to Reg 03h bits [3:0] c. Instruct HMC900lP5e to use provided codes by setting Reg 01h bit 4. Filter Bandwidth Setting After Calibration after the initial filter calibration is completed as above the filter bandwidth can be changed to an arbitrary bandwidth by recalculating coarse_bandwidth_code[3:0] and fine_bandwidth_code[3:0] from the previously determined ctune. This results in the same coarse_bandwidth_code[3:0] and fine_bandwidth_code[3:0] as if the HMC900lP5e was recalibrated as described above. If ctune is unknown but the current desired frequency is known then the value of ctune needs to be estimated based on the values of coarse_bandwidth_code[3:0] and fine_bandwidth_code[3:0] and the corresponding nominal frequencies in Table 9 and Table 10. For example, if the 3 dB bandwidth for the HMC900lP5e was factory pre-programmed to a customer defined requirement of 34 MHz and coarse_bandwidth_code[3:0] and fine_bandwidth_code[3:0] are “0111” and “1001” respectively (as determined from Reg 0ah for a pre-programmed part or from Reg 02h for a non programmed part) then ctune can be estimated as follows: 1. lookup the nominal coarse bandwidth and fine bandwidth frequencies. a. From Table 9 the nominal coarse frequency is 35.0 MHz b. From Table 10 the nominal fine normalized frequency is 1.107 MHz/ MHz or simply 1.107 2. estimate ctune as: ctune=(35 MHz * 1.107 )/ 34 MHz = 1.13956 This value of ctune can now be used to calculate any arbritary filter frequency as described above. 3 - 17 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Output Driver The HMC900lP5e output driver consists of a differential class aB driver which is designed to drive typical aDC loads directly or can drive up to 200Ω in parallel with 50 pF to aC ground per differential output. Note that the output common mode of the driver is controlled directly via the CMI/CMQ pin and can be set as per “Table 1. electrical specifications”. also note, that driver loading does not impact filter transfer responses. The output common mode of the driver is controlled directly via the CMI/CMQ pin and can be set as per the “Table 1. electrical specifications”. a block diagram showing output connections is presented below. 3 IF / BaseBaND sIgNal PROCessINg 3 - 18 Figure 22. Output Driver Block Diagram RC Calibration Circuit The RC Calibration block uses a known user supplied clock to measure an on chip RC time constant. This measurement is representative of the uncorrected corner frequency error for a given bandwidth for the lPF. Calibration is normally done at room temperature Refer to “Table 1. electrical specifications” for further details on the variation of the 3dB cutoff point with temperature. With this information, the HMC900lP5e can correctly fine tune the lPF by adjusting the resistors in the lPF to center the corner frequency to the desired bandwidth. The calibration for the HMC900lP5e proceeds as follows: 1. 2. 3. the clock used for calibration is programmed between 20 MHz and 100 MHz via Reg 05h. also note that for clocks between 20 MHz and 40 MHz the doubler must be enabled via Reg 01h. the RC calibration circuit is enabled via Reg 01h. a calibration cycle is initialized by writing to Reg 04h. For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER When complete, the calibration value can be retrieved from Reg 08h and, if desired, the calibration results can be overridden via Reg 03h. Bias Circuit a band gap reference circuit generates the reference currents used by the different sections. The bias circuit is enabled or disabled as required with the I or Q channel as appropriate. One Time Programmable Memory (OTP) The HMC900lP5e features one time programmable memory which can be programmed by the end user or ordered from the factory precalibrated. The OTP memory is programmed via the standard 4 wire serial port (sPI) as follows: 3 IF / BaseBaND sIgNal PROCessINg 1. enable OTP write mode (see Reg 0Bh bit 0 enables OTP programming). 2. read the status of the OTP active flag (see Reg 08h, bit 5 is the OTP active flag). The Write Pulse status (OTP active flag) must be 0 to allow the OTP to be programmed. 3. write the OTP bit address to be set (Reg 0Ch). This address is a 4 bit number representing the address of the bit to be programmed. Note that when programming a bit we change its state from 0 to 1 and this operation cannot be reversed. OTP bit addresses can be found in Reg 08h. 4. start the OTP Write operation. Write any data to the OTP strobe register (Reg 0Dh). 5. read the status of the OTP active flag (Reg 08h, bit 5 is the OTP active flag). If bit 5 is set then the Write pulse is still high. Repeat until bit 5 is 0 which indicates that the write pulse is finished. 6. Repeat steps 3 to 5 to program the remaining desired bits. Note that bit 13 OTP_prg_flag must be set by the user to use OTP values. 7. When completed, disable OTP write mode (Reg 0Bh). Serial Port Interface The HMC900lP5e features a four wire serial port for simple communication with the host controller. Typical serial port operation can be run with sCK at speeds up to 30MHz. The details of sPI access for the HMC900lP5e is provided in the following sections. Note that the ReaD operation below is always preceded by a WRITe operation to Reg 0h to define the register to be queried. also note that every ReaD cycle is also a WRITe cycle in that data sent to the sPI while reading the data will also be stored by the HMC900lP5e when seN goes high. If this is not desired then it is suggested to write to Reg 0h during the ReaD operation as the status of the device will be unaffected. Power on Reset and Soft Reset The HMC900lP5e has a built in Power On Reset (POR) and also a serial port accessible soft Reset (sR). POR is accomplished when power is cycled for the HMC900lP5e while sR is accomplished via the sPI by writing 20h to Reg 0h followed by writing 00h to Reg 0h. all chip registers will be reset to default states approximately 250us after power up. Serial Port WRITE Operation The host changes the data on the falling edge of sCK and the HMC900lP5e reads the data on the rising edge. a typical WRITe cycle is shown in Figure 23. It is 32 clock cycles long. 1. The host both asserts seN (active low serial Port enable) and places the MsB of the data on sDI followed by a rising edge on sClK. For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com 3 - 19 HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER 2. HMC900lP5e reads sDI (the MsB) on the 1st rising edge of sCK after seN. 3. HMC900lP5e registers the data bits, D23:D0, in the next 23 rising edges of sClK (total of 24 data bits). 4. Host places the 5 register address bits, a4:a0, on the next 5 falling edges of sClK (MsB to lsB) while the HMC900lP5e reads the address bits on the corresponding rising edge of sCK. 5. Host places the 3 chip address bits, Ca2:Ca0=[101], on the next 3 falling edges of sCK (MsB to lsB). Note the HMC900lP5e chip address is fixed as “5d” or “101b”. 6. seN goes from low to high after the 32th rising edge of sCK. This completes the WRITe cycle. 7. HMC900lP5e also exports data back on the sDO line. For details see the section on ReaD operation. Serial Port READ Operation The sPI can read from the internal registers in the chip. The data is available on sDO line. This line itself is tri-stated when the device is not being addressed. However when the device is active and has been addressed by the sPI master, the HMC900lP5e controls the sDO line and exports data on this line during the next sPI cycle. HMC900lP5e changes the data to the host on the rising edge of sClK and the host reads the data from HMC900lP5e on the falling edge. a typical ReaD cycle is shown in Figure 23. Read cycle is 32 clock cycles long. To specifically read a register, the address of that register must be written to dedicated Reg 0h. This requires two full cycles, one to write the required address, and a 2nd to retrieve the data. a read cycle can then be initiated as follows; 1. The host asserts seN (active low serial Port enable) followed by a rising edge sClK. 2. HMC900lP5e reads sDI (the MsB) on the 1st rising edge of sCK after seN. 3. HMC900lP5e registers the data bits in the next 23 rising edges of sClK (total of 24 data bits). The LSBs of the data bits represent the address of the register that is intended to be read. 4. Host places the 5 register address bits on the next 5 falling edges of sClK (MsB to lsB) while the HMC900lP5e reads the address bits on the corresponding rising edge of sCK. For a read operation this is “00000”. 5. Host places the 3 chip address bits on the next 3 falling edges of sCK (MsB to lsB). Note the HMC900lP5e chip address is fixed as “5d” or “101b”. 6. seN goes from low to high after the 32th rising edge of sCK. This completes the first portion of the ReaD cycle. 7. The host asserts seN (active low serial Port enable) followed by a rising edge sClK. 8. HMC900lP5e places the 24 data bits, 5 address bits, and 3 chip id bits, on the sDO, on each rising edge of the sCK, commencing with the first rising edge beginning with MsB. 9. The host deasserts seN (i.e. sets seN high) after reading the 32 bits from the sDO output. The 32 bits consists of 24 data bits, 5 address bits, and the 3 chip id bits. Note that the data sent to the sPI during this portion of the ReaD operation is stored in the sPI when seN is deasserted. This can potentially change the state of the HMC900lP5e. If this is undesired it is recommended that during the second phase of the ReaD operation that Reg 0h is addressed with either the same address or the address of another register to be read during the next cycle. 10. This completes the ReaD cycle. 3 IF / BaseBaND sIgNal PROCessINg 3 - 20 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Serial Port Bus Operation with Multiple Devices The sPI bus architecture supports multiple HMC devices on the same sPI bus. each HMC900lP5e on the bus requires a dedicated seN line to enable the appropriate device. The sDO pin is normally driven by the HMC900lP5e during and after an sPI read/write which is addressed directly to the HMC900lP5e (chip address = 5d or ‘101’b). a write to the HMC900lP5e where chip address is set to any value other than 5d or ‘101’b is required in order to ensure that the sDO pin remains tri-stated after accessing the HMC900lP5e. such a write will not result in any change in the HMC900lP5e configuration because of the incorrect chip address. 3 IF / BaseBaND sIgNal PROCessINg Figure 23. SPI Timing Diagram Table 11. Main SPI Timing Characteristics DVDD = 5V ±5%, gND = 0V Parameter t1 t2 t3 t4 t5 t6 t7 t8 Conditions sDI to sCK setup Time sDI to sCK Hold Time sCK High Duration [a] sCK low Duration seN low Duration seN High Duration sCK to seN [b] Min 8 8 10 10 20 20 8 Typ Max Units nsec nsec nsec nsec nsec nsec nsec sCK to sDO Out[c] 8 nsec a. The sPI is relative insensitive to the duty cycle of sCK. b. seN must rise after the 32nd falling edge of sCK but before the next rising sCK edge. If sCK is shared amongst several devices this timing must be respected. c. Typical load to sDO 10pF, max 20pF 3 - 21 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Built In Self Test (RC-BIST) The HMC900lP5e RC Calibration state machine features built in self test (RC-BIsT) to facilitate improved device testing. The RC-BIsT can be exercised as follows: 1. apply reset to the chip via a power cycle (hard reset) or via the sPI (soft reset). soft reset is accomplished by writing 20h to Reg 0h followed by writing 00h to Reg 0h. 2. setup the RCCal input parameters if desired. Note that the RC-BIsT will work with the default settings from power up however test coverage will improve if the following sPI registers are also accessed: a. program the RC clock period (Reg 05h). b. program the measurement adjustment setting (Reg 06h). c. program the threshold adjustment settings. 3. enable BIsT mode (Reg 0eh). 4. start the BIsT by writing any data to the BIsT strobe register (Reg 04h). Note that the BIsT will take 2^ 18 ~ 260k clock cycles to complete. 5. read the result of the BIsT test. Read the value in the BIsT Out register (Reg 0F). Bit 16 is the busy flag and will be set when the BIsT is still running. When this bit is reset then the BIsT output value in bits 15:0 are valid. Note that the value of the BIsT output must be compared to the expected result depending on values programmed into the registers in step 2. The BIsT procedure can be repeated as desired to ensure adequate test coverage for the RC Calibration engine. The suggested register settings to maximize test coverage with BIsT is provided below. 3 IF / BaseBaND sIgNal PROCessINg 3 - 22 Table 12. Test Conditions Register Settings Reg 05h[14:0]=65, Reg 06h[8:0]=255, Reg10h[4:0] to eg1ah[4:0]=0d or 0h Reg 05h[14:0]=32702, Reg 06h[8:0]=36, Reg10h[4:0] to Reg1ah[4:0]=31d or 1Fh Reg 05h[14:0]=10922, Reg 06h[8:0]=170, Reg10h[4:0] to Reg1ah[4:0]=10d or ah Reg 05h[14:0]=21845, Reg06h[8:0]=853, Reg10h[4:0] to Reg1ah[4:0]=21d or 15h Expected Result Reg 0Fh[15:0]=36092, Reg 09h[23:0]=14942167 Reg 0Fh[15:0]=55027, Reg 09h[23:0]=14143649 Reg 0Fh[15:0]=28618, Reg 09h[23:0]=8907563 Reg oFg[15:0]=16368, Reg 09h[23:0]=3396981 For price, delivery, and to place orders, please contact Hittite Microwave Corporation: 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com HMC900LP5E v04.0811 50 MHz DUAL PROGRAMMABLE LOW PASS FILTER with DRIVER Register Map Table 13. Reg 01h - Enable Bit [0] [1] [2] [3] [4] Name OTP_DontUse cal_enable filter_I_enable filter_Q_enable force_cal_code Width 1 1 1 1 1 Default 0 0 1 1 0 Description Default use stored OTP values (only if OTP is programmed) enable RC Calibration circuit enable I channel gain stage, filter, and driver enable Q channel gain stage, filter, and driver Force calibration setting to use sPI values (Reg 03h - Calibration) 0-- Doubler Disabled. RC Calibration clock 40 MHz