HI-3210PQIF

HI-3210 May 2011 ARINC 429 DATA MANAGEMENT ENGINE / Octal Receiver / Quad Transmitter FEATURES • Eight ARINC 429 Receive channels • Four ARINC 429 Transmit channels • 32KB on chip user-configurable data storage memory GENERAL DESCRIPTION The HI-3210 from Holt Integrated Circuits is a single chip CMOS data management IC capable of managing, storing and forwarding avionics data messages between eight ARINC 429 receive channels and four ARINC 429 transmit channels. The ARINC 429 buses may be operated independently, allowing a host CPU to send and receive data on multiple buses, or the HI-3210 can be programmed to automatically re-format, re-label, re-packetize and re-transmit data from ARINC 429 receive buses to ARINC 429 transmit buses. A 32K x 8 on-board memory allows received data to be logically organized and automatically updated as new ARINC 429 labels are received. An auto-initialization feature allows configuration information to be up-loaded from an external EEPROM on reset to facilitate rapid start-up or operation without a host CPU. The HI-3210 interfaces directly with Holt’s HI-8448 octal ARINC 429 receiver IC and HI-8592 or HI-8596 ARINC 429 line drivers. • Programmable received data filtering • Programmable transmission schedulers for periodic ARINC 429 broadcasting • SPI Host CPU interface • Auto-initialization feature allows power-on configuration or independent operation without CPU PIN CONFIGURATION ARX2P ARX1N ARX1P ARX0N ARX0P SCANEN ARXBIT5 READY ESCLK EMOSI ECSB EMISO RUN ARXBIT4 ATXMSK MRST 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 APPLICATION CPU HI-8448 Memory ARINC 429 4 x Transmit ARINC 429 8 x Receive AACK 1 ARXBIT6 2 AINT 3 ARXBIT7 4 SCANSHIFT 5 ARX2N 6 ARX3P 7 VDD 8 GND 9 ARX3N 10 ARX4P 11 ARX4N 12 ARX5P 13 ARX5N 14 ARX6P 15 ARX6N 16 HI-3210PQI & HI-3210PQT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ARXBIT3 ATXSLP0 ATX0N ATX0P ATX1N ATX1P ATXSLP1 VDD GND ARXBIT2 ATXSLP2 ATX2N ATX2P ATX3N ATX3P ATXSLP3 Controller HI-3210 64 - Pin Plastic Quad Flat Pack (PQFP) (See ordering information for additional pin configurations) (DS3210 Rev. New) ARX7P ARX7N MODE0 MODE1 MCLK MODE2 ARXBIT0 VDD GND ARXBIT1 HMISO HSCLK HMOSI HCSB MINT MINTACK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 05/11 HI-3210 BLOCK DIAGRAM Host CPU MINTACK MINT ARINC 429 BIT MATCH ARXBIT7 ARXBIT6 ARXBIT5 ARXBIT4 ARXBIT3 ARXBIT2 ARXBIT1 ARXBIT0 ARINC 429 RECEIVE DATA MEMORY 0 1K x 8 HCSB HSCLK HMOSI HMISO ARINC 429 Interrupt Handler AACK AINT SPI Programmable Interrupts 4 x ARINC 429 Transmit Buses ARINC 429 Descriptor Table 0 ARINC 429 TRANSMIT SCHEDULER 0 TRANSMITTER 0 8 x ARINC 429 Receive Buses RECEIVER 0 FILTER TABLE 0 TRANSMIT TIMER CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 32 x 32 FIFO LABEL FILTER CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 Message 32 “ “ “ Message 2 Message 1 EEPROM SPI HI-3210 ECSB ESCLK EMOSI EMISO Auto-Initialization EEPROM HOLT INTEGRATED CIRCUITS 2 HI-3210 APPLICATION OVERVIEW The HI-3210 is a flexible device for managing ARINC 429 communications and data storage in many avionics applications. The device architecture centers around a 32K x 8 static RAM used for data storage, data filtering tables and table-driven transmission schedulers. Once configured, the device can operate autonomously without a host CPU, negating the need for software development or DO-178 certification. Configuration data may be uploaded into the device from an external EEPROM, following system reset. The device supports up to eight ARINC 429 receive channels. Received data is stored in on-chip RAM organized by channel number and label. The data table continually updates as new labels arrive. Programmable interrupts and filters alert the host subsystem to labels of interest. Each ARINC 429 receive channel also includes a 32 message deep FIFO allowing selected label data to be queued for subsequent host access. The HI-3210 includes four independent ARINC 429 transmit channels. Transmission may be controlled entirely by an external CPU, or autonomously by programming one or more of the four on-chip ARINC 429 transmit schedulers. These allow periodic transmission to occur without CPU. Source data for transmission may be selected from RAM based tables of constants and / or from the received channel data. Powerful options exist for constructing ARINC 429 labels as well as controlling their timing and conditional transmission. Even when running under the control of schedulers, the host CPU may insert new labels for transmission at will. The following examples show five possible configurations of how the HI-3210 may be used: Example 1. ARINC 429 Data reception using on-chip RAM RECEIVER 7 Channel 7, Label FF “ “ “ Channel 7, Label 01 Channel 7, Label 00 RECEIVER 6 Channel 6, Label FF “ “ “ Channel 6, Label 01 Channel 6, Label 00 Channel 5, Label FF “ “ “ Channel 5, Label 01 Channel 5, Label 00 RECEIVER 5 8 x ARINC 429 Receive Buses RECEIVER 4 Channel 4, Label FF “ “ “ Channel 4, Label 01 Channel 4, Label 00 Channel 3, Label FF “ “ “ Channel 3, Label 01 Channel 3, Label 00 Channel 2, Label FF “ “ “ Channel 2, Label 01 Channel 2, Label 00 ARINC 429 RECEIVE INTERRUPT TABLE AINT AACK Host CPU SPI HCSB HSCLK HMOSI HMISO RECEIVER 3 RECEIVER 2 RECEIVER 1 Channel 1, Label FF “ “ “ Channel 1, Label 01 Channel 1, Label 00 Channel 0, Label FF “ “ “ Channel 0, Label 01 Channel 0, Label 00 RECEIVER 0 8K x 8 RAM HI-3210 HOLT INTEGRATED CIRCUITS 3 HI-3210 Example 2. ARINC 429 Data reception using on-chip filters and FIFOs FILTER TABLE 0 RECEIVER 0 LABEL FILTER Message 32 “ “ “ Message 2 Message 1 8 x ARINC 429 Receive Buses 32 x 32 FIFO SPI FIFO STATUS HCSB HSCLK HMOSI HMISO Host CPU FIFO EMPTY FIFO THRESHOLD FIFO FULL CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 ARINC 429 RECEIVE FIFO INTERRUPT CONTROL AINT AACK HI-3210 Example 3. ARINC 429 Data transmission directly from CPU TRANSMITTER 0 Host CPU HCSB HSCLK HMOSI HMISO TRANSMITTER 1 SPI TRANSMITTER 2 4 x ARINC 429 Transmit Buses TRANSMITTER 3 HI-3210 Example 4. ARINC 429 Data transmission using on-chip schedulers Descriptor Table 0 TRANSMIT SCHEDULER 0 TRANSMITTER 0 Host CPU HCSB HSCLK HMOSI HMISO SPI Descriptor Table 1 TRANSMIT TIMER CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 4 x ARINC 429 Transmit Buses Descriptor Table 2 Auto-Initialization EEPROM ECSB ESCLK EMOSI EMISO EEPROM SPI Descriptor Table 3 RAM HI-3210 H OLT INTEGRATED CIRCUITS 4 HI-3210 Example 5. Autonomous ARINC 429 Data Concentrator / Repeater RECEIVER 7 Channel 7, Label FF “ “ “ Channel 7, Label 01 Channel 7, Label 00 RECEIVER 6 Channel 6, Label FF “ “ “ Channel 6, Label 01 Channel 6, Label 00 Channel 5, Label FF “ “ “ Channel 5, Label 01 Channel 5, Label 00 Descriptor Table 3 TRANSMIT SCHEDULER 3 TRANSMITTER 3 TRANSMIT TIMER RECEIVER 5 8 x ARINC 429 Receive Buses RECEIVER 4 Channel 4, Label FF “ “ “ Channel 4, Label 01 Channel 4, Label 00 Channel 3, Label FF “ “ “ Channel 3, Label 01 Channel 3, Label 00 Channel 2, Label FF “ “ “ Channel 2, Label 01 Channel 2, Label 00 Channel 1, Label FF “ “ “ Channel 1, Label 01 Channel 1, Label 00 Descriptor Table 2 TRANSMIT SCHEDULER 2 TRANSMITTER 2 4 x ARINC 429 Transmit Buses TRANSMIT TIMER RECEIVER 3 Descriptor Table 1 TRANSMIT SCHEDULER 1 TRANSMITTER 1 RECEIVER 2 TRANSMIT TIMER RECEIVER 1 Descriptor Table 0 RECEIVER 0 Channel 0, Label FF “ “ “ Channel 0, Label 01 Channel 0, Label 00 TRANSMIT SCHEDULER 0 TRANSMITTER 0 TRANSMIT TIMER EEPROM SPI HI-3210 ECSB ESCLK EMOSI EMISO Auto-Initialization EEPROM H OLT INTEGRATED CIRCUITS 5 HI-3210 PIN DESCRIPTIONS SIGNAL AACK AINT ARX0N ARX0P ARX1N ARX1P ARX2N ARX2P ARX3N ARX3P ARX4N ARX4P ARX5N ARX5P ARX6N ARX6P ARX7N ARX7P ARXBIT0-7 ATX0N ATX0P ATX1N ATX1P ATX2N ATX2P ATX3N ATX3P ATXMSK ATXSLP0 ATXSLP1 ATXSLP2 ATXSLP3 ECSB EMISO EMOSI ESCLK GND HCSB HMISO HMOSI HSCLK MCLK MINT MINTACK MODE2:0 MRST PROG (MODE0) READY RUN SCANEN SCANSHIFT VDD FUNCTION INPUT OUTPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT OUTPUTS OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT OUTPUT OUTPUT POWER INPUT OUTPUT INPUT INPUT INPUT OUTPUT INPUT INPUTS INPUT INPUT OUTPUT INPUT RESERVED RESERVED POWER DESCRIPTION ARINC 429 Receiver Interrupt Acknowledge ARINC 429 Receiver Interrupt ARINC 429 Rx negative data input for channel 0 ARINC 429 Rx positive data input for channel 0 ARINC 429 Rx negative data input for channel 1 ARINC 429 Rx positive data input for channel 1 ARINC 429 Rx negative data input for channel 2 ARINC 429 Rx positive data input for channel 2 ARINC 429 Rx negative data input for channel 3 ARINC 429 Rx positive data input for channel 3 ARINC 429 Rx negative data input for channel 4 ARINC 429 Rx positive data input for channel 4 ARINC 429 Rx negative data input for channel 5 ARINC 429 Rx positive data input for channel 5 ARINC 429 Rx negative data input for channel 6 ARINC 429 Rx positive data input for channel 6 ARINC 429 Rx negative data input for channel 7 ARINC 429 Rx positive data input for channel 7 ARINC 429 received payload bit monitor pins 0 through 7 ARINC 429 Tx channel 0 negative data output to line driver ARINC 429 Tx channel 0 positive data output to line driver ARINC 429 Tx channel 1 negative data output to line driver ARINC 429 Tx channel 1 positive data output to line driver ARINC 429 Tx channel 2 negative data output to line driver ARINC 429 Tx channel 2 positive data output to line driver ARINC 429 Tx channel 3 negative data output to line driver ARINC 429 Tx channel 3 positive data output to line driver Turn off ARINC 429 Transmit pins (Holds TXnA/B pins zero) ARINC 429 Tx channel 0 data rate select output. 1 = high speed, 0 = low speed ARINC 429 Tx channel 1 data rate select output. 1 = high speed, 0 = low speed ARINC 429 Tx channel 2 data rate select output. 1 = high speed, 0 = low speed ARINC 429 Tx channel 3 data rate select output. 1 = high speed, 0 = low speed SPI chip select for auto-initialization EEPROM SPI serial data input from auto-inialization EEPROM SPI serial data output to auto-initialization EEPROM SPI clock for auto-initialization EEPROM Chip 0V supply Chip select. Data is shifted into HMOSI and out of HMISO when HCSB is low Host CPU SPI interface serial data output Host CPU SPI interface serial data input SPI Clock. Data is shifted into or out of the SPI interface using HSCLK Master 48 MHZ and reference clock for ARINC 429 bus bit timing Programmable event interrupt output Programmable event interrupt acknowledge MODE2 through MODE0 define HI-3210 start-up and initialization mode Master Reset to HI-3210 Active High Multiplexed with MODE0 pin, PROG initiates HI-3210 Auto-Initialization EEPROM programming routine READY goes high when post-RESET initialization is complete Master enable signal for ARINC 429 transmit schedulers Connect to GND Connect to GND 3.3V power supply H OLT INTEGRATED CIRCUITS 6 HI-3210 HI-3210 MEMORY MAP 0x8XXX Configuration Registers 0x8000 0x7FFF RESERVED 0x7C00 0x7BFF ARINC 429 RX Interrupt Map Look-up Tables 0x7A00 0x79FF ARINC 429 RX Enable Map 0x7BFF 0x7B00 0x7AFF 0x7A00 RESERVED 0x6000 0x5FFF 0x5800 0x57FF 0x5000 0x4FFF 0x4800 0x47FF 0x4000 0x3FFF ARINC 429 TX3 Transmit Schedule Table ARINC 429 TX2 Transmit Schedule Table ARINC 429 TX1 Transmit Schedule Table ARINC 429 TX0 Transmit Schedule Table RESERVED 0x3400 0x33FF 0x3000 0x2FFF ARINC 429 Log FIFO Space RESERVED 0x2000 0x1FFF Shaded Area User - Programmed ARINC 429 Receive Data Non-shaded Area Data Storage 0x0000 HOLT INTEGRATED CIRCUITS 7 HI-3210 HI-3210 REGISTER MAP ADDRESS R/W 0x8000 0x8001 0x8002 0x8003 0x8004 0x8005 0x8006 0x8007 0x8008 0x8009 0x800A 0x800B 0x800C 0x800D 0x800E 0x800F 0x8010 0x8011 0x8012 0x8013 0x8014 0x8015 0x8016 0x8017 0x8018 0x8019 0x801A 0x801B 0x801C 0x801D 0x801E 0x801F 0x8020 0x8021 0x8022 0x8029 0x802A 0x802B 0x802C 0x802D 0x802E 0x802F 0x8034 0x8035 R* R R R R R R R R R* R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R/W R/W REGISTER ARINC 429 Rx PENDING INTERRUPT ARINC 429 Rx INTERRUPT ADDRESS 0 ARINC 429 Rx INTERRUPT ADDRESS 1 ARINC 429 Rx INTERRUPT ADDRESS 2 ARINC 429 Rx INTERRUPT ADDRESS 3 ARINC 429 Rx INTERRUPT ADDRESS 4 ARINC 429 Rx INTERRUPT ADDRESS 5 ARINC 429 Rx INTERRUPT ADDRESS 6 ARINC 429 Rx INTERRUPT ADDRESS 7 RESERVED PENDING INTERRUPT REGISTER RESERVED MUXED FIFO FLAGS ARINC 429 TX READY BITS MASTER STATUS REGISTER MASTER CONTROL REGISTER ARINC 429 RX CONTROL REGISTER 0 ARINC 429 RX CONTROL REGISTER 1 ARINC 429 RX CONTROL REGISTER 2 ARINC 429 RX CONTROL REGISTER 3 ARINC 429 RX CONTROL REGISTER 4 ARINC 429 RX CONTROL REGISTER 5 ARINC 429 RX CONTROL REGISTER 6 ARINC 429 RX CONTROL REGISTER 7 ARINC 429 TX CONTROL REGISTER 0 ARINC 429 TX CONTROL REGISTER 1 ARINC 429 TX CONTROL REGISTER 2 ARINC 429 TX CONTROL REGISTER 3 ARINC 429 TX REPETITION RATE 0 ARINC 429 TX REPETITION RATE 1 ARINC 429 TX REPETITION RATE 2 ARINC 429 TX REPETITION RATE 3 ARINC 429 Rx INTERRUPT MASK ARINC 429 Rx FIFO THRESHOLD VALUE ARINC 429 LOOPBACK ARINC 429 Rx FIFO FULL FLAG ARINC 429 Rx FIFO THRESHOLD FLAG ARINC 429 Rx FIFO NOT EMPTY FLAG ARINC 429 TX SEQUENCE POINTER 0 ARINC 429 TX SEQUENCE POINTER 1 ARINC 429 TX SEQUENCE POINTER 2 ARINC 429 TX SEQUENCE POINTER 3 INTERRUPT MASK REGISTER ARINC 429 TX READY INT ENABLE MNEMONIC APIR AIAR0 AIAR1 AIAR2 AIAR3 AIAR4 AIAR5 AIAR6 AIAR7 PIR AMFF ATRB MSR MCR ARXC0 ARXC1 ARXC2 ARXC3 ARXC4 ARXC5 ARXC6 ARXC7 ATXC0 ATXC1 ATXC2 ATXC3 ATXRR0 ATXRR1 ATXRR2 ATXRR3 AIMR AFTV ALOOP AFFF AFTF FFNE ATXSP0 ATXSP1 ATXSP2 ATXSP3 IMR ATRIE DESCRIPTION Defines channel(s) with pending Interrupt ARINC 429 Interrupt Vector channel 0 ARINC 429 Interrupt Vector channel 1 ARINC 429 Interrupt Vector channel 2 ARINC 429 Interrupt Vector channel 3 ARINC 429 Interrupt Vector channel 4 ARINC 429 Interrupt Vector channel 5 ARINC 429 Interrupt Vector channel 6 ARINC 429 Interrupt Vector channel 7 Indicates Interrupt type ARINC 429 Multiplexed FIFO flags ARINC 429 Transmitter Ready flags Indicates HI-3200 current status HI-3200 global configuration Configures ARINC 429 receive channel 0 Configures ARINC 429 receive channel 1 Configures ARINC 429 receive channel 2 Configures ARINC 429 receive channel 3 Configures ARINC 429 receive channel 4 Configures ARINC 429 receive channel 5 Configures ARINC 429 receive channel 6 Configures ARINC 429 receive channel 7 Configures ARINC 429 transmit channel 0 Configures ARINC 429 transmit channel 1 Configures ARINC 429 transmit channel 2 Configures ARINC 429 transmit channel 3 Sets sequence repeat time for ARINC TX0 Sets sequence repeat time for ARINC TX1 Sets sequence repeat time for ARINC TX2 Sets sequence repeat time for ARINC TX3 Enables Interrupts on AINT pin Sets flag value for ARINC 429 Receive FIFO Sets loop-back self-test mode Indicates which FIFOs are full Indicates which FIFOs hold > (thresh) messages Indicates which receive FIFOs hold data Current address of ARINC transmit sequence 0 Current address of ARINC transmit sequence 1 Current address of ARINC transmit sequence 2 Current address of ARINC transmit sequence 3 Enables Interrupts on INT pin Enables ARINC 429 TX Ready Interrupts Fast Access Registers Memory mapped register access only * Register is cleared when read (auto clear) HOLT INTEGRATED CIRCUITS 8 HI-3210 ADDRESS R/W 0x805F 0x8060 0x8061 0x8062 0x8063 0x8064 0x8065 0x8066 0x8067 0x8068 0x8069 0x806A 0x806B 0x806C 0x806D 0x806E 0x806F 0x8070 0x8071 0x8072 0x8073 0x8074 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R REGISTER PINS ARXBIT[7:0] PIN ARXBIT0 CONFIG REG 1 PIN ARXBIT0 CONFIG REG 2 PIN ARXBIT1 CONFIG REG 1 PIN ARXBIT1 CONFIG REG 2 PIN ARXBIT2 CONFIG REG 1 PIN ARXBIT2 CONFIG REG 2 PIN ARXBIT3 CONFIG REG 1 PIN ARXBIT3 CONFIG REG 2 PIN ARXBIT4 CONFIG REG 1 PIN ARXBIT4 CONFIG REG 2 PIN ARXBIT5 CONFIG REG 1 PIN ARXBIT5 CONFIG REG 2 PIN ARXBIT6 CONFIG REG 1 PIN ARXBIT6 CONFIG REG 2 PIN ARXBIT7 CONFIG REG 1 PIN ARXBIT7 CONFIG REG 2 BIST CONTROL/STATUS BIST FAIL ADDRESS [7:0] BIST FAIL ADDRESS [12:8] AUTO-INIT FAIL LS ADDRESS [7:0] AUTO-INIT FAIL MS ADDRESS [15:8] MNEMONIC ARXBIT ARX0CR1 ARX0CR2 ARX1CR1 ARX1CR2 ARX2CR1 ARX2CR2 ARX3CR1 ARX3CR2 ARX4CR1 ARX4CR2 ARX5CR1 ARX5CR2 ARX6CR1 ARX6CR2 ARX7CR1 ARX7CR2 BISTS BISTFL BISTFH AIFL AIFH DESCRIPTION Values of pins ARXBIT[7:0] ARINC 429 bit Monitor 0 channel & bit select ARINC 429 bit Monitor 0 label select ARINC 429 bit Monitor 1 channel & bit select ARINC 429 bit Monitor 1 label select ARINC 429 bit Monitor 2 channel & bit select ARINC 429 bit Monitor 2 label select ARINC 429 bit Monitor 3 channel & bit select ARINC 429 bit Monitor 3 label select ARINC 429 bit Monitor 4 channel & bit select ARINC 429 bit Monitor 4 label select ARINC 429 bit Monitor 5 channel & bit select ARINC 429 bit Monitor 5 label select ARINC 429 bit Monitor 6 channel & bit select ARINC 429 bit Monitor 6 label select ARINC 429 bit Monitor 7 channel & bit select ARINC 429 bit Monitor 7 label select Built-In Self-Test Low-order failing BIST memory address High-order failing BIST memory address Auto-initialization fail address (low-byte) Auto-initialization fail address (high byte) H OLT INTEGRATED CIRCUITS 9 HI-3210 HI-3210 SYSTEM CONFIGURATION Starting at memory address 0x8000, the HI-3210 contains a set of registers that are used to configure the device. The user needs only to program the HI-3210 configuration registers to completely define the full system operation. The configuration registers are divided into three categories, as follows; 1. HI-3210 global configuration 2. ARINC 429 Receive channel configuration 3. ARINC 429 Transmit channel configuration HI-3210 Global Configuration The following registers define the HI-3210 top-level configuration: 29 A4 RX 29 TX LI 0 4 3 MASTER CONTROL REGISTER (Address 0x800F) Bit Name 7 A429RX R/W R/W Default Description 0 0 76 MSB 5 AF X 2 A4 P X 1 X 0 LSB This bit must be set to a “1” to allow the HI-3210 to receive ARINC 429 data on any of the eight channels. If set to a zero, the HI-3210 will not respond to any ARINC 429 receive bus, regardless of the state of the ARINC 429 Receive channel Control Registers. This bit must be set to a “1” to allow the HI-3210 to transmit ARINC 429 data on any of the four channels. If set to a zero, the HI-3210 will not output ARINC 429 data and the ARINC 429 transmit sequencers will remain in their reset state. Must be ‘0’ Must be ‘0’ When set to a “1”, this bit switches the bit order of the ARINC 429 label byte in both receive and transmit channels. Not Used Not Used Not Used 6 A429TX R/W 0 5 4 3 2 1 0 AFLIP - R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 HOLT INTEGRATED CIRCUITS 10 HI-3210 HI-3210 Operational Status Information The Master Status Register may be read at any time to determine the current operational state of the HI-3210: EA AC DY T SA IVE F RE AM PR BU OS AU G Y TO IN IT X 76 MSB 5 4 3 2 1 X 0 LSB MASTER STATUS REGISTER (Address 0x800E) Bit Name 7 6 5 4 3 2 1 0 READY ACTIVE SAFE RAM BUSY PROG AUTOINIT R/W R R R R R R R R Default Description 0 0 0 0 0 0 0 0 This bit is high, when the READY output pin is high, indicating that the part is able to accept and respond to host CPU SPI commands This bit is high after RUN is asserted and the HI-3210 is in normal operating mode. This bit goes high when the part enters safe mode as a result of a Built-in Self-test fail or autoinitialization fail. This is high during the time the RAM Integrity Check is running and RAM is clearing Indicates that the HI-3210 is currently in the EEPROM programming cycle. Note that READY stays low until the cycle is complete. The HI-3210 is currently loading internal memory, registers and look-up tables from the Autoinitialization EEPROM Not used Not Used HOLT INTEGRATED CIRCUITS 11 R HI-3210 ARINC 429 RECEIVE OPERATION The HI-3210 can receive ARINC 429 messages from up to eight ARINC 429 receive buses. External analog line receivers handle the physical layer connection ARINC 429 Receive Channel Configuration Each of the eight possible ARINC 429 Receive channels is configured using its own Control Register. Register address 0x8010 controls ARINC 429 Receive channel #0, register address 0x8011 controls channel #1 and so on. ARINC 429 Receive Control Registers may be read at any time, but can only be written when the device is in the IDLE state (RUN input = “0”, READY output = “1”). EN A R BL AT E PA E R D ITY EC E N SD OD 10 ER SD 9 FF S1 FF S0 ARINC 429 RX CONTROL REGISTER 0 - 7 (Address 0x8010 - 0x8017) Bit Name 7 6 5 ENABLE HI / LO PARITYEN R/W R/W R/W R/W Default Description 0 0 0 76 MSB 5 4 3 2 1 0 LSB This bit must be set to a “1” to enable ARINC 429 data reception on this channel. Selects the ARINC 429 bit rate for the ARINC 429 receive channel. A “0” selects high-speed (100Kb/s) and a “1” selects low-speed (12.5Kb/s). When this bit is a one, the 32nd received ARINC bit is overwritten with a parity flag. The flag bit is set to a zero when the received ARINC word, including its parity bit has an odd number of ones. When PARITYEN is a zero, all 32-bits are received without parity checking. When DECODER is a “1”, bits 9 and 10 of ARINC 429 words received on this channel must match the SD9 and SD10 bits in the register. ARINC words received that do not match the SD conditions are ignored. If DECODER is set to a “1”, then this bit must match the received ARINC word bit 10 for the word to be accepted. If DECODER is set to a “1”, then this bit must match the received ARINC word bit 9 for the word to be accepted. FFS1 and FFS0 define when this channel’s FIFO Flag is set, as shown below. 4 DECODER R/W 0 3 2 SD10 SD9 R/W R/W R/W 0 0 0 1-0 FFS1:0 FFS1 0 0 1 1 FFS0 0 1 0 1 FLAG set condition FLAG never set Set FLAG if FIFO NOT EMPTY bit = “1” Set FLAG if FIFO > Threshold value Set FLAG is FIFO FULL bit “1” HOLT INTEGRATED CIRCUITS 12 HI-3210 ARINC 429 Received Data Management The HI-3210 supports eight ARINC 429 receive buses using on-chip receivers to handle the protocol validation. The eight ARINC 429 RX Control Registers, ARXC0 - 7, define the characteristics of each receive channel. The ARINC 429 receive function of the HI-3210 is activated by setting the A429RX bit in the Master Control Register. When an ARINC 429 message is received by the HI-3210 on any bus, it is checked for protocol compliance. Messages with incorrect encoding are rejected. The HI-3210 contains an 8K byte memory for storing ARINC 429 received data. The memory is organized by channel number and ARINC 429 label value. Four bytes of memory are dedicated to each channel / label to store the 32-word ARINC 429 message. A look-up table is used to enable an interrupt on receipt of a new ARINC 429 message. Look-up table bit positions preloaded with a “1” will cause an Interrupt to be generated. When a message is received that triggers an Interrupt, that channel’s Interrupt bit is set in the ARINC 429 Receive Pending Interrupt Register. If this bit is unmasked in the ARINC 429 Receive Interrupt Mask Register, the AINT output pin is asserted. The label number of the ARINC 429 message causing the interrupt is loaded into that channel’s ARINC 429 Receive Interrupt Address Register (AIAR0 - AIAR7). Because the ARINC Receive Memory is organized by label value, it is not necessary to store the received label value (first eight bits of the ARINC message) in the memory. Instead, the first byte is used to store a status byte. The six active bits of the status byte are set to “1” when a new ARINC word is stored in the memory. These bits flag the ARINC word as new when the location is interrogated by the host CPU or any of the four ARINC 429 transmit schedulers. ARINC 429 Received Data Memory Organization 0x1FFF 0x1FFC Block 2048 Channel 7, Label FF 0x000B 0x0008 0x0007 Block 3 Channel 0, Label 02 Block 2 Channel 0, Label 01 0x0003 0x0002 0x0001 0x0000 Etc. ARINC data byte 4 ARINC data byte 3 ARINC data byte 2 Status Byte 0x0004 0x0003 Block 1 Channel 0, Label 00 0x0000 HOLT INTEGRATED CIRCUITS 13 HI-3210 ARINC 429 Received Data Interrupt Look-Up Table 0x7BFF 0x7BE0 Interrupt Look-Up Table Channel 7 Label = 0xFF Label = 0xF8 0x7B3F 0x7B20 0x7B1F 0x7B00 Label = 0x08 Interrupt Look-Up Table Channel 1 Interrupt Look-Up Table Channel 0 Label = 0x07 Label = 0x0F 7 6 5 4 3 2 1 0 Label = 0x00 Label = 0x01 ARINC 429 Received Data Status Byte Definition ST EW H O N N X 5 4 3 2 1 0 LSB STATUS BYTE X X 76 MSB Bit Name 7 6 5 4 3 2 1 0 NEWHOST NEWTX3 NEWTX2 NEWTX1 NEWTX0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default Description 0 0 0 0 0 0 0 0 Not used Not used This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when the host CPU executes SPI instruction 0xC0 - 0xFF to read the block. Not Used This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when the ARINC 429 Transmit scheduler #3 reads any bytes from the block. This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when theARINC 429 Transmit scheduler #2 reads any bytes from the block. This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when theARINC 429 Transmit scheduler #1 reads any bytes from the block. This bit is set when a new ARINC 429 word is received and stored in this block. It is reset when the ARINC 429 Transmit scheduler #0 reads any bytes from the block. T EW X3 N TX EW 2 N TX EW 1 TX 0 N EW HOLT INTEGRATED CIRCUITS 14 HI-3210 ARINC 429 Received Data Log FIFO A 1K x 8 block of memory located between 0x3000 and 0x33FF is reserved for a set of eight ARINC 429 received data FIFOs. There is one FIFO for each ARINC 429 received data channel. Each FIFO can hold up to 32 ARINC 429 32-bit messages. A look-up table driven filter defines which ARINC 429 messages are stored in each FIFO. The look-up table is pre-loaded with a “1” for each bit position corresponding to a selected channel / label combination. The look-up table is located at memory address 0x7A00. When a new ARINC 429 message is received that meets the programmed conditions for acceptance (Enable lookup table bit = “1”), it is written into the channel’s Receive Data FIFO. The contents of the FIFO may be read by the host CPU using dedicated FIFO read SPI Instructions. The status of each channel’s FIFOs is monitored by three FIFO status registers: FIFO NOT EMPTY, FIFO THRESHOLD, and FIFO FULL. One bit of each register reflects the current status of each FIFO. The FIFOs are empty following Reset. All three status registers are cleared. When an ARINC 429 message is written to a FIFO, its FIFO NOT EMPTY bit is set to a “1”. When the FIFO contains more than the user-defined number of messages as programmed in the ARINC FIFO THRESHOLD VALUE register, its FIFO THRESHOLD bit is set. If the FIFO is allowed to accumulate 32 messages, its FIFO FULL bit is set. Once a FIFO is full, subsequent messages continue to be written to the FIFO, and the oldest message is lost. The user may generate an Interrupt by enabling one of the three FIFO status register bits to assert the FLAG bit in the Pending Interrupt Register. ARINC 429 Control Register bits 1:0 select the condition to trigger the FLAG interrupt. The FIFO feature is particularly useful if the application wishes to accumulate sequential ARINC 429 messages of the same label value before reading them. The regular ARINC 429 receive data memory will, of course, overwrite messages of the same label value if a new message is received before the host CPU extracts the data. ARINC 429 Received Data Enable Look-Up Table 0x7AFF 0x7AE0 Filter Look-Up Table Channel 7 Label = 0xFF Label = 0xF8 0x7A3F 0x7A20 0x7A1F 0x7A00 Label = 0x08 Filter-Look-Up Table Channel 1 Filter Look-Up Table Channel 0 Label = 0x07 Label = 0x0F 7 6 5 4 3 2 1 0 Label = 0x00 Label = 0x01 ARINC 429 Received Data FIFO (x8) FIFO NOT EMPTY A FNEn AFHFn A FFn Select FLAGn Message 2 (32-bits) Message 1 (32-bits) ARINC 429 received message Data read by Host CPU SPI Instruction FIFO THRESHOLD FIFO FULL ARXCn From Other Channels 0 - 32 Messages (32-bits) } OR PIR FLAG HOLT INTEGRATED CIRCUITS 15 HI-3210 ARINC 429 Received Data FIFO Status Registers AF N AF E7 N AF E6 N AF E5 N AF E4 N AF E3 N AF E2 N AF E1 N E0 FIFO NOT EMPTY REGISTER (Address 0x802B) Bit Name 7 6 5 4 3 2 1 0 AFNE7 AFNE6 AFNE5 AFNE4 AFNE3 AFNE2 AFNE1 AFNE0 R/W R R R R R R R R 76 MSB 5 4 3 2 1 0 LSB Default Description 0 0 0 0 0 0 0 0 This bit is set to “1” if FIFO #7 contains at least one ARINC 429 message This bit is set to “1” if FIFO #6 contains at least one ARINC 429 message This bit is set to “1” if FIFO #5 contains at least one ARINC 429 message This bit is set to “1” if FIFO #4 contains at least one ARINC 429 message This bit is set to “1” if FIFO #3 contains at least one ARINC 429 message This bit is set to “1” if FIFO #2 contains at least one ARINC 429 message This bit is set to “1” if FIFO #1 contains at least one ARINC 429 message This bit is set to “1” if FIFO #0 contains at least one ARINC 429 message T AF F7 T AF F6 T AF F5 T AF F4 T AF F3 T AF F2 T AF F1 TF 0 LSB FIFO THRESHOLD REGISTER (Address 0x802A) 76543210 MSB Bit Name 7 6 5 4 3 2 1 0 AFTF7 AFTF6 AFTF5 AFTF4 AFTF3 AFTF2 AFTF1 AFTF0 R/W R R R R R R R R Default Description 0 0 0 0 0 0 0 0 This bit is set to “1” if FIFO #7 contains > threshold number of ARINC 429 messages This bit is set to “1” if FIFO #6 contains > threshold number of ARINC 429 messages This bit is set to “1” if FIFO #5 contains > threshold number of ARINC 429 messages This bit is set to “1” if FIFO #4 contains > threshold number of ARINC 429 messages This bit is set to “1” if FIFO #3 contains > threshold number of ARINC 429 messages This bit is set to “1” if FIFO #2 contains > threshold number of ARINC 429 messages This bit is set to “1” if FIFO #1 contains > threshold number of ARINC 429 messages This bit is set to “1” if FIFO #0 contains > threshold number of ARINC 429 messages F AF F7 F AF F6 F AF F5 F AF F4 F AF F3 F AF F2 F AF F1 FF 0 5 4 3 2 1 0 LSB FIFO FULL REGISTER (Address 0x8029) Bit Name 7 6 5 4 3 2 1 0 AFFF7 AFFF6 AFFF5 AFFF4 AFFF3 AFFF2 AFFF1 AFFF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W 76 MSB Default Description 0 0 0 0 0 0 0 0 This bit is set to “1” if FIFO #7 contains 32 ARINC 429 messages This bit is set to “1” if FIFO #6 contains 32 ARINC 429 messages This bit is set to “1” if FIFO #5 contains 32 ARINC 429 messages This bit is set to “1” if FIFO #4 contains 32 ARINC 429 messages This bit is set to “1” if FIFO #3 contains 32 ARINC 429 messages This bit is set to “1” if FIFO #2 contains 32 ARINC 429 messages This bit is set to “1” if FIFO #1 contains 32 ARINC 429 messages This bit is set to “1” if FIFO #0 contains 32 ARINC 429 messages AF AF HOLT INTEGRATED CIRCUITS 16 HI-3210 ARINC 429 FIFO Threshold Value Register Threshold FIFO THRESHOLD VALUE (Address 0x8021) Threshold Value 00000 00001 00010 00011 Description 0 0 0 5 4 3 2 1 0 LSB Default = 0x10 76 MSB Threshold flag is set if at least 1 message is in FIFO (Same as FIFO NOT EMPTY FLAG) Threshold flag is set if more than one message are in the FIFO Threshold flag is set if more than two messages are in the FIFO Threshold flag is set if more than three messages are in the FIFO 10000 Threshold flag is set if more than sixteen messages are in the FIFO (default) 11111 Threshold flag is set if 32 messages are in the FIFO (Same as FIFO FULL FLAG) ARINC 429 Loop-back Self-Test The HI-3210 includes an ARINC 429 loop-back feature, which allows users to exercise the ARINC 429 transmit and receive channels for self-test purposes. The ARINC 429 Loop-Back register, ALOOP defines which receiver channels are in loop-back mode. When a “1” is programmed in the ALOOP bit position for a receiver, then its ARINC 429 bus connection to the external pins is broken and instead the input is connected to one of the four ARINC 429 transmit channels. Transmit channel 0 is connected to receive channel 0 and 1, transmit channel 1 is connected to receive channels 2 and 3, and so on. When in loop-back mode, incoming ARINC 429 messages are ignored by the HI-3210. When running in loop-back mode the ARINC 429 transmit pins may be disabled by pulling the TXMSK input high. This prevents test messages from being output to the external ARINC 429 transmit buses. ARINC 429 LOOPBACK (Address 0x8022) Bit Name 7 6 5 4 3 2 1 0 ALOOP7 ALOOP6 ALOOP5 ALOOP4 ALOOP3 ALOOP2 ALOOP1 ALOOP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W 76 MSB Default Description 0 0 0 0 0 0 0 0 This bit is set to “1” to loop-back transmit channel 3 to receiver 7 This bit is set to “1” to loop-back transmit channel 3 to receiver 6 This bit is set to “1” to loop-back transmit channel 2 to receiver 5 This bit is set to “1” to loop-back transmit channel 2 to receiver 4 This bit is set to “1” to loop-back transmit channel 1 to receiver 3 This bit is set to “1” to loop-back transmit channel 1 to receiver 2 This bit is set to “1” to loop-back transmit channel 0 to receiver 1 This bit is set to “1” to loop-back transmit channel 0 to receiver 0 O AL OP O7 AL OP O6 AL OP O5 AL OP O4 AL OP O3 AL OP O2 AL OP O1 O P0 5 4 3 2 1 0 LSB AL HOLT INTEGRATED CIRCUITS 17 HI-3200, HI-3201 ARINC 429 Bit ordering ARINC 429 messages consist of a 32-bit sequence as shown below. The first eight bits that appear on the ARINC 429 bus are the label byte. The next twenty three bits comprise a data field which presents data in a variety of formats defined in the ARINC 429 specification. The last bit transmitted is an odd parity bit. The HI-3210 stores the received message as four bytes. The bytes are stored in memory in little-endian order. That is to say, the label byte (or status byte) is stored at the lowest memory address, the byte representing received bits 9 through 16 is stored at the next address, the byte representing bits 17 through 24 at the next address and the byte representing bits 25 though 32 at the highest address. The ARINC 429 specifies the MSB of the label as ARINC bit 1. Conversely, the data field MSB is bit 31. So the bit significance of the label byte and data fields are opposite. The HI-3210 may be programmed to “flip” the bit ordering of the label byte as soon as it is received and immediately prior to transmission. This is accomplished by setting the AFLIP bit to a “1” in the Master Control Register. Note that once the label byte has been flipped, the HI-3210 handles the flipped data byte “post-flip” for the purpose of label interrupt matching, filtering and storage. ARINC 429 Message as received / transmitted on the ARINC 429 serial bus 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 time ARINC 429 Message as stored in HI-3210 memory Byte 3 Byte 2 Byte 1 Byte 0 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AFLIP = “0” AFLIP = “1” HOLT INTEGRATED CIRCUITS 18 PA R I SD SD I IT MSB LABEL LSB LSB DATA MSB Y HI-3210 ARINC 429 Bit Monitor Pins The HI-3210 has the capability of externally monitoring any ARINC 429 received payload bit through the pins ARXBIT[7:0]. When the appropriate ARINC 429 receiver is enabled and the target label is received, the monitored bit value will be reflected on the pin. This allows the user to monitor any ARINC 429 received payload bit without performing any host SPI reads. The following registers configure the functionality of these monitor pins. Note that all these control register bits are RESET to zero. PINS ARXBIT[7:0] REGISTER (Address 0x805F) 76 MSB Bit Name 7:0 ARXBIT[7:0] R/W R/W Default Description 0 These bits reflect the value of the corresponding pins ARXBIT[7:0]. After reset, all values are zero. When a monitored ARINC 429 bit changes, this register is updated with the value, which is reflected on the corresponding pin. The purpose of this register is to allow the user to preset the ARXBIT values after chip reset. PIN ARXBIT0 CONFIGURATION REGISTER 1 (Address 0x8060) Bit Name 7:5 ARXCR1[7:5] 4:0 ARXCR1[4:0] R/W R/W R/W Default Description 0 0 76 MSB These bits select which receive channel (0 through 7) will have bits monitored and reflected on the pin ARXBIT0. These bits select which bit (8 through 31) of the ARINC payload will be reflected on the pin ARXBIT0. The receiver is specified by bits ARX0CR1[7:5] and the target label is specified by pin ARXBIT0 Configuration Register 2 described below. Note that bits 0 through 7 of the ARINC payload are not monitored and selecting these bits results in no effect. PIN ARXBIT0 CONFIGURATION REGISTER 2 (Address 0x8061) 76 MSB Bit Name 7:0 ARXCR2[7:0] R/W R/W Default Description 0 These bits select which label (0 through 255) will have bits monitored and reflected on the pin ARXBIT0. The receive channel and specific bits monitored are specified in ARXBIT0 Configuration Register 1 described above. PINS ARXBIT1 Through ARXBIT7 CONFIGURATION REGISTERS (Addresses 0x8062 to 0x806F) Each pin ARXBIT1 through ARXBIT7 are also specified by a pair of configuration registers similar to ARXBIT0 described above. Functionality is exactly the same. The register addresses for each pin specification are listed in the Register Map section (see page 9). Note that HI-3210 provides external monitoring of eight bits through pins ARXBIT7 to ARXBIT0. H OLT INTEGRATED CIRCUITS 19 AR R X 27 AR CR X 26 AR CR X 25 AR CR X 24 AR CR X 23 AR CR X 22 AR CR XC 21 R 20 5 4 3 2 1 0 LSB AR XC X AR CR X 17 AR CR X 16 AR CR X 15 AR CR X 14 AR CR X 13 AR CR X 12 AR CR XC 11 R 10 AR AR X AR BIT X7 AR BIT X6 AR BIT X5 AR BIT X4 AR BIT X3 AR BIT X2 AR BIT XB 1 IT 0 5 4 3 2 1 0 LSB 5 4 3 2 1 0 LSB HI-3210 ARINC 429 TRANSMIT OPERATION The HI-3210 has four on-board ARINC 429 transmit channels which directly drive ARINC 429 differential line drivers such as the Holt HI-8596. ARINC 429 words may be written to the transmitters either directly, using an SPI instruction, or be generated automatically using the four ARINC 429 message schedulers. ARINC 429 Transmit Channel Configuration Each of the four available ARINC 429 Transmit channels is configured using its own register. Register address 0x8018 controls ARINC 429 Transmit channel #0, register address 0x8019 controls channel #1 and so on. The ATXCn registers may be written or read at any time. N / I / ST LO OP PA R EV ITY E /D SK N / AT IP OD A D H X 76 MSB 5 4 3 2 X 1 R U ARINC 429 TX CONTROL REGISTER 0 - 3 (Address 0x8018 - 0x801B) X 0 LSB Bit Name 7 RUN / STOP R/W R/W Default Description 0 When zero, transmission from this ARINC 429 transmit channel is suspended after the currently transmitting label is sent. When this bit is taken high, transmission starts at the beginning of the descriptor table for this channel. Selects the transmission rate for the ARINC 429 transmit channel. A “0” selects high-speed (100Kb/s) and a “1” selects low-speed (12.5Kb/s). When this bit is a one, the 32nd transmitted ARINC bit is overwritten with a parity flag. When this bit is a zero, all 32-bits are transmitted as data. When PARITY / DATA is a “1”, this bit defines whether th 32nd transmitted bit is set for Even or Odd Parity. A “1” selects even parity and a “0” selects odd parity. When set a “1’ instructs the transmit sequencer to wait for the next Repetition Rate Counter rollover before beginning a new transmission cycle. A “0” causes an immediate restart of the cycle following completion of the prior cycle. Not Used Not Used Not Used 6 5 4 3 HI / LO R/W 0 0 0 0 PARITY / DATA R/W EVEN / ODD SKIP R/W R/W 2 1 0 - R/W R/W R/W 0 0 0 HOLT INTEGRATED CIRCUITS 20 HI-3210 ARINC 429 Transmit Scheduler Each of the four ARINC 429 transmit channels has its own transmit controller. The controller is userprogrammed to output ARINC labels in a predefined order and repetition rate. A sequence of up to 256 ARINC labels may be transmitted before repeating the sequence. A descriptor table with up to 256 entries (descriptors) is compiled by the user to define the sequence of ARINC 429 messages transmitted on each channel. When the RUN/STOP bit in the ARINC TX Control Register is asserted, the controller compiles the first 32-bit ARINC word from the instructions given by the first descriptor and then transmits it. A Transmit Sequence Pointer then increments to the next descriptor in the table and the process is repeated for Descriptor number 2. ARINC 429 messages continue to be compiled and transmitted until the last descriptor in the table. The end of the table is marked by a special descriptor if not all 256 entries are needed. The Sequence Pointer is then reset to zero. A Repetition Rate Counter is used to time the start of the next transmission cycle. The user is responsible for construction of the descriptor table and for setting the Repetition Rate prior to asserting RUN/STOP. Facilities exist for immediate cycle repetition and for single-cycle operation. The byte content of each ARINC 429 message transmitted is user defined by the descriptor contents. Data bytes may be sourced from the host CPU / autoinitialization EEPROM (immediate data) or from the ARINC 429 receive memory (ARINC indexed). This allows received ARINC data to be re-transmitted on another bus with or without filtering, label byte reassignment or data modification. It also allows data from multiple ARINC 429 receive buses to be re-packetized into new ARINC 429 transmitted messages. Conditional transmission control allows sequenced words to be skipped if no new data is available. Each ARINC 429 transmit channel is independently configured with its own ARINC 429 TX Control Register, ATXCR0-3, as previously described. ARINC 429 Transmit Descriptor table Repetion Rate Register 0x47FF 0x47F8 0x47F0 Sequence 255 Descriptor Frame Sequence 254 Descriptor Frame Repetition rate counter Value Byte 4 0x4028 0x4020 (Memory Addresses shown for ARINC Tx channel 0) 0x4018 0x4010 0x4008 Sequence pointer 000 Sequence 5 Descriptor Frame Sequence 4 Descriptor Frame Sequence 3 Descriptor Frame Sequence 2 Descriptor Frame Sequence 1 Descriptor Frame Sequence 0 Descriptor Frame Action Byte 4 Value Byte 3 Action Byte 3 Value Byte 2 Action Byte 2 Value Byte 1 Action Byte 1 0x4000 The value of each ARINC 429 label transmitted in the sequence is defined by its eight-byte descriptor. The descriptor consists of one “Action byte” and one “Value” byte for each of the four bytes that make up the ARINC 429 transmitted label. The four pairs of Action and Value bytes describe where the data for each byte may be found. Different op-codes allow the data source to be host CPU populated fixed values, or values from specific locations within the ARINC 429 receive memory. Action byte 1 also has one additional op-code to facilitate sequence flow control. The construction of Action and Value bytes are described in the next section. HOLT INTEGRATED CIRCUITS 21 HI-3210 Current Sequence number TRANSMIT SEQUENCE POINTERS 0 -3 (Address 0x802C - 0x802F) 76 MSB 5 4 3 2 1 0 LSB The transmit sequence pointer is set to zero on Master Reset. Once the Control Register RUN / STOP bit goes high, sequence execution begins at sequence count zero. After the first word is sent, the pointer is incremented by one descriptor (counts descriptor frames). This continues until the programmed sequence is complete. The sequence pointer is then reset to the beginning of the descriptor table and program execution begins as soon the channel repetition rate counter time elapses. Channel Repetition Period REPETITION RATE REGISTER (Address 0x801C - 0x801F) 76 MSB 5 4 3 2 1 0 LSB The Repetition rate register value defines the time interval between successive starts of the programmed transmit sequence for each ARINC 429 transmit channel. The value is set in binary, with the LSB representing 10 ms. Repetition rate time periods may therefore be set from 0 ms to 2.55 seconds If the repetition rate is shorter than the minimum time needed to transmit all ARINC 429 words in the sequence (but not zero), the transmit sequence will begin again immediately if the Control Register SKIP bit is a zero. If the SKIP bit is a one, the sequencer will wait until the next rollover of the Repetition Rate Counter before starting a new cycle. When the Repetition Rate counter is programmed to zero (default), the transmit sequence shall execute one time only. A zero - to - one transition of the RUN/STOP bit will cause the transmit sequence to start. One-time execution of the sequencer is useful when transmitting ARINC 429 words directly from the host CPU. One or more immediate-mode descriptors can be written into the sequence table, transmitted, and then refreshed for the next cycle. HOLT INTEGRATED CIRCUITS 22 HI-3210 Op-Code Index Value ARINC 429 BYTE 1 DESCRIPTOR 76 MSB 5 4 3 2 1 0 LSB 76 MSB 5 4 3 2 1 0 LSB ACTION BYTE VALUE BYTE Op-Code Index Value Description 000 XXXXX XXXXXXXX End of sequence. When op-code 000 is encountered by the sequencer before it reaches sequence number 255, the sequencer resets to zero and begins the next transmission cycle starting at descriptor number 0 as soon as the repitition rate counter rolls over. Note that the descriptor table is cleared following Master Reset, so no ARINC 429 transmissions are possible until the sequence table has been configured. No-operation. This descriptor is ignored and the sequencer increments to the next descriptor in the sequence. This opcode may be used to temporarily suspend transmission of a particular message in the sequence, without having to modify the remaining bit fields of the descriptor or reloading the entire descriptor block in order to delete the entry. Immediate data. The value contained in the descriptor value data byte is loaded into byte 1 (the ARINC 429 “label” byte) of the ARINC 429 label to be transmitted. Immediate data conditional. The NEWTXn bit corresponding to the ARINC Data RAM location defined by channel “CCC” and label block “LLLLLLLL” is read. LLLLLLLL is used as Byte 1 if NEWTXn is set for this or any other conditional opcode within this descriptor frame. If NEWTXn = 0 for all conditional op codes (within this descriptor frame) then no transmission occurs for this frame and the sequencer increments to the next descriptor frame. The NEWTXn bit for the referenced ARINC RAM block is reset. Indexed data. The value of ARINC Data RAM location defined by channel “CCC”, label block “LLLLLLLL” and byte number “BB” is loaded into byte 1 of the ARINC 429 label to be transmitted. Indexed data conditional. The NEWTXn bit corresponding to the ARINC Data RAM location defined by channel “CCC”, label block “LLLLLLLL” and byte number “BB” is read. The corresponding byte is used as Byte 1 if NEWTXn is set for this or any other conditional opcode within this descriptor frame. If NEWTXn = 0 for all conditional op codes (within this descriptor frame) then no transmission occurs for this frame and the sequencer increments to the next descriptor frame. The NEWTXn bit for the referenced ARINC RAM block is reset. Reserved. Do not use. Reserved. Do not use. 001 XXXXX XXXXXXXX 010 XXXXX LLLLLLLL 011 CCCXX LLLLLLLL 100 CCCBB LLLLLLLL 101 CCCBB LLLLLLLL 110 111 XXXX XXXX XXXXXXXX XXXXXXXX HOLT INTEGRATED CIRCUITS 23 HI-3210 Op-Code Index Value ARINC 429 BYTES 2 - 4 DESCRIPTOR 76 MSB 5 4 3 2 1 0 LSB 76 MSB 5 4 3 2 1 0 LSB ACTION BYTE VALUE BYTE Op-Code Index Value Description 000 001 010 XXXXX XXXXX XXXXX XXXXXXXX XXXXXXXX LLLLLLLL No-Op op-code. ARINC 429 word construction will be terminated and the sequencer will move on to the next descriptor in the table. No-Op op-code. ARINC 429 word construction will be terminated and the sequencer will move on to the next descriptor in the table. Immediate data. The value contained in the descriptor value data byte is loaded into this byte position of the ARINC 429 32-bit message to be transmitted. Immediate data conditional. The NEWTXn bit corresponding to the ARINC Data RAM location defined by channel “CCC” and label block “LLLLLLLL” is read. LLLLLLLL is used if NEWTXn is set for this or any other conditional opcode within this descriptor frame. If NEWTXn = 0 for all conditional op codes (within this descriptor frame) then no transmission occurs for this frame and the sequencer increments to the next descriptor frame. The NEWTXn bit for the referenced ARINC RAM block is reset. Indexed data. The value of ARINC Data RAM location defined by channel “CCC”, label block “LLLLLLLL” and byte number “BB” is loaded into this byte position of the ARINC 429 label to be transmitted. Indexed data conditional. The NEWTXn bit corresponding to the ARINC Data RAM location defined by channel “CCC”, label block “LLLLLLLL” and byte number “BB” is read. The corresponding byte is used if NEWTXn is set for this or any other conditional opcode within this descriptor frame. If NEWTXn = 0 for all conditional op codes (within this descriptor frame) then no transmission occurs for this frame and the sequencer increments to the next descriptor frame. The NEWTXn bit for the referenced ARINC RAM block is reset. Reserved. Do not use. Reserved. Do not use. 011 CCCXX LLLLLLLL 100 CCCBB LLLLLLLL 101 CCCBB LLLLLLLL 110 111 XXXX XXXX XXXXXXXX XXXXXXXX HOLT INTEGRATED CIRCUITS 24 HI-3210 ARINC 429 Immediate Transmit Option The Host CPU may instruct the HI-3210 to transmit an ARINC 429 message immediately using a special SPI command. The SPI command selects the transmit channel and provides the four bytes of data to be sent as a 32-bit ARINC 429 message. If the transmit channel’s sequencer is not running (ATCR bit RUN/STOP = “0”), or the sequencer is waiting for the repetition rate counter to rollover, then the new ARINC 429 message is transmitted without delay. If the transmit sequencer for the selected channel is active, then the new message is transmitted as soon as the current message has been sent. The sequencer then resumes operation at the next location in the queue. Both the RUN input and the Master Control Register A429TX bit must be high to enable any ARINC 429 transmission. Table 1 lists the host CPU SPI instruction format. HOLT INTEGRATED CIRCUITS 25 HI-3210 RESET AND START-UP OPERATION After power-on, the HI-3210 is in an undefined state. The RESET pin must be taken high to begin device initialization. The RESET pin may be asserted at any time. Taking RESET high immediately stops all execution and sets the READY output low indicating that the part is in the reset state. On the falling edge of RESET, the HI-3210 samples the state of the MODE2-0 input pins. This is the only occasion these inputs are sampled. The state of the MODE pins determines one of six possible initialization sequences as shown in the following diagram. These six initialization modes allow the user to customize the startup configuration of the device. Once the initialization is complete, the device enters the Idle State when the ready pin goes high. In Idle State, the host CPU may communicate with the HI-3210 memory and registers using the host CPU SPI link. When in the Idle State, the HI-3210 does not transmit or receive any messages on any of the ARINC 429 buses. To begin data bus operation, the user must transition the RUN input from a low to high state. Immediately following the rising edge of RUN, the part enters the Active State and bus message processing begins. During initialization, various device configuration tasks are performed according to the Mode selection set at the MODE2:0 input pins. The available options are: 3. Initialize Registers and Clear all memory In addition to clearing data memory (0x0000 to 0x33FF), Modes 0, 1, 2, and 3 also clear all configuration and lookup tables (0x3400 to 0x7FFF) as well as setting all registers (0x8000 to 0x807F) to their default states. All registers default to zero unless otherwise noted. 4. Auto-Initialize from EEPROM The contents of the Auto-Initialization EEPROM are copied into the HI-3210 memory and registers via the EEPROM SPI interface. The part verifies the integrity of the data transfer from the EEPROM by running through a byte-by-byte compare routine and a checksum validation. If a compare error is detected, the AUTOERR bit is set in the Pending Interrupt Register, the MINT output is asserted, the location of the error is captured in the AUTO-INIT FAIL ADDRESS registers 0x8073 (Auto-Init Fail LS address) and 0x8074 (Auto-Init Fail MS address) and the part enters the Safe state. If a checksum error is detected, the CHKERR bit is set in the Pending Interrupt Register, the MINT output is asserted and the part enters the Safe state. The AUTOERR and the CHKERR interrupts are not maskable. Once initialization is complete, the part enters the Idle state. The host CPU may read and write HI-3210 internal memory and registers in all Modes. If not using the autoinitizarion feature, the host CPU should configure the device at this time. NOTE: Modes 6 and 7 are reserved and should not be used. 1. RAM Integrity Check In Modes 2 and 3, the HI-3210 performs a RAM integrity check. A read/write check is performed on the entire RAM space. An incrementing pattern is written to sequential RAM locations then this pattern is read and verified. Each RAM location is re-written with the 1s complement of its current contents then this pattern is read and verified. The incrementing pattern followed by its 1s complement ensures that each RAM location can store both a 1 and 0 state. If the RAM integrity check fails, the MINT pin is asserted and the Pending Interrupt Register RAMFAIL bit is set. The part enters the “Safe” state, in which the HI-3210 is able to accept and respond to Host CPU SPI Instructions, but cannot enter Normal Operating mode until the RESET input is taken high to repeat the initialization sequence. The RAMFAIL Interrupt is not maskable. 2. Clear Data Memory In Modes 0, 1, 2, 3 and 5, the HI-3210 automatically clears all memory locations in the address range 0x0000 to 0x33FF. This is the space reserved for ARINC 429 message data. Configuration tables and HI-3210 registers are not affected. HOLT INTEGRATED CIRCUITS 26 HI-3210 Reset and Start-up Operation RESET driven to “1” Stop execution, READY => 0 RESET STATE RESET driven to “0” Sample MODE2:0 inputs MODE 0 Perform RAM Integrity Check Clear data memory (0x0000 - 0x33FF) Initialize Registers and Clear Configuration Tables (0x3400 - 0xFFFF) Auto-Initialize from EEPROM No Yes Yes MODE 1 No Yes Yes MODE 2 Yes Yes Yes MODE 3 Yes Yes Yes MODE 4 No No No MODE 5 No Yes No MODE 6 RESERVED RESERVED RESERVED MODE 7 RESERVED RESERVED RESERVED No Yes No Yes No No RESERVED RESERVED RAM Pass ? Yes No Set RAMFAIL INT = 1 Copy OK ? Yes READY => 1 No Set AUTOERROR INT = 1 IDLE STATE SAFE STATE RUN driven 0 - 1 ACTIVE STATE HOLT INTEGRATED CIRCUITS 27 HI-3210 INTERRUPT HANDLING The HI-3210 includes a simple, user-selectable Interrupt Handler. Two types of Interrupt are possible - Message Event Driven (ARINC 429 Bus), and Fault Driven. Fault Interrupts There are four fault Interrupt bits in the PIR. Fault Interrupts are not maskable, and their Interrupt Mask bits are fixed at a “1”. COPYERR is set when the HI-3210 detects a mismatch between RAM and EEPROM after attempting to program the Auto-initialization EEPROM. AUTOERR is set when the Auto-Initialization EEPROM read verification cycle detects a mismatch between the on-chip memory and EEPROM following autoinitialization. CHKERR is set when an auto-initialization checksum error is detected. The RAMFAIL bit is set if the Built-In Self Test sequence fails. ARINC 429 Receive Interrupts As described earlier, the user can elect to generate an interrupt upon receipt of an ARINC 429 message on any combination of the eight available channels and for any of the possible 256 label byte (ARINC message bits 1-8) values. Interrupts are enabled when the ARINC 429 Rx Interrupt look-up bit is a “1”. When a message arrives that is flagged to generate an Interrupt, that channel’s bit is set in the ARINC 429 Receiver Pending Interrupt Register APIR. The ARINC 429 Interrupt Address Register (AIAR) for that channel is updated with the ARINC 429 8-bit label value. For example, if ARINC Receive channel 7 is enabled for Interrupts when messages with ARINC label 0xD4 arrive, then on receipt of such a message, APIR bit 7 is set to a “1” and the value 0xD4 is written to AIAR7. If the corresponding bit in the ARINC 429 Receive Interrupt Mask Register is a “1” the AINT interrupt output will go high and stay high until the AACK input pin is driven high. Driving AACK high, causes the AINT pin to return to zero. A special Indexed SPI read instruction is available to allow the host to efficiently retrieve ARINC 429 messages which have Interrupts Enabled (see SPI instruction set section). Note that if AACK is tied high permanently, the AINT pin will go high for approximately 1 us before returning to zero. A host CPU read of the APIR register reads the current value and resets APIR to 0x00. HOLT INTEGRATED CIRCUITS 28 HI-3210 PENDING INTERRUPT REGISTER (Address 0x800A) Bit Name 7 6 5 4 3 2 1 0 COPYERR AUTOERR CHKERR RAMFAIL FLAG ATXRDY R/W R/W R/W R/W R/W R/W R/W R/W R/W Default Description 0 0 0 0 0 0 0 0 O P AU YE TO RR CE HR KR BI ER ST R FL FA AG IL AT XR D Y C X 76 MSB 5 4 3 2 1 X 0 LSB EE copy error. RAM - EEPROM mismatch Auto-inititailization RAM read error Auto-initialization checksum fail Power-On Reset RAM Integrity Check fail Logical OR of ARINC 429 Receive FIFO FLAG signals ARINC 429 Host TX ready. Used with Host SPI op-code 100101TT (see Table 1). Interrupt when ready for next 32-bit word from host Not Used Not Used INTERRUPT REGISTER MASK REGISTER (Address 0x8034) AU E T RR C OE HR KR BI ER ST R FL FA AG IL AT XR D Y X X 0 LSB 5 4 3 2 1 76 MSB Bit Name 7 6 5 4 3 2 1 0 COPYERR AUTOERR CHKERR RAMFAIL FLAG ATXRDY - R/W R R R R R/W R/W R/W R/W Default Description 1 1 1 1 0 0 0 0 COPYERR is not maskable AUTOERR is not maskable CHKERR is not maskable RAMFAIL is not maskable INT is asserted if this bit is a “1” and the PIR FLAG bit is set INT is asserted if this bit is a “1” and the PIR ATXRDY bit is set Not Used Not Used HOLT INTEGRATED CIRCUITS 29 C O PY HI-3210 RAM BUILT-IN SELF-TEST The HI-3210 offers a built-in self-test (BIST) feature which can be used to check RAM integrity. The BIST Control/Status Register is used to control the BIST function. All tests are destructive, overwriting data present before test commencement. BIST CONTROL/STATUS REGISTER (Address 0x8070) 76 MSB This register controls RAM built-in self-test. Bits 0,1 are Read Only. The remaining bits in this register are Read-Write but can be written only in MODE2:0 = 0x04. BIST Control Register bits provide a means for the host to perform RAM self-test at other times. Register bits 6:4 select RAM test type. Then bit 3 starts the selected RAM test, and bits 1:0 report a fail/pass result after test completion. Bit No. 7 6:4 Mnemonic Interrupt Type RBFFAIL RAM BIST Force Failure. When this bit is asserted, RAM test failure is forced to verify that RAM BIST logic is functional. RBSEL2-0 RAM BIST Select Bits 2-0. This 3-bit field selects the RAM BIST test mode applied when the RBSTART bit is set: RBSEL2:0 000 001 010 011 100 101 110 111 SELECTED RAM TEST Idle Pattern Test, described below Write 0x00 to RAM address range 0x0000 - 0x7FFF Read and verify 0x00 over RAM address range 0x0000 - 0x7FFF Write 0xFF to RAM address range 0x0000 - 0x7FFF Read and verify 0xFF over RAM address range 0x0000 - 0x7FFF Inc / Dec Test performs only steps 5 - 8 of the Pattern Test below Idle Description of the RAM BIST “PATTERN” test selected when register bits RBSEL2:0 = 001: 1. Write 0x00 to all RAM locations, 0x0000 through 0x7FFF 2. Repeat the following sequence for each RAM location from 0x0000 through 0x7FFF: a. Read and verify 0x00 b. Write then read and verify 0x55 c. Write then read and verify 0xAA d. Write then read and verify 0x33 e. Write then read and verify 0xCC f. Write then read and verify 0x0F g. Write then read and verify 0xF0 h. Write then read and verify 0x00 I. Write then read and verify 0xFF j. Write 0x00 then increment RAM address and go to step (a) 3. Write 0xFF to all RAM locations, 0x0000 through 0x7FFF 4. Repeat the following sequence for each RAM location from 0x0000 through 0x7FFF: a. Read and verify 0xFF b. Write then read and verify 0x55 c. Write then read and verify 0xAA d. Write then read and verify 0x33 e. Write then read and verify 0xCC H OLT INTEGRATED CIRCUITS 30 BF R AIL BS R EL BS 2 R EL BS 1 R EL BS 0 TA RT R BF R AIL BP AS S R X 5 4 3 2 1 0 LSB HI-3210 f. g. h. I. j. 5. 6. 7. 8. 3 RBSTRT Write then read and verify 0x0F Write then read and verify 0xF0 Write then read and verify 0x00 Write then read and verify 0xFF Write 0xFF then increment RAM address and go to step (a) Write an incrementing pattern into sequential RAM locations from 0x0000 to 0x7FFF Read each memory location from 0x0000 to 0x7FFF and verify the contents Write 1s complement of each cell’s current contents, into each RAM location (same addr range) Read each memory location and verify the contents RAM BIST Start. Writing logic 1 to this bit initiates the RAM BIST test selected by register bits RBSEL2:0. The RBSTRT bit can only be set in MODE2:0 = 0x04. This bit is automatically cleared upon test completion. Register bits 1:0 indicate fail / pass test result. Not Used. RAM BIST Fail. Device logic asserts this bit when failure occurs while performing the selected RAM test. This bit is automatically cleared when RBSTRT bit 3 is set. When BIST failure occurs, a clue to the failing RAM address can be read at register addresses 0x8071 and 0x8072. For speed, the RAM BIST concurrently tests four consecutive RAM addresses in parallel. If a test failure occurs, register addresses 0x8071 and 0x8072 can be used to determine the four RAM addresses tested. RAM BIST Pass. Device logic asserts this bit when the selected RAM test completes without error. This bit is automatically cleared when RBSTRT bit 3 is set. 2 1 --------RBFAIL 0 RBPASS BISTFL LOWER BIST FAIL ADDRESS REGISTER (Address 0x8071) 76 MSB 5 4 3 2 1 0 LSB BISTFH UPPER BIST FAIL ADDRESS REGISTER (Address 0x8072) X X 15 14 13 12 11 10 9 8 LSB MSB H OLT INTEGRATED CIRCUITS 31 HI-3210 HOST SERIAL PERIPHERAL INTERFACE In the HI-3210, internal RAM and registers occupy a (32K + 128) x 8 address space. The lowest 32K addresses access RAM locations and the remaining addresses access registers. Timing is identical for register operations and RAM operations via the serial peripheral interface, and read and write operations have likewise identical timing. Host access is only allowed when the part is READY or in SAFE mode. NOTE: writes will be blocked and reads will return the Master Status Register value until either of these modes occur. SCK, and output data for each device changes on the falling edge. These are known as SPI Mode 0 (CPHA = 0, CPOL = 0) and SPI Mode 3 (CPHA = 1, CPOL = 1). Be sure to set the host SPI logic for one of these modes. As seen in Figure 1, the difference between SPI Modes 0 and 3 is the idle state for the SCK signal. There is no configuration setting in the HI-3210 to select SPI Mode 0 or Mode 3 because compatibility is automatic. Beyond this point, the HI-3210 data sheet only shows the SPI Mode 0 SCK signal in timing diagrams. The SPI protocol transfers serial data as 8-bit bytes. Once CS chip select is asserted, the next 8 rising edges on SCK latch input data into the master and slave devices, starting with each byte’s most-significant bit. The HI-3210 SPI can be clocked at 20 MHz. Multiple bytes may be transferred when the host holds CS low after the first byte transferred, and continues to clock SCK in multiples of 8 clocks. A rising edge on CS chip select terminates the serial transfer and reinitializes the HI-3210 SPI for the next transfer. If CS goes high before a full byte is clocked by SCK, the incomplete byte clocked into the device SI pin is discarded. In the general case, both master and slave simultaneously send and receive serial data (full duplex) as shown in Figure 1 below. When the HI-3210 is sending data on SO during read operations, activity on its SI input is ignored. Figures 2 and 3 show actual behavior for the HI-3210 SO output. Serial Peripheral Interface (SPI) Basics The HI-3210 uses an SPI synchronous serial interface for host access to registers and RAM. Host serial communication is enabled through the Chip Select (CS) pin, and is accessed via a three-wire interface consisting of Serial Data Input (SI) from the host, Serial Data Output (SO) to the host and Serial Clock (SCK). All programming cycles are completely self-timed, and no erase cycle is required before write. The SPI (Serial Peripheral Interface) protocol specifies master and slave operation; the HI-3210 Host CPU interface operates as an SPI slave. The SPI protocol defines two parameters, CPOL (clock polarity) and CPHA (clock phase). The possible CPOLCPHA combinations define four possible "SPI Modes." Without describing details of the SPI modes, the HI-3210 operates in the two modes where input data for each device ( master and slave) is clocked on the rising edge of SCK (SPI Mode 0) 0 1 2 3 4 5 6 7 SCK (SPI Mode 3) 0 1 2 3 4 5 6 7 SI MSB LSB SO High Z MSB LSB High Z CS FIGURE 1. Generalized Single-Byte Transfer Using SPI Protocol, SCK is Shown for SPI Modes 0 and 3 HOLT INTEGRATED CIRCUITS 32 HI-3210 0 SCK SPI Mode 0 MSB 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 LSB SI Command Byte SO High Z Data Byte CS Host may continue to assert CS here to read sequential byte(s) when allowed by the instruction. Each byte needs 8 SCK clocks. MSB LSB MSB High Z FIGURE 2. Single-Byte Read From RAM or a Register 0 SCK SPI Mode 0 MSB 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 LSB MSB LSB MSB LSB SI Command Byte SO High Z Data Byte 0 Data Byte 1 CS Host may continue to assert CS here to write sequential byte(s) when allowed by the SPI instruction. Each byte needs 8 SCK clocks. FIGURE 3. 2-Byte Write To RAM or a Register Pair HOLT INTEGRATED CIRCUITS 33 HI-3210 HI-3210 SPI COMMANDS For the HI-3210, each SPI read or write operation begins with an 8-bit command byte transferred from the host to the device after assertion of CS. Since HI-3210 command byte reception is half-duplex, the host discards the dummy byte it receives while serially transmitting the command byte. Note: When the primary or fast-access address pointer is used for auto-incrementing multi-word read/write and reaches the top of the memory address range (0x7FFF), or the top of the register address range (0xFFFF) attempts to read further bytes will result the terminal address (0x7FFF or 0xFFFF) being output again. The host should avoid this situation. Two single-byte SPI commands use the current address pointer value in MAP without first loading or otherwise modifying it: Command 0x80 Command 0x84 Read Operation read location addressed by pointer value Write Operation write location addressed by pointer value Fast Access Commands for Registers 0-15 The SPI command set includes directly-addressed read and write commands for registers 0 through 15 (Memory Address 0x8000 to 0x800F). The 8-bit pattern for these commands has the general form 0-W-R-R-R-R-0-0 where RRRR is the 4-bit register number, and W signifies Write when 1, or Read when 0. Figures 2 and 3 show read and write timing as it appears for fast-access register operations. The command byte is immediately followed by a data byte comprising the 8-bit data word read or written. For a single register read or write, CS is negated after the data byte is transferred. Multiple register read or write cycles may be performed by transferring more than one byte before CS is negated. Multiple register access occur in address order starting with the register specified in the SPI instruction. Note: Register locations not shown in table 1 are “reserved” and cannot be written using any SPI command. Further, these register addresses will not provide meaningful data in response to read commands. Either of these commands can be used to read or write a single location, or may be used when starting a multi-byte read or write by using the pointer’s auto-increment feature. Special Purpose Commands Several other HI-3210 SPI commands load or otherwise modify the memory address pointer before initiating a read or write process. These commands are designed to allow speedy access to messages received on the ARINC 429 buses. Using a single-byte SPI command, the address pointer can be directly loaded with the memory address for the last received ARINC 429 message which triggered an interrupt. Op Code 110RRR00 The HI-3210 will retrieve the current ARINC Receive Interrupt Vector for a given channel (RRR), calculate the memory address for the first word of the corresponding receive memory data block and write it to the Memory Address pointer (MAP). Read the location addressed by the new pointer value. This command can be used to read just the most recent ARINC 429 Receive Status Byte, or may be used to start a four-byte read because memory pointer auto-increment occurs after the Status Byte is read. Op Code 111RRR00 The HI-3210 will retrieve the current ARINC Receive Interrupt Vector for a given channel (RRR), calculate the memory address for the first word of the corresponding receive memory data block and write it to the Memory Address Pointer (MAP). Output the value of the Receive Interrupt Vector (ARINC 429 label byte). This command can be used to read just the most recent ARINC 429 label value received, or may be used to start a four-byte read to output the entire four-byte ARINC RAM and Register Indirect Addressing Refer to the HI-3210 SPI command set shown in Table 1. SPI commands other than fast-access use an address pointer to indicate the address for read or write transactions. This sixteen-bit memory address pointer (MAP) must be initialized before any non-fast-access read or write operation. Two dedicated SPI instructions are used to write and read the MAP. SPI Instruction 0x8C followed by two data bytes is used to write MAP. SPI instruction 0x88 reads two data bytes from MAP. The first byte is the most significant eight bytes of the address. For example, SPI sequence 0x8C, 0x12, 0x34 write the value 0x1234 into the MAP. Two SPI instructions read and write data bytes to memory or registers using the MAP as an address pointer. Single or multi-byte reads and writes may be performed. MAP is incremented after each byte access. Two command bytes cannot be “chained”; CS must be negated after the command, then reasserted for the following Read or Write command. HOLT INTEGRATED CIRCUITS 34 HI-3210 message, because memory pointer auto-increment occurs after the label byte is output. Op Code 100101TT Writes an ARINC 429 message to ARINC 429 transmit scheduler TT for immediate transmission, where TT represents the channel number. TABLE 1. DEFINED INSTRUCTIONS OP CODE Binary OP CODE Hex Auto Increment Number of Data Bytes DESCRIPTION 00RRRR00 0x00 - 0x3C 01RRRR00 0x40 - 0x7C 10000000 0x80 10000100 0x84 10001000 0x88 10001100 0x8C 100101TT 0x94 - 0x97 101RRR00 0xA0 - 0xBC 110RRR00 0xC0 - 0xDC 111RRR00 0xE0 - 0xFC Yes Yes Yes Yes No No No Yes No No 1++ 1++ 1++ 1++ 2 2 4 4, 8, 12... 4 4 Fast Register Read from register RRRR Fast Register Write to register RRRR Read memory at address MAP Write memory at address MAP Read MAP Write MAP Transmit ARINC 429 message on transmit bus TT Read ARINC 429 FIFO # RRR. Reads exactly four bytes Read ARINC block at receive channel RRR, label Read ARINC message at receive channel RRR, label FAST-ACCESS SPI COMMANDS FOR REGISTERS 0-15 Command Bits 5:2 Convey the 4-Bit Register Address COMMAND BITS 76543210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HEX BYTE 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C FAST-ACCESS READ Read APIR Read AIAR0 Read AIAR1 Read AIAR2 Read AIAR3 Read AIAR4 Read AIAR5 Read AIAR6 Read AIAR7 Reserved Read PIR Reserved Read AMFF Read ATRB Read MSR Read MCR COMMAND BITS 76543210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HEX BYTE 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C FAST-ACCESS WRITE N/A (Read only) N/A (Read only) N/A (Read only) N/A (Read only) N/A (Read only) N/A (Read only) N/A (Read only) N/A (Read only) N/A (Read only) Reserved N/A (Read only) Reserved N/A (Read only) N/A (Read only) N/A (Read only) Write MCR HOLT INTEGRATED CIRCUITS 35 HI-3210 PROGRAMMING THE AUTO-INITIALIZATION EEPROM. Following reset, the HI-3210 may be completely configured by automatically copying the contents of an external EEPROM into HI-3210 memory and registers. An SPI enabled 64KByte EEPROM is used for this purpose. The EEPROM memory space is mapped to the HI-3210 as shown in the diagram below. All configuration memory blocks are copied. The ARINC 429 Received Data Memory contents and ARINC 429 Receive log FIFO contents are not copied to or from the EEPROM. The HI-3210 can be used to program the Auto-Initialization EEPROM. When the HI-3210 is in its IDLE state (RUN input = “0”), a three step sequence must be performed to begin the EEPROM programming cycle: 1. Write data value 0x5A to HI-3210 memory address 0x8FFF. 2. Write data value 0xA5 to HI-3210 memory address 0x8FFF. 3. Apply a positive pulse to the PROG input pin of at least 1ms. 0x8XXX If the three-step sequence is interrupted by any intervening host activity between steps 1 and 2, or 2 and 3, or if the PROG pulse is less than 1 ms, the programming cycle will not start and the device remains in the IDLE state. Taking the PROG pin low initiates the cycle. The READY pin goes low, and the contents of the HI-3210 memory and registers are copied to the EEPROM. When copying is complete, the HI-3210 executes a byte-by-byte comparison of the EEPROM and its own register / memory contents. If the verification completes successfully, the READY pin goes high. A 2’s complement of the checksum is also written to the EEPROM, which is used during the Auto-Initialization sequence validation test. If the comparison of the EEPROM contents and HI-3210 memory / register contents results in a discrepancy, the HI3210 enters the SAFE state, the PROGERR bit is set in the Pending Error Register and the INT output is asserted. The user must clear the PROGERR issue before normal operation can resume. 0x8XXX Configuration Registers 0x8000 0x7FFF Configuration Registers 0x8000 0x7FFF RESERVED 0x7C00 0x7BFF 0x7A00 0x79FF RESERVED 0x7C00 Look-up Tables RESERVED Look-up Tables RESERVED ARINC 429 TX3 Transmit Schedule Table ARINC 429 TX2 Transmit Schedule Table ARINC 429 TX1 Transmit Schedule Table ARINC 429 TX0 Transmit Schedule Table RESERVED 0x7BFF 0x7A00 0x79FF 0x6000 0x5FFF 0x5800 0x57FF 0x5000 0x4FFF 0x4800 0x47FF 0x4000 0x3FFF 0x3400 0x33FF ARINC 429 TX3 Transmit Schedule Table ARINC 429 TX2 Transmit Schedule Table ARINC 429 TX1 Transmit Schedule Table ARINC 429 TX0 Transmit Schedule Table RESERVED 0x6000 0x5FFF 0x5800 0x57FF 0x5000 0x4FFF 0x4800 0x47FF 0x4000 0x3FFF 0x3400 0x3FFF 0x0000 0x0000 HI-3210 Memory HOLT INTEGRATED CIRCUITS 36 EEPROM HI-3210 ABSOLUTE MAXIMUM RATINGS Supply voltage (VDD) Logic input voltage range Power dissipation at 25°C Solder Temperature Junction Temperature Storage Temperature -0.3 V to +5.0 V -0.3 V DC to +3.6 V 1.0 W 275°C for 10 sec. 175°C -65°C to +150°C RECOMMENDED CONDITIONS Operating Supply Voltage X VDD....................................... 3.3 VDC ±5% X Operating Temperature Range X Industrial ......................... -40°C to +85°C Extended ....................... -55°C to +125°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. DC ELECTRICAL CHARACTERISTICS VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER Operating Voltage Supply Current Min. Input Voltage Max. Input Voltage (HI) (LO) SYMBOL VDD IDD VIH VIL IPUD VOH VIH CONDITION MIN 3.15 TYP 3.30 MAX 3.45 50 UNITS V mA VDD Digital inputs Digital inputs Digital inputs and data bus IOUT = -1.0mA, Digital outputs IOUT = 1.0mA, Digital outputs 70% 30% 30 90% 10% VDD µA VDD VDD Pull-Up / Pull-Down Current Min. Output Voltage Max. Output Voltage (HI) (LO) HOLT INTEGRATED CIRCUITS 37 HI-3210 AC ELECTRICAL CHARACTERISTICS VDD = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). LIMITS PARAMETER SPI Host Bus Interface SCK clock period CE set-up time to first SCK rising edge CE hold time after last SCK falling edge CE inactive between SPI instructions SPI SI Data set-up time to SCK rising edge SPI SI Data hold time after SCK rising edge SCK high time SCK low time SO valid after SCK falling edge SO high-impedance after CE inactive tCYC tCES tCEH tCPH tDS tDH tSCKH tSCKL tDV tCHZ 50 25 25 100 10 10 25 25 20 75 ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNITS SERIAL INPUT TIMING DIAGRAM t CPH t CEH CE t CES SCLK t DS SI MSB t DH LSB SERIAL OUTPUT TIMING DIAGRAM t CPH CE t SCKH SCLK t SCKL t CHZ MSB LSB Hi Impedance SO Hi Impedance t DV HOLT INTEGRATED CIRCUITS 38 HI-3210 PIN CONFIGURATION FOR HI-3210, 64-PIN QFN PACKAGE Notes 1 . All VDD and GND pins must be connected. 2. See data sheet page 1 for HI-3210, 64-Pin PQFP Package Configuration. AACK ARXBIT6 AINT ARXBIT7 SCANSHIFT ARX2N ARX3P VDD GND ARX3N ARX4P ARX4N ARX5P ARX5N ARX6P ARX6N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ARX2P ARX1N ARX1P ARX0N ARX0P SCANEN ARXBIT5 READY ESCLK EMOSI ECSB EMISO RUN ARXBIT4 ATXMSK MRST HI-3210PCx 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ARXBIT3 ATXSLP0 ATX0N ATX0P ATX1N ATX1P ATXSLP1 VDD GND ARXBIT2 ATXSLP2 ATX2N ATX2P ATX3N ATX3P ATXSLP3 HOLT INTEGRATED CIRCUITS 39 ARX7P ARX7N MODE0 MODE1 MCLK MODE2 ARXBIT0 VDD GND ARXBIT1 HMISO HSCLK HMOSI HCSB MINT MINTACK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 TOP VIEW HI-3210 ORDERING INFORMATION HI-3210Px x x PART NUMBER Blank F PART NUMBER I T M PART NUMBER PQ PC PACKAGE DESCRIPTION Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free RoHS compliant) TEMPERATURE RANGE -40°C TO +85°C -55°C TO +125°C -55°C TO +125°C PACKAGE DESCRIPTION 64 PIN PLASTIC QUAD FLAT PACK PQFP (64PQTS) 64-PIN PLASTIC CHIP-SCALE PACKAGE QFN (64PCS) FLOW I T M BURN IN No No Yes HOLT INTEGRATED CIRCUITS 40 HI-3210 REVISION HISTORY Document Rev. Date DS3210 New 5/10/11 Description of Change Initial Release. HOLT INTEGRATED CIRCUITS 41 PACKAGE DIMENSIONS 64 PIN PLASTIC QUAD FLAT PACK (PQFP) inches (millimeters) Package Type: 64PQTS .473 (12.00) BSC SQ .394 BSC SQ (10.00) .02 BSC (0.50) .009 ± .002 (0.22 ± .05) .055 ± .002 (1.40 ± .05) .008 R max (0.20) See Detail A .063 max (1.60) .004 ± .002 (0.10 ± .05) .003 R min (0.08) 0° £ Q £ 7° BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) Detail A 64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) The metal heat sink pad on the bottom of the package is electrically isolated from the chip. It can be left floating or connected to VDD or GND inches (millimeters) Package Type: 64PCS .354 BSC (9.00) .281 ± .003 (7.125 ± .075) .0197 BSC (0.50) .354 BSC (9.00) Top View .281 ± .003 (7.125 ± .075) Bottom View .010 typ (0.25) .016 ± .004 (0.40 ± .10) .008 typ (0.20) .039 max (1.00) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 42