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MPC9772FAR2

MPC9772FAR2

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

    LQFP52

  • 描述:

    IC CLOCK GEN 1:12 PLL LV 52-LQFP

  • 数据手册
  • 价格&库存
MPC9772FAR2 数据手册
3.3V 1:12 LVCMOS PLL Clock Generator MPC9772 DATA SHEET PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 The MPC9772 is a 3.3 V compatible, 1:12 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications. MPC9772 Features • • • • • • • • • • • • • • • • 1:12 PLL Based Low-Voltage Clock Generator 3.3 V Power Supply Internal Power-On Reset Generates Cock Signals Up to 240 MHz Maximum Output Skew of 250 ps On-Chip Crystal Oscillator Clock Reference Two LVCMOS PLL Reference Clock Inputs External PLL Feedback Supports Zero-Delay Capability Various Feedback and Output Dividers (See Applications Information Section) Supports Up to Three Individual Generated Output Clock Frequencies Synchronous Output Clock Stop Circuitry for Each Individual Output for Power Down Support Drives Up to 24 Clock Lines Ambient Temperature Range 0C to +70C Pin and Function Compatible To the MPC972 52-Lead Pb-Free Package For drop in replacement use 87972DYI-147 3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR AE SUFFIX 52-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 848D-03 Functional Description The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9772 features an extensive level of frequency programmability between the 12 outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1, and 8:3. The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a nonbinary factor. The MPC9772 also supports the 180 phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals. The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the MPC9772. The MPC9772 has an internal power-on reset. The MPC9772 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50  transmission lines. For series terminated transmission lines, each of the MPC9772 outputs can drive one or two traces giving the devices an effective fanout of 1:24. The device is pin and function compatible to the MPC972 and is packaged in a 52-lead LQFP package. MPC9772 REVISION 8 3/16/16 1 ©2016 Integrated Device Technology, Inc. MPC9772 DATA SHEET QA0 All input resistors have a value of 25k XTAL_IN XTAL_OUT XTAL 1 VCC CCLK0 0 CCLK1 1 CCLK_SEL Bank A Ref 0 VCO 2 0 1 1 0 4, 6, 8, 12 1 4, 6, 8, 10 CLK Stop 4, 6, 8, 10 12, 16, 20 VCC QB0 Bank B SYNC PULSE REF_SEL FB_IN CLK Stop FB Bank C VCC QB2 FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] QC0 CLK Stop 2 2 2 3 FSEL_A[0:1] 0 1 CLK Stop Power-On Reset CLK Stop Clock Stop QC1 QC2 QC3 QFB INV_CLK STOP_DATA STOP_CLK MR/OE QB1 QB3 VCO_SEL PLL_EN VCC QA2 QA3 2, 4, 6, 8 PLL QA1 QSYNC 12 GND QB0 VCC QB1 GND QB2 VCC QB3 FB_IN GND QFB VCC FSEL_FB0 Figure 1. Logic Diagram FSEL_FB1 QSYNC GND QC0 VCC QC1 FSEL_C0 FSEL_C1 QC2 VCC QC3 GND INV_CLK XTAL_IN XTAL_OUT VCC_PLL 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 25 41 24 42 23 43 22 44 21 45 20 46 MPC9772 19 47 18 48 17 49 16 50 15 51 14 52 1 2 3 4 5 6 7 8 9 10 11 12 13 GND MR/OE STOP_CLK STOP_DATA FSEL_FB2 PLL_EN REF_SEL CCLK_SEL CCLK0 CCLK1 FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VCC QA2 GND QA1 VCC QA0 GND VCO_SEL Figure 2. MPC9772 52-Lead Package Pinout (Top View) REVISION 8 3/16/16 2 ©2016 Integrated Device Technology, Inc. MPC9772 DATA SHEET Table 1. Pin Configuration Pin I/O Type Function CCLK0 Input LVCMOS PLL reference clock CCLK1 Input LVCMOS Alternative PLL reference clock XTAL_IN, XTAL_OUT Analog Crystal oscillator interface FB_IN Input LVCMOS PLL feedback signal input, connect to an QFB CCLK_SEL Input LVCMOS LVCMOS clock reference select REF_SEL Input LVCMOS LVCMOS/PECL reference clock select VCO_SEL Input LVCMOS VCO operating frequency select PLL_EN Input LVCMOS PLL enable/PLL bypass mode select MR/OE Input LVCMOS Output enable/disable (high-impedance tristate) and device reset FSEL_A[0:1] Input LVCMOS Frequency divider select for bank A outputs FSEL_B[0:1] Input LVCMOS Frequency divider select for bank B outputs FSEL_C[0:1] Input LVCMOS Frequency divider select for bank C outputs FSEL_FB[0:2] Input LVCMOS Frequency divider select for the QFB output INV_CLK Input LVCMOS Clock phase selection for outputs QC2 and QC3 STOP_CLK Input LVCMOS Clock input for clock stop circuitry STOP_DATA Input LVCMOS Configuration data input for clock stop circuitry QA[0-3] Output LVCMOS Clock outputs (Bank A) QB[0-3] Output LVCMOS Clock outputs (Bank B) QC[0-3] Output LVCMOS Clock outputs (Bank C) QFB Output LVCMOS PLL feedback output. Connect to FB_IN. QSYNC Output LVCMOS Synchronization pulse output GND Supply Ground VCC_PLL Supply VCC PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation REVISION 8 3/16/16 Negative power supply 3 ©2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9772 DATA SHEET Table 2. Function Table (Configuration Controls) Control Default 0 1 REF_SEL 1 Selects CCLKx as the PLL reference clock Selects the crystal oscillator as the PLL reference clock CCLK_SEL 1 Selects CCLK0 Selects CCLK1 VCO_SEL 1 Selects VCO2. The VCO frequency is scaled by a factor of 2 (low VCO Selects VCO1. (high VCO frequency range) frequency range). PLL_EN 1 Test mode with the PLL bypassed. The reference clock is substituted for the Normal operation mode with PLL enabled. internal VCO output. MPC9772 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. INV_CLK 1 QC2 and QC3 are in phase with QC0 and QC1 MR/OE 1 Outputs disabled (high-impedance state) and device is reset. During Outputs enabled (active) reset/output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC9772 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal poweron reset (POR) circuitry during power-up. QC2 and QC3 are inverted (180 phase shift) with respect to QC0 and QC1 VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency ratios. See Table 3 to Table 6 and the Applications Information for supported frequency ranges and output to input frequency ratios. Table 3. Output Divider Bank A (NA) VCO_SEL FSEL_A1 FSEL_A0 0 0 0 QA[0:3] VCO8 0 0 1 VCO12 0 1 0 VCO16 0 1 1 VCO24 1 0 0 VCO4 1 0 1 VCO6 1 1 0 VCO8 1 1 1 VCO12 VCO_SEL FSEL_B1 FSEL_B0 QB[0:3] 0 0 0 VCO8 0 0 1 VCO12 0 1 0 VCO16 0 1 1 VCO20 1 0 0 VCO4 1 0 1 VCO6 1 1 0 VCO8 1 1 1 VCO10 VCO_SEL FSEL_C1 FSEL_C0 QC[0:3] 0 0 0 VCO4 0 0 1 VCO8 0 1 0 VCO12 0 1 1 VCO16 1 0 0 VCO2 Table 4. Output Divider Bank B (NB) Table 5. Output Divider Bank C (NC) REVISION 8 3/16/16 4 ©2016 Integrated Device Technology, Inc. MPC9772 DATA SHEET Table 5. Output Divider Bank C (NC) VCO_SEL FSEL_C1 FSEL_C0 QC[0:3] 1 0 1 VCO4 1 1 0 VCO6 1 1 1 VCO8 Table 6. Output Divider PLL Feedback (M) VCO_SEL FSEL_FB2 FSEL_FB1 FSEL_FB0 QFB 0 0 0 0 VCO8 0 0 0 1 VCO12 0 0 1 0 VCO16 0 0 1 1 VCO20 0 1 0 0 VCO16 0 1 0 1 VCO24 0 1 1 0 VCO32 0 1 1 1 VCO40 1 0 0 0 VCO4 1 0 0 1 VCO6 1 0 1 0 VCO8 1 0 1 1 VCO10 1 1 0 0 VCO8 1 1 0 1 VCO12 1 1 1 0 VCO16 1 1 1 1 VCO20 Table 7. General Specifications Symbol Characteristics Min Typ Max VCC  2 Unit Condition VTT Output Termination Voltage V MM ESD Protection (Machine Model) 200 V HBM ESD Protection (Human Body Model) 2000 V LU Latch-Up Immunity 200 mA CPD Power Dissipation Capacitance 12 pF Per output CIN Input Capacitance 4.0 pF Inputs Table 8. Absolute Maximum Ratings(1) Symbol Characteristics Min Max Unit VCC Supply Voltage –0.3 3.9 V VIN DC Input Voltage –0.3 VCC+0.3 V DC Output Voltage –0.3 VCC+0.3 V DC Input Current 20 mA DC Output Current 50 mA 125 C VOUT IIN IOUT TS Storage Temperature –65 Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. REVISION 8 3/16/16 5 ©2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9772 DATA SHEET Table 9. DC Characteristics (VCC = 3.3 V ± 5%, TA = -40° to 85°C) Symbol Characteristics Min Typ Max Unit Condition VCC_PLL PLL Supply Voltage 3.0 VCC V LVCMOS VIH Input High Voltage 2.0 VCC + 0.3 V LVCMOS VIL Input Low Voltage 0.8 V LVCMOS VOH Output High Voltage V IOH = –24 mA(1) VOL Output Low Voltage V V IOL = 24 mA IOL = 12 mA ZOUT Output Impedance IIN ICC_PLL ICCQ 2.4 0.55 0.30  14 – 17 Input Current(2) Maximum PLL Supply Current 200 A VIN = VCC or GND 5.0 mA VCC_PLL Pin 15 mA All VCC Pins 3.0 Maximum Quiescent Supply Current 1. The MPC9772 is capable of driving 50  transmission lines on the incident edge. Each output drives one 50  parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50  series terminated transmission lines. 2. Inputs have pull-down resistors affecting the input current. Table 10. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40° to +85°C)(1), (2), continued on next page Max Symbol fREF Characteristics Input reference frequency Min 4 feedback 6 feedback 8 feedback 10 feedback 12 feedback 16 feedback 20 feedback 24 feedback 32 feedback 40 feedback 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 6.25 5.00 Input reference frequency in PLL bypass mode(3) fVCO VCO frequency range(4) 200 fXTAL Crystal interface frequency range(4) 10 fMAX Output Frequency 2 output 4 output 6 output 8 output 10 output 12 output 16 output 20 output 24 output 100.0 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 fSTOP_CLK Serial interface clock frequency tPW,MIN Input Reference Pulse Width(5) tR, tF CCLKx Input Rise/Fall Time(6) REVISION 8 3/16/16 Typ Condition TA = 0°C TA = –40°C to +70°C to +85°C 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 15.0 12.0 115.00 76.67 57.50 46.00 38.33 28.75 23.00 19.16 14.37 11.50 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz PLL locked 250 250 MHz PLL bypass 480 460 MHz 25 240.0 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 MHz 230.00 115.00 76.67 57.50 46.00 38.33 28.75 23.00 19.16 20 2.0 MHz MHz MHz MHz MHz MHz MHz MHz MHz PLL locked MHz ns 1.0 6 Unit ns 0.8 to 2.0 V ©2016 Integrated Device Technology, Inc. MPC9772 DATA SHEET Table 10. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40° to +85°C)(1), (2), continued on next page Max Symbol Characteristics Min t() Propagation Delay (static phase offset)(7) CCLK to FB_IN 6.25 MHz < fREF < 65.0 MHz 65.0 MHz < fREF < 125 MHz fREF=50 MHz and feedback=8 –3 –4 –166 tSK(O) Output-to-output Skew(8) Typ Unit TA = 0°C TA = –40°C to +70°C to +85°C PLL locked within QA outputs within QB outputs within QC outputs all outputs T 2 +3 +4 +166   ps 100 100 100 250 ps ps ps ps (T2) + 200 ps 1.0 ns DC Output Duty Cycle(9) (T2) – 200 tR, tF Output Rise/Fall Time 0.1 tPLZ, HZ Output Disable Time 8 ns tPZL, LZ Output Enable Time 8 ns 200 ps 150 ps 11 86 13 88 16 19 21 22 27 30 ps ps ps ps ps ps ps ps ps ps tJIT(CC) Cycle-to-cycle Jitter tJIT(PER) Period Jitter(11) 5. 6. 7. 8. 9. 10. 11. 12. 13. 150 I/O Phase Jitter RMS (1 )(12) 4 feedback 6 feedback 8 feedback 10 feedback 12 feedback 16 feedback 20 feedback 24 feedback 32 feedback 40 feedback BW PLL closed loop bandwidth(13) 4 feedback 6 feedback 8 feedback 10 feedback 12 feedback 16 feedback 20 feedback 24 feedback 32 feedback 40 feedback tLOCK 1. 2. 3. 4. (10) tJIT() Condition 1.20 – 3.50 0.70 – 2.50 0.50 – 1.80 0.45 – 1.20 0.30 – 1.00 0.25 – 0.70 0.20 – 0.55 0.17 – 0.40 0.12 – 0.30 0.11 – 0.28 Maximum PLL Lock Time 0.55 to 2.4 V (VCO=400 MHz) MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 10 ms AC characteristics apply for parallel output termination of 50  to VTT. In bypass mode, the MPC9772 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fREF= fVCO  (M Þ VCO_SEL). The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio: fXTAL(min, max) = fVCO(min, max)  (M  VCO_SEL) and 10 MHz  fXTAL  25 MHz. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN  fREF  100% and DCREF,MAX = 100% – DCREF, MIN. The MPC9772 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t(), tPW,MIN, DC and fMAX can only be guaranteed if tR, tF are within the specified range. Static phase offset depends on the reference frequency. t() [s] = t() []  (fREF  360). Excluding QSYNC output. See application section for part-to-part skew calculation. Output duty cycle is DC = (0.5  200 ps  fOUT)  100%. E.g. the DC range at fOUT = 100 MHz is 48% < DC < 52%. T = output period. Cycle jitter is valid for all outputs in the same divider configuration. See Applications Information section for more details. Period jitter is valid for all outputs in the same divider configuration. See Applications Information section for more details. I/O jitter is valid for a VCO frequency of 400 MHz. See Applications Information section for I/O jitter vs. VCO frequency. –3 dB point of PLL transfer characteristics. REVISION 8 3/16/16 7 ©2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9772 DATA SHEET APPLICATIONS INFORMATION MPC9772 Configurations Configuring the MPC9772 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: the specified frequency range. This divider is controlled by the VCO_SEL pin. VCO_SEL effectively extends the usable input frequency range while it has no effect on the output to reference frequency ratio. The output frequency for each bank can be derived from the VCO frequency and output divider: fOUT = fREF  M  N fREF PLL VCO_SEL fQA[0:3] = fVCO  (VCO_SEL  NA) N fQB[0:3] = fVCO  (VCO_SEL  NB) fQC[0:3] = fVCO  (VCO_SEL  NC) fOUT Table 11. MPC9772 Divider M where fREF is the reference frequency of the selected input clock source (CCLKO, CCLK1 or XTAL interface), M is the PLL feedback divider and N is a output divider. The PLL feedback divider is configured by the FSEL_FB[2:0] and the output dividers are individually configured for each output bank by the FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0] inputs. The reference frequency fREF and the selection of the feedback-divider M is limited by the specified VCO frequency range. fREF and M must be configured to match the VCO frequency range of 200 to 480 MHz in order to achieve stable PLL operation: Function VCO_SEL Values M PLL feedback FSEL_FB[0:3] 1 4, 6, 8, 10, 12, 16 2 8, 12, 16, 20, 24, 32, 40 Bank A Output Divider FSEL_A[0:1] 1 4, 6, 8, 12 2 8, 12, 16, 24 Bank B Output Divider FSEL_B[0:1] 1 4, 6, 8, 10 2 8, 12, 16, 20 Bank C Output Divider FSEL_C[0:1] 1 2, 4, 6, 8 2 4, 8, 12, 16 NA NB NC fVCO,MIN  (fREF  VCO_SEL  M)  fVCO,MAX Table 11 shows the various PLL feedback and output dividers and Figure 3 and Figure 4 display example configurations for the MPC9772: The PLL post-divider VCO_SEL is either a divide-by-one or a divide-by-two and can be used to situate the VCO into REVISION 8 3/16/16 Divider 8 ©2016 Integrated Device Technology, Inc. MPC9772 DATA SHEET CCLK0 CCLK1 CCLK_SEL fref = 33.3 MHz 1 VCO_SEL FB_IN 11 00 00 101 FSEL_A[1:0] FSEL_B[1:0] FSEL_C[1:0] FSEL_FB[2:0] QA[3:0] 33.3 MHz QB[3:0] 100 MHz QC[3:0] 200 MHz CCLK0 CCLK1 CCLK_SEL fref = 25 MHz 1 VCO_SEL FB_IN 00 00 00 011 QFB FSEL_A[1:0] FSEL_B[1:0] FSEL_C[1:0] FSEL_FB[2:0] MPC9772 QA[3:0] 62.5 MHz QB[3:0] 62.5 MHz QC[3:0] 125 MHz QFB MPC9772 33.3 MHz (Feedback) 25 MHz (Feedback) MPC9772 example configuration (feedback of QFB = 33.3 MHz, fVCO=400 MHz, VCO_SEL=1, M=12, NA=12, NB=4, NC=2). MPC9772 example configuration (feedback of QFB = 25 MHz, fVCO=250 MHz, VCO_SEL=1, M=10, NA=4, NB=4, NC=2). Frequency Range TA = 0°C to +70°C TA = –40°C to +85°C Frequency Range Input 16.6 – 40 MHz 16.6 – 38.33 MHz Input 20 – 48 MHz 20 – 46 MHz QA Outputs 16.6 – 40 MHz 16.6 – 38.33 MHz QA Outputs 50 – 120 MHz 50 – 115 MHz QA Outputs 50 – 120 MHz 50 – 115 MHz QA Outputs 50 – 120 MHz 50 – 115 MHz QC Outputs 100 – 240 MHz 100 – 230 MHz QC Outputs 100 – 240 MHz 100 – 230 MHz Figure 3. Example Configuration TA = 0°C to +70°C TA = –40°C to +85°C Figure 4. Example Configuration MPC9772 Individual Output Disable (Clock Stop) Circuitry The individual clock stop (output enable) control of the MPC9772 allows designers, under software control, to implement power management into the clock distribution design. A simple serial interface and a clock stop control logic provides a mechanism through which the MPC9772 clock outputs can be individually stopped in the logic ‘0’ state: The clock stop mechanism allows serial loading of a 12-bit serial input register. This register contains one programmable clock stop bit for 12 of the 14 output clocks. The QC0 and QFB outputs cannot be stopped (disabled) with the serial port. The user can program an output clock to stop (disable) by writing logic ‘0’ to the respective stop enable bit. Likewise, the user may programmably enable an output clock by writing logic ‘1’ to the respective enable bit. The clock stop logic enables or disables clock outputs during the time when the output would be in normally in logic low state, eliminating the possibility of short or ‘runt’ clock pulses. The user can write to the serial input register through the STOP_DATA input by supplying a logic ‘0’ start bit followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the free—running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the MPC9772 can sample each STOP_DATA bit with the rising edge of the free—running STOP_CLK signal. (See Figure 5.) STOP_CLK STOP_DATA START QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC Figure 5. Clock Stop Circuit Programming SYNC Output Description The MPC9772 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC9772 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic low) one period in duration and one period prior to the REVISION 8 3/16/16 coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse is dependent QA and QC output frequencies: the QSYNC pulse width is equal to the period of the higher of the QA and QC output frequencies. Figure 6 shows various waveforms for the QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank C outputs. 9 ©2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9772 DATA SHEET fVCO 1:1 Mode QA QC QSYNC 2:1 Mode QA QC QSYNC 3:1 Mode QC(2) QA(6) QSYNC 3:2 Mode QA(4) QC(6) QSYNC 4:1 Mode QC(2) QA(8) QSYNC 4:3 Mode QA(6) QC(8) QSYNC 6:1 Mode QA(12) QC(2) QSYNC Figure 6. QSYNC Timing Diagram REVISION 8 3/16/16 10 ©2016 Integrated Device Technology, Inc. MPC9772 DATA SHEET Power Supply Filtering The MPC9772 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9772 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA_PLL pin for the MPC9772. Figure 7 illustrates a typical power supply filter scheme. The MPC9772 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 3.0 V must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 7 must have a resistance of 5-10  to meet the voltage drop criteria. Using the MPC9772 in Zero-Delay Applications Nested clock trees are typical applications for the MPC9772. Designs using the MPC9772 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the MPC9772 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of Part-to-Part Skew The MPC9772 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9772 are connected together, the maximum overall timing uncertainty from the common CCLKx input to any output is: tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT()  CF CF = 22 F RF = 5–10 RF VCC this section should be adequate to eliminate power supply noise related problems in most designs. This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: VCC_PLL CF 10 nF MPC9772 VCC CCLKCommon 33...100 nF QFBDevice 1 Figure 7. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 7, the filter cut-off frequency is around 4.5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9772 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in REVISION 8 3/16/16 tPD,LINE(FB) –t() tJIT() Any QDevice 1 +tSK(O) +t() QFBDevice2 Any QDevice 2 Max. skew tJIT() +tSK(O) tSK(PP) Figure 8. MPC9772 Maximum Device-to-Device Skew 11 ©2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9772 DATA SHEET Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 12. Max. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 120 Table 12. Confidence Factor CF Probability of Clock Edge within the Distribution  1 0.68268948  2 0.95449988  3 0.99730007  4 0.99993663  5 0.99999943  6 0.99999999 tjit() [ps] RMS 100 CF FB=6 FB=24 40 0 200 FB=12 250 300 350 400 VCO Frequency [MHz] 450 480 Figure 10. MPC9772 I/O Jitter Max. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB tjit() [ps] RMS 140 120 450 FB=40 60 40 FB=20 250 300 350 400 VCO Frequency [MHz] 450 480 Figure 11. MPC9772 I/O Jitter Driving Transmission Lines The MPC9772 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20  the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Freescale Semiconductor application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50  resistance to VCC2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9772 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 12 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9772 clock driver is effectively doubled due to its capability to drive multiple lines. Max. I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB 160 140 FB=32 120 100 FB=16 80 FB=8 60 40 20 FB=4 0 200 250 300 350 400 VCO Frequency [MHz] FB=10 100 80 20 0 200 tSK(PP) = [-166ps...166ps] + [-250ps...250ps] + [(13ps @ –3)...(13ps @ 3)] + tPD, LINE(FB) tSK(PP) = [-455ps...455ps] + tPD, LINE(FB) tjit() [ps] RMS 60 20 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. Due to the frequency dependence of the static phase offset and I/O jitter, using Figure 9 to Figure 11 to predict a maximum I/O jitter and the specified t( parameter relative to the input reference frequency results in a precise timing performance analysis. In the following example calculation an I/O jitter confidence factor of 99.7% ( 3) is assumed, resulting in a worst case timing uncertainty from the common input reference clock to any output of –455 ps to +455 ps relative to CCLK (PLL feedback = 8, reference frequency = 50 MHz, VCO frequency = 400 MHz, I/O jitter = 13 ps rms max., static phase offset t() =  166 ps): 480 Figure 9. MPC9772 I/O Jitter REVISION 8 3/16/16 80 12 ©2016 Integrated Device Technology, Inc. MPC9772 DATA SHEET towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). MPC9772 Output Buffer 14 MPC9772 Output Buffer In ZO = 50  OutA OutA tD = 3.8956 2.5 OutB tD = 3.9386 2.0 RS = 36  ZO = 50  RS = 36  ZO = 50 In OutB0 Voltage (V) In 3.0 RS = 36  14 1.5 1.0 OutB1 0.5 0 Figure 12. Single versus Dual Transmission Lines 2 The waveform plots in Figure 13 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9772 output buffer is more than sufficient to drive 50  transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9772. The output waveform in Figure 13 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36  series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: 4 6 8 Time (ns) 10 12 14 Figure 13. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 14 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9772 Output Buffer VL = VS (Z0  (RS+R0 +Z0)) Z0 = 50 || 50 RS = 22  ZO = 50  RS = 22  ZO = 50  14 RS = 36  || 36  R0 = 14 VL = 3.0 (25  (18+17+25) 14  + 22  || 22  = 50  || 50  25  = 25  = 1.31 V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment Figure 14. Optimized Dual Line Termination MPC9772 DUT Pulse Generator Z = 50 ZO = 50 ZO = 50 RT = 50 RT = 50 VTT VTT Figure 15. CCLK MPC9772 AC Test Reference REVISION 8 3/16/16 13 ©2016 INTEGRATED DEVICE TECHNOLOGY, INC. MPC9772 DATA SHEET VCC VCC2 VCC GND VCC2 CCLKx VCC VCC2 GND GND VCC VCC2 FB_IN tSK(O) GND t() The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 16. Output-to-Output Skew tSK(O) Figure 17. Propagation Delay (t(), Static Phase Offset) Test Reference VCC VCC2 CCLKx GND tP FB_IN T0 DC = tP/T0 x 100% TJIT() = |T0-T1mean| The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 19. I/O Jitter Figure 18. Output Duty Cycle (DC) TN TN+1 TJIT(CC) = |TN-TN+1| TJIT(PER) = |TN-1/f0| T0 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 20. Cycle-to-Cycle Jitter Figure 21. Period Jitter VCC=3.3 V 2.4 0.55 tR tF Figure 22. Output Transition Time Test Reference REVISION 8 3/16/16 14 ©2016 Integrated Device Technology, Inc. MPC9772 DATA SHEET 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR 4X 4X 13 TIPS 0.20 (0.008) H L-M N 0.20 (0.008) T L-M N -XX=L, M, N 52 40 1 CL 39 AB G 3X VIEW Y -L- -M- AB B B1 13 V VIEW Y BASE METAL F PLATING V1 27 14 J 26 U -N- A1 D 0.13 (0.005) M T L-M S N S S1 SECTION AB-AB A ROTATED 90˚ CLOCKWISE S 4X θ2 C 0.10 (0.004) T -H-T- 4X θ3 SEATING PLANE VIEW AA 0.05 (0.002) S W 2X R θ1 R1 0.25 (0.010) C2 θ GAGE PLANE K C1 E Z VIEW AA NOTES: 1. CONTROLLING DIMENSIONS: MILLIMETER. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSTION 0.07 (0.003). DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z θ θ1 θ2 θ3 MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --1.70 0.05 0.20 1.50 1.30 0.40 0.20 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0˚ 7˚ --0˚ 12˚ REF 12˚ REF INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 7˚ 0˚ --0˚ 12˚ REF 12˚ REF CASE 848D-03 ISSUE D 52-LEAD LQFP PACKAGE REVISION 8 3/16/16 15 ©2016 Integrated Device Technology, Inc. MPC9772 DATA SHEET Revision History Sheet Rev Table 7 Page 1 8 8 REVISION 8 3/16/16 1 Description of Change Date NRND – Not Recommend for New Designs 1/8/13 Removed NRND and updated data sheet format 3/18/15 Product Discontinuation Notice - Last time buy expires September 7, 2016. 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