IDT70V3589

HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS IDT70V3599/89S DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: ◆ ◆ ◆ ◆ ◆ ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access – Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) – Industrial: 4.2ns (133MHz) (max.) Selectable Pipelined or Flow-Through output mode Counter enable and repeat features Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports – 6ns cycle time, 166MHz operation (12Gbps bandwidth) – Fast 3.6ns clock to data out – 1.7ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 166MHz – Data input, address, byte enable and control registers – Self-timed write allows fast cycle time ◆ ◆ ◆ ◆ ◆ ◆ ◆ Separate byte controls for multiplexed bus and bus matching compatibility Dual Cycle Deselect (DCD) for Pipelined Output mode LVTTL- compatible, 3.3V (±150mV) power supply for core LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port Industrial temperature range (-40°C to +85°C) is available at 133MHz. Available in a 208-pin Plastic Quad Flatpack (PQFP), 208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball Grid Array (BGA) Supports JTAG features compliant with IEEE 1149.1 Functional Block Diagram BE3L BE2L BE1L BE0L BE3R BE2R BE1R BE0R FT/PIPEL 1/0 0a 1a a 0b 1b b 0c 1c c 0d 1d d 1d 0d d 1c 0c c 1b 0b b 1a 0a a 1/0 FT/PIPER R/WL R/WR CE0L CE1L 1 0 1/0 B W 0 L B W 1 L BBB WWW 233 LLR B W 2 R BB WW 10 RR 1 0 1 /0 CE0R CE1R OEL OER Dout0-8_L Dout9-17_L Dout18-26_L Dout27-35_L Dout0-8_R Dout9-17_R Dout18-26_R Dout27-35_R 1d 0d 1c 0c 1b 0b 1a 0a a b cd 0a 1a 0b 1b 0c 1c 0d 1d 0/1 FT/PIPEL 0/1 FT/PIPER d cba 128K x 36 MEMORY ARRAY I/O0L - I/O35 L Din_L Din_R I/O0R - I/O35R CLKL A16L (1) A0L REPEATL ADSL CNTENL CLKR , A 16R(1) Counter/ Address Reg. ADDR_L ADDR_R Counter/ Address Reg. A 0R REPEATR ADSR CNTENR 5617 tbl 01 TDI NOTE: 1. A16 is a NC for IDT70V3589. JTAG TDO TCK TMS TRST MAY 2003 1 DSC 5617/6 ©2003 Integrated Device Technology, Inc. IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges The IDT70V3599/89 is a high-speed 128/64K x 36 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V3599/89 has been optimized for applications having unidirectional Description: or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70V3599/89 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) remains at 3.3V. Pin Configuration(1,2,3,4,5) 06/28/02 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 IO19L IO18L B1 B2 VSS B3 TDO B4 NC B5 A16L(1) A12L B6 B7 A8L B8 BE1L B9 VDD B10 CLKL CNTENL A4L B11 B12 B13 A0L B14 OPTL I/O17L B15 B16 VSS B17 I/O20R C1 VSS C2 I/O18R C3 TDI C4 NC C5 A13L C6 A9L C7 BE2L C8 CE0L C9 VSS C10 ADSL C11 A5L C12 A1L C13 VSS C14 VDDQR I/O16L I/O15R C15 C16 C17 VDDQL I/O19R VDDQR PL/FT L D1 D2 D3 D4 NC D5 A14L D6 A10L D7 BE3L D8 CE1L D9 VSS D10 R/WL D11 A6L D12 A2L D13 VDD D14 I/O16R I/O15L D15 D16 VSS D17 I/O22L E1 VSS E2 I/O21L I/O20L A15L E3 E4 A11L A7L BE0L VDD OEL REPEATL A3L VDD I/O17R VDDQL I/O14L I/O14R E14 E15 E16 E17 I/O23L I/O22R VDDQR I/O21R F1 F2 F3 F4 I/O12L I/O13R F14 F15 VSS F16 I/O13L F17 VDDQL I/O23R I/O24L G1 G2 G3 VSS G4 VSS G14 I/O12R I/O11L VDDQR G15 G16 G17 I/O26L H1 VSS H2 I/O25L I/O24R H3 H4 I/O9L VDDQL I/O10L I/O11R VDD J1 I/O26R VDDQR I/O25R J2 J3 J4 70V3599/89BF BF-208(6) 208-Pin fpBGA Top View(7) H14 H15 H16 H17 VDD J14 IO9R J15 VSS J16 I/O10R J17 VDDQL K1 VDD K2 VSS K3 VSS K4 VSS K14 VDD K15 VSS VDDQR K16 K17 I/O28R L1 VSS L2 I/O27R L3 VSS L4 I/O7R VDDQL I/O8R L14 L15 L16 VSS L17 I/O29R I/O28L VDDQR I/O27L M1 M2 M3 M4 I/O6R M14 I/O7L M15 VSS M16 I/O8L M17 VDDQL I/O29L I/O30R N1 N2 N3 VSS N4 VSS N14 I/O6L I/O5R VDDQR N15 N16 N17 I/O31L P1 VSS P2 I/O31R I/O30L P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 I/O3R VDDQL I/O4R P14 P15 P16 I/O5L P17 I/O32R I/O32L VDDQR I/O35R TRST A16R(1) A12R R1 R2 R3 R4 R5 R6 R7 A8R R8 BE1R R9 VDD R10 CLKR CNTENR A4R R11 R12 R13 I/O2L I/O3L R14 R15 VSS R16 I/O4L R17 VSS T1 I/O33L I/O34R TCK T2 T3 T4 NC T5 A13R T6 A9R T7 BE2R CE0R T8 T9 VSS T10 ADSR T11 A5R T12 A1R T13 VSS T14 VDDQL I/O1R VDDQR T15 T16 T17 I/O33R I/O34L VDDQL TMS U1 U2 U3 U4 NC U5 A14R U6 A10R U7 BE3R U8 CE1R U9 VSS U10 R/WR A6R U12 A2R U13 VSS U14 I/O0R U15 VSS U16 I/O2R U17 VSS I/O35L PL/ FTR NC A15R A11R A7R BE0R VDD OER A3R A0R VDD OPTR I/O0L I/O1L , NOTES: 5617 drw 02c 1. A16 is a NC for IDT70V3589. 2. All VDD pins must be connected to 3.3V power supply. 3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 4. All VSS pins must be connected to ground supply. 5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 6. This package code is used to reference the package diagram. 7. This text does not indicate orientation of the actual part-marking. 62 .42 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Pin Configuration(1,2,3,4,5) (con't.) 70V3599/89BC BC-256(6) 06/28/02 A1 A2 A3 A4 A5 A6 A7 256-Pin BGA Top View(7) A8 A9 A10 A11 A12 A13 A14 A15 A16 NC B1 TDI B2 NC B3 NC B4 A14L B5 A11L B6 A8L B7 BE2L B8 CE1L B9 OEL CNTENL B10 B11 A5L B12 A2L B13 A0L B14 NC B15 NC B16 I/O18L C1 NC C2 TDO C3 NC C4 A15L C5 A12L C6 A9L C7 BE3L C8 CE0L R/WL REPEATL C9 C10 C11 A4L C12 A1L C13 VDD C14 I/O17L C15 NC C16 I/O18R I/O19L D1 D2 VSS D3 A16L(1) D4 A13L D5 A10L D6 A7L D7 BE1L D8 BE0L CLKL ADSL D9 D10 D11 A6L D12 A3L D13 OPTL I/O17R I/O16L D14 D15 D16 I/O20R I/O19R I/O20L PIPE/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD I/O15R I/O15L I/O16R E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 I/O21R I/O21L I/O22L VDDQL F1 F2 F3 F4 VDD F5 VDD F6 VSS F7 VSS F8 VSS F9 VSS F10 VDD F11 VDD VDDQR I/O13L I/O14L I/O14R F12 F13 F14 F15 F16 I/O23L I/O22R I/O23R VDDQL G1 G2 G3 G4 VDD G5 VSS G6 VSS G7 VSS G8 VSS G9 VSS G10 VSS G11 VDD VDDQR I/O12R I/O13R I/O12L G12 G13 G14 G15 G16 I/O24R I/O24L I/O25L VDDQR H1 H2 H3 H4 VSS H5 VSS H6 VSS H7 VSS H8 VSS H9 VSS H10 VSS H11 VSS H12 VDDQL I/O10L I/O11L I/O11R H13 H14 H15 H16 I/O26L I/O25R I/O26R VDDQR VSS J1 J2 J3 J4 J5 VSS J6 VSS J7 VSS J8 VSS J9 VSS J10 VSS J11 VSS J12 VDDQL I/O9R J13 J14 IO9L I/O10R J15 J16 I/O27L I/O28R I/O27R VDDQL K1 K2 K3 K4 VSS K5 VSS K6 VSS K7 VSS K8 VSS K9 VSS K10 VSS K11 VSS K12 VDDQR I/O8R I/O7R K13 K14 K15 I/O8L K16 I/O29R I/O29L I/O28L VDDQL L1 L2 L3 L4 VSS L5 VSS L6 VSS L7 VSS L8 VSS L9 VSS L10 VSS L11 VSS L12 VDDQR I/O6R L13 L14 I/O6L L15 I/O7L L16 I/O30L I/O31R I/O30R VDDQR VDD M1 M2 M3 M4 M5 VSS M6 VSS M7 VSS M8 VSS M9 VSS M10 VSS M11 VDD M12 VDDQL I/O5L M13 M14 I/O4R I/O5R M15 M16 I/O32R I/O32L I/O31L VDDQR N1 N2 N3 N4 VDD N5 VDD N6 VSS N7 VSS N8 VSS N9 VSS N10 VDD N11 VDD N12 VDDQL I/O3R N13 N14 I/O3L N15 I/O4L N16 I/O33L I/O34R I/O33R PIPE/FTR VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 VDD P13 I/O2L P14 I/O1R I/O2R P15 P16 I/O35R I/O34L TMS A16R(1) A13R R1 R2 R3 R4 R5 A10R R6 A7R R7 BE1R BE0R CLKR ADSR R8 R9 R10 R11 A6R R12 A3R R13 I/O0L I/O0R R14 R15 I/O1L R16 I/O35L T1 NC T2 TRST T3 NC T4 A15R T5 A12R T6 A9R T7 BE3R CE0R R/WR REPEATR T8 T9 T10 T11 A4R T12 A1R T13 OPTR T14 NC T15 NC T16 , NC TCK NC NC A14R A11R A8R BE2R CE1R OER CNTENR A5R A2R A0R NC NC 5617 drw 02d NOTES: 1. A16 is a NC for IDT70V3589. 2. All VDD pins must be connected to 3.3V power supply. 3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 4. All VSS pins must be connected to ground supply. 5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 6. This package code is used to reference the package diagram. 7. This text does not indicate orientation of the actual part-marking. , 63 .42 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Pin Configuration(1,2,3,4,5) (con't.) 06/28/02 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 VSS VDDQR I/O18R I/O18L VSS PL/FTL TDI TDO NC NC NC A16L(1) A15L A14L A13L A12L A11L A10L A9L A8L A7L BE3L BE2L BE1L BE0L CE1L CE0L VDD VDD VSS VSS CLKL OEL R/WL ADSL CNTENL REPEATL A6L A5L A4L A3L A2L A1L A0L VDD VDD VSS OPTL I/O17L I/O17R VDDQR VSS 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 I/O19L I/O19R I/O20L I/O20R VDDQL VSS I/O21L I/O21R I/O22L I/O22R VDDQR VSS I/O23L I/O23R I/O24L I/O24R VDDQL VSS I/O25L I/O25R I/O26L I/O26R VDDQR VSS VDD VDD VSS VSS VDDQL VSS I/O27R I/O27L I/O28R I/O28L VDDQR VSS I/O29R I/O29L I/O30R I/O30L VDDQL VSS I/O31R I/O31L I/O32R I/O32L VDDQR VSS I/O33R I/O33L I/O34R I/O34L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 70V3599/89DR DR-208(6) 208-Pin PQFP Top View(7) 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 I/O16L I/O16R I/O15L I/O15R VSS VDDQL I/O14L I/O14R I/O13L I/O13R VSS VDDQR I/O12L I/O12R I/O11L I/O11R VSS VDDQL I/O10L I/O10R I/O9L I/O9R VSS VDDQR VDD VDD VSS VSS VSS VDDQL I/O8R I/O8L I/O7R I/O7L VSS VDDQR I/O6R I/O6L I/O5R I/O5L VSS VDDQL I/O4R I/O4L I/O3R I/O3L VSS VDDQR I/O2R I/O2L I/O1R I/O1L , NOTES: 1. 2. 3. 4. 5. 6. 7. A16 is a NC for IDT70V3589. All VDD pins must be connected to 3.3V power supply. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). All VSS pins must be connected to ground supply. Package body is approximately 28mm x 28mm x 3.5mm. This package code is used to reference the package diagram. This text does not indicate orientation of the actual part-marking. VSS VDDQL I/O35R I/O35L PL/FTR TMS TCK TRST NC NC NC A16R(1) A15R A14R A13R A12R A11R A10R A9R A8R A7R BE3R BE2R BE1R BE0R CE1R CE0R VDD VDD VSS VSS CLKR OER R/WR ADSR CNTENR REPEATR A6R A5R A4R A3R A2R A1R A0R VDD VSS VSS OPTR I/O0L I/O0R VDDQL VSS 5617 drw 02a 64 .42 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port CE0L, CE1L R/WL OEL A0L - A16L (1) Right Port CE0R, CE1R R/ WR OER A0R - A16R (1) Names Chip Enables (5) Read/Write Enable Output Enable Address Data Input/Output Clock Pipeline/Flow-Through Address Strobe Enable Counter Enable Counter Repeat(4) Byte Enables (9-bit bytes)(5) Power (I/O Bus) (3.3V or 2.5V)(2) Option for selecting VDDQX(2,3) Power (3.3V)(2) Ground (0V) Test Data Input Test Data Output Test Logic Clock (10MHz) Test Mode Select Reset (Initialize TAP Controller) 5617 tbl 01 I/O0L - I/O35L CLKL PL/ FTL ADSL CNTENL REPEATL BE0L - BE3L VDDQL OPTL I/O0R - I/O35R CLKR PL/FTR ADSR CNTENR REPEATR BE0R - BE3R VDDQR OPTR VDD VSS TDI TDO TCK TMS TRST NOTES: 1. A16 is a NC for IDT70V3589. 2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 3. OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and address controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 4. When REPEATX is asserted, the counter will reset to the last valid address loaded via ADS X. 5. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the signals take two cycles to deselect. 65 .42 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Truth Table I—Read/Write and Enable Control(1,2,3,4) OE X X X X X X X X X X L L L L L L L H CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ CE0 H X L L L L L L L L L L L L L L L L CE1 X L H H H H H H H H H H H H H H H H BE3 X X H H H H L H L L H H H L H L L L BE2 X X H H H L H H L L H H L H H L L L BE1 X X H H L H H L H L H L H H L H L L BE0 X X H L H H H L H L L H H H L H L L R/W X X X L L L L L L L H H H H H H H X Byte 3 I/O27-35 High-Z High-Z High-Z High-Z High-Z High-Z DIN High-Z DIN DIN High-Z High-Z High-Z DOUT High-Z DOUT DOUT High-Z Byte 2 I/O18-26 High-Z High-Z High-Z High-Z High-Z DIN High-Z High-Z DIN DIN High-Z High-Z DOUT High-Z High-Z DOUT DOUT High-Z Byte 1 I/O9-17 High-Z High-Z High-Z High-Z DIN High-Z High-Z DIN High-Z DIN High-Z DOUT High-Z High-Z DOUT High-Z DOUT High-Z Byte 0 I/O0-8 High-Z High-Z High-Z DIN High-Z High-Z High-Z DIN High-Z DIN DOUT High-Z High-Z High-Z DOUT High-Z DOUT High-Z MODE Deselected–Power Down Deselected–Power Down All Bytes Deselected Write to Byte 0 Only Write to Byte 1 Only Write to Byte 2 Only Write to Byte 3 Only Write to Lower 2 Bytes Only Write to Upper 2 bytes Only Write to All Bytes Read Byte 0 Only Read Byte 1 Only Read Byte 2 Only Read Byte 3 Only Read Lower 2 Bytes Only Read Upper 2 Bytes Only Read All Bytes Outputs Disabled 5617 tbl 02 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN , REPEAT = VIH. 3. OE is an asynchronous input signal. 4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here. Truth Table II—Address Counter Control(1,2) External Address X An An X Previous Internal Address X X Ap Ap Internal Address Used An An Ap Ap + 1 CLK ↑ ↑ ↑ ↑ ADS X L (4) CNTEN X X H L (5) REPEAT(6) L(4) H H H I/O(3) DI/O(0) DI/O (n) DI/O(p) DI/O(p+1) MODE Counter Reset to last valid ADS load External Address Used External Address Blocked—Counter disabled (Ap reused) Counter Enabled—Internal Address generation H H 5617 tbl 03 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE. 3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the date out will be delayed by one cycle. 4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn. 6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location. 66 .42 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Recommended Operating Temperature and Supply Voltage(1) Grade Commercial Industrial Ambient Temperature 0OC to +70OC -40 C to +85 C O O Recommended DC Operating Conditions with VDDQ at 2.5V Symbol Parameter Core Supply Voltage I/O Supply Voltage Ground Input High Voltage (Address & Control Inputs) Input High Voltage - I/O(3) Input Low Voltage (3) Min. 3.15 2.4 0 1.7 1.7 -0.3 (1) Typ. 3.3 2.5 0 ____ Max. 3.45 2.6 0 V DDQ + 100mV (2) Unit V V V V V V 5617 tbl 05a GND 0V 0V VDD 3.3V + 150mV 3.3V + 150mV 5617 tbl 04 V DD VDDQ V SS VIH VIH VIL NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. ____ ____ V DDQ + 100mV(2) 0.7 Absolute Maximum Ratings(1) Symbol VTERM(2) TBIAS(3) TSTG TJN IOUT Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Junction Temperature DC Output Current Commercial & Industrial -0.5 to +4.6 -55 to +125 -65 to +150 +150 50 Unit V o NOTES: 1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed. 2. VTERM must not exceed VDDQ + 100mV. 3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be supplied as indicated above. C C C Recommended DC Operating Conditions with VDDQ at 3.3V Symbol V DD VDDQ V SS VIH VIH VIL Parameter Core Supply Voltage I/O Supply Voltage (3) Ground Input High Voltage (Address & Control Inputs)(3) Input High Voltage - I/O(3) Input Low Voltage Min. 3.15 3.15 0 2.0 2.0 -0.3(1) Typ. 3.3 3.3 0 ____ o o Max. 3.45 3.45 0 VDDQ + 150mV (2) Unit V V V V V V 5617 tbl 05b mA 5617 tbl 06 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or 4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV. 3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected. ____ ____ VDDQ + 150mV(2) 0.8 NOTES: 1. Undershoot of VIL > -1.5V for pulse width less than 10ns is allowed. 2. VTERM must not exceed VDDQ + 150mV. 3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be supplied as indicated above. 67 .42 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Capacitance(1) Symbol CIN COUT (3) (TA = +25°C, F = 1.0MHZ) PQFP ONLY Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 8 10.5 Unit pF pF 5617 tbl 07 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV) 70V3599/89S Symbol |ILI| |ILO | VOL (3.3V) VOH (3.3V) VOL (2.5V) VOH (2.5V) Parameter Input Leakage Current (1) (1) Test Conditions VDDQ = Max., VIN = 0V to V DDQ CE0 = VIH or CE1 = VIL, VOUT = 0V to V DDQ IOL = + 4mA, VDDQ = Min. IOH = -4mA, VDDQ = Min. IOL = + 2mA, VDDQ = Min. IOH = -2mA, VDDQ = Min. Min. ___ ___ ___ Max. 10 10 0.4 ___ Unit µA µA V V V V 5617 tbl 08 Output Leakage Current Output Low Voltage(2) Output High Voltage (2) Output Low Voltage (2) (2) 2.4 ___ 0.4 ___ Output High Voltage 2.0 NOTE: 1. At VDD < 2.0V leakages are undefined. 2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details. 68 .42 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV) 70V3599/89S166 Com'l Only Symbol IDD Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) Full Standby Current (One Port - CMOS Level Inputs) CEL and C ER= VIL, Outputs Disabled, f = fMAX(1) CEL = C ER = VIH, Outputs Disabled, f = fMAX(1) CE"A" = VIL and C E"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(1) Both Ports Outputs Disabled CEL and C ER > VDD - 0.2V, VIN > VDD - 0.2V or VIN < 0.2V, f = 0(2) CE"A" < 0.2V and CE"B" > VDD - 0.2V(5) VIN > VDD - 0.2V or VIN < 0.2V Active Port, Outp uts Disabled , f = f MAX(1) Test Condition Version COM'L IND COM'L IND COM'L IND COM'L IND COM'L IND S S S S S S S S S S Typ.(4) 370 ____ 70V3599/89S133 Com'l & Ind Typ. (4) 320 320 115 115 220 220 15 15 220 220 Max. 400 480 160 195 290 350 30 40 290 350 5617 tbl 09 Max. 500 ____ Unit mA ISB1 125 ____ 200 ____ mA ISB2 250 ____ 350 ____ mA ISB3 15 ____ 30 ____ mA ISB4 250 ____ 350 ____ mA NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ). 5. CEX = V IL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X - 0.2V "X" represents "L" for left port or "R" for right port. 69 .42 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges AC Test Conditions (VDDQ - 3.3V/2.5V) Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V/GND to 2.4V GND to 3.0V/GND to 2.4V 2ns 1.5V/1.25V 1.5V/1.25V Figures 1 and 2 5617 tbl 10 2.5V 833Ω DATAOUT 770Ω 5pF* , 3.3V 590Ω 50Ω DATAOUT 50Ω 1.5V/1.25 10pF (Tester) , DATAOUT 435Ω 5pF* 5617 drw 03 Figure 1. AC Output Test load. 5617 drw 04 , Figure 2. Output Test Load (For tCKLZ , tCKHZ, tOLZ, and tOHZ). *Including scope and jig. 10.5pF is the I/O capacitance of this device, and 10pF is the AC Test Load Capacitance. 7 6 5 4 ∆tCD (Typical, ns) 3 2 1 • • 20.5 • 30 • 50 80 100 200 , -1 Capacitance (pF) 5617 drw 05 Figure 3. Typical Output Derating (Lumped Capacitive Load). 6.42 10 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(2,3) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C) 70V3599/89S166 Com'l Only Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tSA tHA tSC tHC tSB tHB tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRPT tHRPT tOE tOLZ tOHZ tCD1 tCD2 tDC tCKHZ tCKLZ Clock Cycle Time (Flow-Through)(1) Clock Cycle Time (Pipelined) (1) (1) 70V3599/89S133 Com'l & Ind Min. 25 7.5 7 7 2.6 2.6 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 ____ Parameter Min. 20 6 6 6 2.1 2.1 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5 ____ Max. ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ Max. ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clock High Time (Flow-Through) Clock Low Time (Flow-Through)(1) Clock High Time (Pipelined) Clock Low Time (Pipelined) Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time Byte Enable Setup Time Byte Enable Hold Time R/W Setup Time R/W Hold Time Input Data Setup Time Input Data Hold Time ADS Setup Time ADS Hold Time CNTEN Setup Time CNTEN Hold Time REPEAT Setup Time REPEAT Hold Time Output Enable to Data Valid Output Enable to Output Low-Z Output Enable to Output High-Z Clock to Data Valid (Flow-Through)(1) Clock to Data Valid (Pipelined)(1) Data Output Hold After Clock High Clock High to Output High-Z Clock High to Output Low-Z (2) (1) 4.0 ____ 4.2 ____ 1 1 ____ ____ 1 1 ____ ____ 3.6 12 3.6 ____ 4.2 15 4.2 ____ 1 1 1 1 1 1 3 ____ 3 ____ Port-to-Port Delay tCO Clock-to-Clock Offset 5 ____ 6 ____ ns 5617 tbl 11 NOTES: 1. The Pipelined output parameters (t CYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when FT /PIPE = VIL for that port. 2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a DC signal, i.e. steady state during operation. 3. These values are valid for either level of V DDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port. 6.42 11 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE'X' = VIH)(2) tCYC2 tCH2 CLK CE0 tCL2 tSC CE1 tSB BEn tHC tSC (3) tHC tHB tSB (5) tHB R/W tSW tSA tHW tHA An + 1 (1 Latency) tCD2 Qn tCKLZ (1) ADDRESS (4) An An + 2 tDC Qn + 1 An + 3 DATAOUT Qn + 2 tOLZ (5) tOHZ OE (1) tOE 5617 drw 06 Timing Waveform of Read Cycle for Flow-through Output (FT/PIPE"X" = VIL)(2,6) tCYC1 tCH1 CLK CE0 tCL1 tSC CE1 tSB BEn tHC tSC (3) tHC tHB tSB tHB R/W tSW tHW tSA tHA An + 1 tCD1 tDC Qn tCKLZ (1) ADDRESS (4) An An + 2 An + 3 tCKHZ DATAOUT Qn + 1 tOHZ tOLZ Qn + 2 (5) tDC OE NOTES: 1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 2. ADS = VIL, CNTEN and REPEAT = VIH. 3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to Truth Table 1. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. If BEn was HIGH, then the appropriate Byte of DATA OUT for Qn + 2 would be disabled (High-Impedance state). 6. "x" denotes Left or Right port. The diagram is with respect to that port. tOE 5617 drw 07 6.42 12 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of a Multi-Device Pipelined Read(1,2) tCH2 CLK tSA ADDRESS(B1) tSC CE0(B1) tCYC2 tCL2 tHA A0 tHC tSC tCD2 tHC tCD2 Q0 tDC Q1 tDC A3 A4 tCKLZ A5 tCKHZ tCD2 Q3 tCKHZ A6 A1 A2 A3 A4 A5 A6 DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1 A2 tSC CE0(B2) tHC tSC tHC tCD2 tCKHZ Q2 tCKLZ tCKLZ 5617 drw 08 tCD2 Q4 DATAOUT(B2) Timing Waveform of a Multi-Device Flow-Through Read(1,2) tCH1 CLK tSA ADDRESS(B1) tSC tHA A0 tHC tSC tHC tCD1 DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1 A2 A3 A4 A5 A6 D0 tDC tCD1 D1 tDC tCKLZ (1) tCYC1 tCL1 A1 A2 A3 A4 A5 A6 CE0(B1) tCKHZ (1) tCD1 D3 tCKHZ (1) tCD1 D5 tCKLZ (1) tSC tHC CE0(B2) tSC tHC tCD1 DATAOUT(B2) tCKLZ (1) tCKHZ D2 (1) tCD1 tCKLZ (1) tCKHZ D4 (1) 5617 drw 09 NOTES: 1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3599/89 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. BEn, OE, and ADS = VIL; CE1(B1) , CE1(B2) , R/W, CNTEN, and REPEAT = VIH. 6.42 13 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4) CLK"A" tSW R/W"A" tSA ADDRESS"A" tHA NO MATCH tHW MATCH tSD DATAIN"A" tHD VALID tCO(3) CLK"B" tCD2 R/W"B" tSW tSA ADDRESS"B" tHW tHA NO MATCH MATCH DATAOUT"B" VALID NOTES: 1. CE0, BEn, and ADS = VIL; CE1, CNTEN , and REPEAT = VIH. 2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to. 3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be tCO + 2 tCYC2 + tCD2 ). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port will be tCO + t CYC2 + t CD2). 4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A" tDC 5617 drw 10 Timing Waveform with Port-to-Port Flow-Through Read(1,2,4) CLK "A" tSW R/W "A" tSA ADDRESS "A" tHA NO MATCH tHW MATCH tSD DATAIN "A" tHD VALID tCO CLK "B" (3) tCD1 R/W "B" tSW tSA ADDRESS "B" tHW tHA NO MATCH MATCH tCD1 DATAOUT "B" tDC VALID VALID tDC 5617 drw 11 NOTES: 1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be tCO + t CYC + tCD1 ). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will be tCO + t CD1). 4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A". 6.42 14 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read tCYC2 (OE = VIL)(2) tCH2 tCL2 CLK CE0 tSC CE1 tSB BEn tHC tHB tSW tHW R/W tSW tHW ADDRESS (3) An tSA tHA An +1 An + 2 An + 2 tSD tHD Dn + 2 An + 3 An + 4 DATAIN (1) tCD2 Qn tCKHZ tCKLZ tCD2 Qn + 3 DATAOUT READ NOP (4) WRITE READ 5617 drw 12 NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE 0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation". 3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2) tCH2 CLK CE0 tCYC2 tCL2 tSC CE1 tSB BEn tHC tHB tSW tHW R/W tSW tHW (3) ADDRESS An tSA tHA An +1 An + 2 tSD tHD An + 3 An + 4 An + 5 DATAIN (1) tCD2 Qn tOHZ (4) Dn + 2 Dn + 3 tCKLZ tCD2 Qn + 4 DATAOUT OE 5617 drw 13 NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE 0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows. READ WRITE READ 6.42 15 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2) tCH1 CLK tCYC1 tCL1 CE0 tSC tHC CE1 tSB BEn tHB tSW tHW R/W tSW tHW ADDRESS (3) tSA DATAIN (1) An tHA An +1 An + 2 An + 2 tSD tHD Dn + 2 An + 3 An + 4 tCD1 Qn tDC READ tCD1 Qn + 1 tCKHZ (5) NOP tCD1 tCD1 Qn + 3 tDC READ DATAOUT tCKLZ WRITE 6517 drw 14 Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2) tCYC1 tCH1 tCL1 CLK CE0 tSC tHC CE1 tSB BEn tHB tSW tHW R/W ADDRESS (3) tSW tHW An tSA tHA An +1 An + 2 tSD tHD Dn + 2 (1) An + 3 An + 4 An + 5 DATAIN tCD1 Qn tOHZ OE Dn + 3 tDC tOE tCD1 tCKLZ tCD1 Qn + 4 tDC DATAOUT READ WRITE READ 5617 drw 15 NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 16 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read with Address Counter Advance(1) tCH2 CLK tSA ADDRESS tHA tCYC2 tCL2 An tSAD tHAD ADS tSAD tHAD CNTEN tSCN tHCN tCD2 DATAOUT Qx - 1(2) Qx tDC Qn Qn + 1 Qn + 2(2) Qn + 3 READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 5617 drw 16 Timing Waveform of Flow-Through Read with Address Counter Advance(1) tCH1 CLK tSA ADDRESS tHA tCYC1 tCL1 An tSAD tHAD ADS tSAD tHAD tSCN tHCN CNTEN tCD1 DATAOUT Qx(2) tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER 5617 drw 17 Qn Qn + 1 Qn + 2 Qn + 3(2) Qn + 4 NOTES: 1. CE 0, OE, BEn = VIL; CE1, R/W, and REPEAT = V IH. 2. If there is no address change via ADS = V IL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks. 6.42 17 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Write with Address Counter Advance (Flow-through or Pipelined Inputs)(1) tCH2 CLK tSA ADDRESS tHA tCYC2 tCL2 An INTERNAL(3) ADDRESS tSAD tHAD ADS An(7) An + 1 An + 2 An + 3 An + 4 tSCN tHCN CNTEN tSD tHD DATAIN Dn WRITE EXTERNAL ADDRESS Dn + 1 Dn + 1 Dn + 2 Dn + 3 Dn + 4 WRITE WRITE WITH COUNTER COUNTER HOLD WRITE WITH COUNTER 5617 drw 18 Timing Waveform of Counter Repeat(2) tCH2 CLK tSA tHA (4) tCYC2 tCL2 ADDRESS INTERNAL(3) ADDRESS Ax LAST ADS LOAD tSW tHW R/W ADS CNTEN An LAST ADS +1 An + 1 An + 2 An An + 1 t SAD tHAD tSCN tHCN tSRPT tHRPT REPEAT tSD tHD D0 DATAIN (5) DATAOUT (6) QLAST EXECUTE REPEAT WRITE LAST ADS ADDRESS READ LAST ADS ADDRESS READ LAST ADS ADDRESS + 1 QLAST+1 READ ADDRESS n+1 Qn READ ADDRESS n NOTES: 1. CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH. 2. CE0, BEn = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II. 7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is written to during this cycle. 5617 drw 19 6.42 18 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Functional Description The IDT70V3599/89 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the LOW to HIGH transition of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70V3599/89s for depth expansion configurations. Two cycles are required with CE0 LOW and CE1 HIGH to re-activate the outputs. Depth and Width Expansion The IDT70V3599/89 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT70V3599/89 can also be used in applications requiring expanded width, as indicated in Figure 4. Through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 72-bits or wider. A17/A16(1) IDT70V3599/89 CE0 CE1 VDD IDT70V3599/89 CE0 CE1 VDD Control Inputs Control Inputs IDT70V3599/89 CE1 CE0 IDT70V3599/89 CE1 CE0 BE, R/W, OE, CLK, ADS, REPEAT, CNTEN Control Inputs Control Inputs 5617 drw 20 Figure 4. Depth and Width Expansion with IDT70V3599/89 NOTE: 1. A17 is for IDT70V3599, A16 is for IDT70V3589. 6.42 19 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges JTAG Timing Specifications tJF TCK tJCL tJCYC tJR tJCH Device Inputs(1)/ TDI/TMS tJS Device Outputs(2)/ TDO TRST 5617 drw 21 tJH tJDC tJRSR tJCD , tJRST Figure 5. Standard JTAG Timing NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO. JTAG AC Electrical Characteristics(1,2,3,4) 70V3599/89 Symbol tJCYC tJCH tJCL tJR tJF tJRST tJRSR tJCD tJDC tJS tJH Parameter JTAG Clock Input Period JTAG Clock HIGH JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery JTAG Data Output JTAG Data Output Hold JTAG Setup JTAG Hold Min. 100 40 40 ____ ____ Max. ____ ____ ____ Units ns ns ns ns ns ns ns ns ns ns ns 5617 tbl 12 3(1) 3 (1) 50 50 ____ ____ ____ 25 ____ ____ ____ 0 15 15 NOTES: 1. Guaranteed by design. 2. 30pF loading on external output signals. 3. Refer to AC Electrical Test Conditions stated earlier in this document. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet. 6.42 20 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Identification Register Definitions Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) NOTE: 1. Device ID for IDT70V3589 is 0x0313. Value 0x0 0x0312 0x33 1 (1) Description Reserved for version number Defines IDT part number Allows unique identification of device vendor as IDT Indicates the presenc e of an ID register 5617 tbl 13 Scan Register Sizes Register Name Instruction (IR) Bypass (BYR) Identification (IDR) Boundary Scan (BSR) Bit Size 4 1 32 Note (3) 5617 tbl 14 System Interface Parameters Instruction EXTEST BYPASS IDCODE Code 0000 1111 0010 0011 0001 Description Forces contents of the bound ary scan cells onto the device outputs(1). Places the boundary scan register (BSR) between TDI and TDO. Places the bypass registe r (BYR) between TDI and TDO. Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state. Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI. Several combinations are reserved. Do not use codes other than those identified above. 5617 tbl 15 HIGHZ SAMPLE/PRELOAD RESERVED All other codes NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST . 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative. 6.42 21 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank I BF DR BC Commercial (0°C to +70°C) Industrial (-40°C to +85°C) 208-pin fpBGA (BF-208) 208-pin PQFP (DR-208) 256-pin BGA (BC-256) 166 133 Commercial Only Commercial & Industrial Standard Power Speed in Megahertz S 70V3599 4Mbit (128K x 36-Bit) Synchronous Dual-Port RAM 70V3589 2Mbit (64K x 36-Bit) Synchronous Dual-Port RAM 5617 drw 22 IDT Clock Solution for IDT70V3599/89 Dual-Port Dual-Port I/O Specitications IDT Dual-Port Part Number Voltage 3.3/2.5 I/O LVTTL Input Capacitance 8pF Clock Specifications Input Duty Cycle Requirement 40% Maximum Frequency 166 Jitter Tolerance 75ps IDT PLL Clock Device IDT5V2528 5617 tbl16a 70V3599/89 6.42 22 IDT70V3599/89S High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges Datasheet Document History: 6/2/00: 7/12/00: 7/30/01: 11/20/01: Initial Public Offering Added mux to functional block diagram Page 20 Changed maximum value for JTAG AC Electrical Characteristics for tJCD from 20ns to 25ns Page 9 Added Industrial Temperature DC Parameters Page 2, 3 & 4 Added date revision for pin configurations Page 11 Changed tOE value in AC Electrical Characteristics, please refer to Errata #SMEN-01-05 Page 1 & 22 Replaced TM logo with ® logo Page 10 Changed AC Test Conditions Input Rise/Fall Times Consolidated multiple devices into one datasheet Page 1 & 5 Added DCD capability for Pipelined Outputs Page 7 Clarified TBIAS and added TJN Page 9 Changed DC Electrical Parameters Page 11 Removed Clock Rise & Fall Time from AC Electrical Characteristics Table Removed Preliminary status Page 11 Added Byte Enable SetupTime & Byte Enable Hold Time to AC Elecctrical Characteristics Table Page 22 Added IDT Clock Solution Table 7/1/02: 05/19/03: CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-5166 fax: 408-492-8674 www.idt.com for Tech Support: 831-754-4613 DualPortHelp@idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 23