HA5023EVAL

® HA5023 Data Sheet June 2, 2006 FN3393.8 Dual 125MHz Video Current Feedback Amplifier The HA5023 is a wide bandwidth high slew rate dual amplifier optimized for video applications and gains between 1 and 10. It is a current feedback amplifier and thus yields less bandwidth degradation at high closed loop gains than voltage feedback amplifiers. The low differential gain and phase, 0.1dB gain flatness, and ability to drive two back terminated 75Ω cables, make this amplifier ideal for demanding video applications. The current feedback design allows the user to take advantage of the amplifier’s bandwidth dependency on the feedback resistor. By reducing RF, the bandwidth can be increased to compensate for decreases at higher closed loop gains or heavy output loads. The performance of the HA5023 is very similar to the popular Intersil HA-5020. Features • Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . 125MHz • Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475V/µs • Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . 800µV • Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03% • Differential Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03° • Supply Current (per Amplifier) . . . . . . . . . . . . . . . . 7.5mA • ESD Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V • Guaranteed Specifications at ±5V Supplies • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Video Gain Block • Video Distribution Amplifier/RGB Amplifier • Flash A/D Driver Ordering Information PART NUMBER HA5023IP HA5023IPZ (Note) HA5023IB HA5023IB96 HA5023IBZ (Note) PART TEMP. MARKING RANGE (°C) HA5023IP HA5023IPZ 5023I 5023I 5023IBZ -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 8 Ld PDIP 8 Ld PDIP* (Pb-free) 8 Ld SOIC PKG. DWG. # E8.3 E8.3 M8.15 • Current to Voltage Converter • Medical Imaging • Radar and Imaging Systems • Video Switching and Routing Pinout HA5023 (PDIP, SOIC) TOP VIEW OUT1 -IN1 +IN1 V1 2 3 4 8 V+ OUT2 -IN2 +IN2 8 Ld SOIC M8.15 Tape and Reel 8 Ld SOIC (Pb-free) M8.15 HA5023IBZ96 5023IBZ (Note) HA5023EVAL M8.15 8 Ld SOIC Tape and Reel (Pb-free) -+ +- 7 6 5 High Speed Op Amp DIP Evaluation Board *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1998, 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HA5023 Absolute Maximum Ratings Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . .36V DC Input Voltage (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . ±VSUPPLY Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V Output Current (Note 4) . . . . . . . . . . . . . . . . . Short Circuit Protected ESD Rating (Note 3) Human Body Model (Per MIL-STD-883 Method 3015.7). . . 2000V Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . ±4.5V to ±15V Thermal Information Thermal Resistance (Typical, Note 2) θJA (°C/W) PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Note 1) . . . . . . . . . . . . . . . . . 175°C Maximum Junction Temperature (Plastic Package, Note 1) . . 150°C Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation, including output load, must be designed to maintain junction temperature below 175°C for die, and below 150°C for plastic packages. See Application Information section for safe operating area information. 2. θJA is measured with the component mounted on an evaluation PC board in free air. 3. The non-inverting input of unused amplifiers must be connected to GND. 4. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle) output current should not exceed 15mA for maximum reliability. Electrical Specifications VSUPPLY = ±5V, RF = 1kΩ, AV = +1, RL = 400Ω, CL ≤ 10pF, Unless Otherwise Specified (NOTE 9) TEST LEVEL TEMP. (°C) PARAMETER INPUT CHARACTERISTICS Input Offset Voltage (VIO) TEST CONDITIONS MIN TYP MAX UNITS A A 25 Full Full Full 25 Full 25 Full Full 25 Full 25 Full 25 Full 25, 85 -40 25, 85 -40 53 50 60 55 ±2.5 - 0.8 1.2 5 3 4 10 6 10 3 5 3.5 8 20 0.15 0.5 0.1 0.3 12 30 15 30 mV mV mV µV/°C dB dB dB dB V µA µA µA/V µA/V µA/V µA/V µA µA µA µA Delta VIO Between Channels Average Input Offset Voltage Drift VIO Common Mode Rejection Ratio Note 5 A B A A VIO Power Supply Rejection Ratio ±3.5V ≤ VS ≤ ±6.5V A A Input Common Mode Range Non-Inverting Input (+IN) Current Note 5 A A A +IN Common Mode Rejection (+IBCMR = 1 ) +RIN +IN Power Supply Rejection Note 5 A A ±3.5V ≤ VS ≤ ±6.5V A A Inverting Input (-IN) Current A A Delta -IN BIAS Current Between Channels A A 2 FN3393.8 June 2, 2006 HA5023 Electrical Specifications VSUPPLY = ±5V, RF = 1kΩ, AV = +1, RL = 400Ω, CL ≤ 10pF, Unless Otherwise Specified (Continued) (NOTE 9) TEST LEVEL A A -IN Power Supply Rejection ±3.5V ≤ VS ≤ ±6.5V A A Input Noise Voltage +Input Noise Current -Input Noise Current TRANSFER CHARACTERISTICS Transimpedence Note 11 A A Open Loop DC Voltage Gain RL = 400Ω, VOUT = ±2.5V A A Open Loop DC Voltage Gain RL = 100Ω, VOUT = ±2.5V A A OUTPUT CHARACTERISTICS Output Voltage Swing RL = 150Ω A A Output Current Output Current, Short Circuit POWER SUPPLY CHARACTERISTICS Supply Voltage Range Quiescent Supply Current AC CHARACTERISTICS (AV = +1) Slew Rate Full Power Bandwidth Rise Time Fall Time Propagation Delay Overshoot -3dB Bandwidth Settling Time to 1% Settling Time to 0.25% VOUT = 100mV 2V Output Step 2V Output Step Note 6 Note 7 Note 8 Note 8 Note 8 B B B B B B B B B 25 25 25 25 25 25 25 25 25 275 22 350 28 6 6 6 4.5 125 50 75 V/µs MHz ns ns ns % MHz ns ns A A 25 Full 5 7.5 15 10 V mA/Op Amp RL = 150Ω VIN = ±2.5V, VOUT = 0V B A 25 Full Full Full ±2.5 ±2.5 ±16.6 ±40 ±3.0 ±3.0 ±20.0 ±60 V V mA mA 25 Full 25 Full 25 Full 1.0 0.85 70 65 50 45 MΩ MΩ dB dB dB dB f = 1kHz f = 1kHz f = 1kHz B B B TEMP. (°C) 25 Full 25 Full 25 25 25 PARAMETER -IN Common Mode Rejection TEST CONDITIONS Note 5 MIN - TYP 4.5 2.5 25.0 MAX 0.4 1.0 0.2 0.5 - UNITS µA/V µA/V µA/V µA/V nV/√Hz pA/√Hz pA/√Hz 3 FN3393.8 June 2, 2006 HA5023 Electrical Specifications VSUPPLY = ±5V, RF = 1kΩ, AV = +1, RL = 400Ω, CL ≤ 10pF, Unless Otherwise Specified (Continued) (NOTE 9) TEST LEVEL TEMP. (°C) PARAMETER AC CHARACTERISTICS (AV = +2, RF = 681Ω) Slew Rate Full Power Bandwidth Rise Time Fall Time Propagation Delay Overshoot -3dB Bandwidth Settling Time to 1% Settling Time to 0.25% Gain Flatness TEST CONDITIONS MIN TYP MAX UNITS Note 6 Note 7 Note 8 Note 8 Note 8 B B B B B B 25 25 25 25 25 25 25 25 25 25 25 - 475 26 6 6 6 12 95 50 100 0.02 0.07 - V/µs MHz ns ns ns % MHz ns ns dB dB VOUT = 100mV 2V Output Step 2V Output Step 5MHz 20MHz B B B B B AC CHARACTERISTICS (AV = +10, RF = 383Ω) Slew Rate Full Power Bandwidth Rise Time Fall Time Propagation Delay Overshoot -3dB Bandwidth Settling Time to 1% Settling Time to 0.1% VIDEO CHARACTERISTICS Differential Gain (Note 10) Differential Phase (Note 10) NOTES: 5. VCM = ±2.5V. At -40°C Product is tested at VCM = ±2.25V because Short Test Duration does not allow self heating. 6. VOUT switches from -2V to +2V, or from +2V to -2V. Specification is from the 25% to 75% points. Slew Rate 7. FPBW = ---------------------------- ; V = 2V . 2 π V PEAK PEAK 8. RL = 100Ω, VOUT = 1V. Measured from 10% to 90% points for rise/fall times; from 50% points of input and output for propagation delay. 9. A. Production Tested; B. Typical or Guaranteed Limit based on characterization; C. Design Typical for information only. 10. Measured with a VM700A video tester using an NTC-7 composite VITS. 11. VOUT = ±2.5V. At -40°C Product is tested at VOUT = ±2.25V because Short Test Duration does not allow self heating. RL = 150Ω RL = 150Ω B B 25 25 0.03 0.03 % ° VOUT = 100mV 2V Output Step 2V Output Step Note 6 Note 7 Note 8 Note 8 Note 8 B B B B B B B B B 25 25 25 25 25 25 25 25 25 350 28 475 38 8 9 9 1.8 65 75 130 V/µs MHz ns ns ns % MHz ns ns 4 FN3393.8 June 2, 2006 HA5023 Test Circuits and Waveforms + DUT 50Ω HP4195 NETWORK ANALYZER 50Ω FIGURE 1. TEST CIRCUIT FOR TRANSIMPEDANCE MEASUREMENTS (NOTE 12) 100Ω + 50Ω RF, 1kΩ DUT VOUT RL 100Ω VIN 50Ω RI 681Ω RF, 681Ω + (NOTE 12) 100Ω VIN DUT VOUT RL 400Ω - - FIGURE 2. SMALL SIGNAL PULSE RESPONSE CIRCUIT NOTE: FIGURE 3. LARGE SIGNAL PULSE RESPONSE CIRCUIT 12. A series input resistor of ≥100Ω is recommended to limit input currents in case input signals are present before the HA5023 is powered up. Vertical Scale: VIN = 100mV/Div., VOUT = 100mV/Div. Horizontal Scale: 20ns/Div. FIGURE 4. SMALL SIGNAL RESPONSE Vertical Scale: VIN = 1V/Div., VOUT = 1V/Div. Horizontal Scale: 50ns/Div. FIGURE 5. LARGE SIGNAL RESPONSE 5 FN3393.8 June 2, 2006 Schematic Diagram V+ R2 800 (One Amplifier of Two) R5 2.5K R10 820 QP8 QP9 QP11 R15 400 R19 400 QP14 R17 280 R18 280 R27 200 R29 9.5 QP19 R31 5 QP1 QN5 QP5 R11 1K QP10 QN12 R24 140 R20 140 QP16 QP20 6 QN8 QP2 R1 60K QN1 QP6 QN6 R12 280 +IN QP4 R3 6K QN2 QN10 D1 QN3 QN4 QP7 QN7 R13 1K R4 800 VR33 800 R9 820 QN9 QN11 FN3393.8 June 2, 2006 QP15 C1 1.4pF QP12 -IN QN13 QP13 R28 20 QP17 QN17 HA5023 C2 1.4pF R25 20 QN15 R21 140 QN21 R32 5 QN19 R30 7 OUT R14 280 QN14 R16 400 R22 280 QN16 R25 140 QN18 R23 400 R26 200 HA5023 Application Information Optimum Feedback Resistor The plots of inverting and non-inverting frequency response, see Figure 8 and Figure 9 in the typical performance section, illustrate the performance of the HA5023 in various closed loop gain configurations. Although the bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier’s unique relationship between bandwidth and RF. All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier’s bandwidth is inversely proportional to RF. The HA5023 design is optimized for a 1000Ω RF at a gain of +1. Decreasing RF in a unity gain application decreases stability, resulting in excessive peaking and overshoot. At higher gains the amplifier is more stable, so RF can be decreased in a tradeoff of stability for bandwidth. The table below lists recommended RF values for various gains, and the expected bandwidth. GAIN (ACL) -1 +1 +2 +5 +10 -10 RF (Ω) 750 1000 681 1000 383 750 BANDWIDTH (MHz) 100 125 95 52 65 22 traces connected to -IN, and that connections to -IN be kept as short as possible to minimize the capacitance from this node to ground. Driving Capacitive Loads Capacitive loads will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases the oscillation can be avoided by placing an isolation resistor (R) in series with the output as shown in Figure 6. 100Ω VIN RT RI RF + R VOUT CL - FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION RESISTOR, R The selection criteria for the isolation resistor is highly dependent on the load, but 27Ω has been determined to be a good starting value. Power Dissipation Considerations Due to the high supply current inherent in dual amplifiers, care must be taken to insure that the maximum junction temperature (TJ , see Absolute Maximum Ratings) is not exceeded. Figure 7 shows the maximum ambient temperature versus supply voltage for the available package styles (Plastic DIP, SOIC). At ±5VDC quiescent operation both package styles may be operated over the full industrial range of -40°C to 85°C. It is recommended that thermal calculations, which take into account output power, be performed by the designer. MAX AMBIENT TEMPERATURE (°C) 140 130 120 110 100 90 SOIC 80 70 60 50 5 7 9 11 13 15 PDIP PC Board Layout The frequency response of this amplifier depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended. If leaded components are used the leads must be kept short especially for the power supply decoupling components and those components connected to the inverting input. Attention must be given to decoupling the power supplies. A large value (10µF) tantalum or electrolytic capacitor in parallel with a small value (0.1µF) chip capacitor works well in most cases. A ground plane is strongly recommended to control noise. Care must also be taken to minimize the capacitance to ground seen by the amplifier’s inverting input (-IN). The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. It is recommended that the ground plane be removed under SUPPLY VOLTAGE (±V) FIGURE 7. MAXIMUM OPERATING AMBIENT TEMPERATURE vs SUPPLY VOLTAGE 7 FN3393.8 June 2, 2006 HA5023 Typical Performance Curves 5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 2 10 FREQUENCY (MHz) 100 200 -5 2 10 FREQUENCY (MHz) 100 200 AV = 10, RF = 383Ω VOUT = 0.2VP-P CL = 10pF AV = +1, RF = 1kΩ AV = 2, RF = 681Ω AV = 5, RF = 1kΩ NORMALIZED GAIN (dB) VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, Unless Otherwise Specified 5 4 3 2 1 0 -1 -2 -3 -4 AV = -10 AV = -5 AV = -2 VOUT = 0.2VP-P CL = 10pF RF = 750Ω AV = -1 FIGURE 8. NON-INVERTING FREQENCY RESPONSE FIGURE 9. INVERTING FREQUENCY RESPONSE -3dB BANDWIDTH (MHz) 140 VOUT = 0.2VP-P CL = 10pF AV = +1 0 NONINVERTING PHASE (°) -45 -90 -135 -100 -225 -270 -315 -360 2 VOUT = 0.2VP-P CL = 10pF 10 AV = -1, RF = 750Ω AV = +10, RF = 383Ω AV = +1, RF = 1kΩ 180 135 90 45 0 -45 INVERTING PHASE (°) 130 AV = -10, RF = 750Ω -90 -135 -180 100 200 5 GAIN PEAKING 500 700 900 1100 1300 FEEDBACK RESISTOR (Ω) 0 1500 FREQUENCY (MHz) FIGURE 10. PHASE RESPONSE AS A FUNCTION OF FREQUENCY -3dB BANDWIDTH (MHz) 100 VOUT = 0.2VP-P CL = 10pF AV = +2 95 -3dB BANDWIDTH GAIN PEAKING (dB) 90 10 FIGURE 11. BANDWIDTH AND GAIN PEAKING vs FEEDBACK RESISTANCE 130 -3dB BANDWIDTH (MHz) 120 -3dB BANDWIDTH 110 6 GAIN PEAKING (dB) 100 4 5 90 GAIN PEAKING GAIN PEAKING 350 500 650 800 950 0 1100 80 0 200 400 600 VOUT = 0.2VP-P CL = 10pF AV = +1 800 2 0 1000 FEEDBACK RESISTOR (Ω) LOAD RESISTOR (Ω) FIGURE 12. BANDWIDTH AND GAIN PEAKING vs FEEDBACK RESISTANCE FIGURE 13. BANDWIDTH AND GAIN PEAKING vs LOAD RESISTANCE 8 FN3393.8 June 2, 2006 GAIN PEAKING (dB) 120 -3dB BANDWIDTH 10 HA5023 Typical Performance Curves 80 VOUT = 0.2VP-P CL = 10pF AV = +10 60 OVERSHOOT (%) 12 VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, Unless Otherwise Specified (Continued) 16 VOUT = 0.1VP-P CL = 10pF VSUPPLY = ±5V, AV = +2 -3dB BANDWIDTH (MHz) 40 6 VSUPPLY = ±15V, AV = +2 VSUPPLY = ±5V, AV = +1 VSUPPLY = ±15V, AV = +1 20 0 200 350 500 650 800 950 FEEDBACK RESISTOR (Ω) 0 0 200 400 600 LOAD RESISTANCE (Ω) 800 1000 FIGURE 14. BANDWIDTH vs FEEDBACK RESISTANCE FIGURE 15. SMALL SIGNAL OVERSHOOT vs LOAD RESISTANCE 0.10 FREQUENCY = 3.58MHz DIFFERENTIAL PHASE (°) DIFFERENTIAL GAIN (%) 0.08 RL = 75Ω 0.08 FREQUENCY = 3.58MHz 0.06 0.06 RL = 150Ω 0.04 0.04 RL = 150Ω RL = 75Ω 0.02 RL = 1kΩ 0.00 0.02 RL = 1kΩ 0.00 3 5 7 9 11 13 15 SUPPLY VOLTAGE (±V) 3 5 7 9 11 SUPPLY VOLTAGE (±V) 13 15 FIGURE 16. DIFFERENTIAL GAIN vs SUPPLY VOLTAGE FIGURE 17. DIFFERENTIAL PHASE vs SUPPLY VOLTAGE -40 VOUT = 2.0VP-P CL = 30pF HD2 -60 3RD ORDER IMD -70 HD2 HD3 -80 HD3 -90 0.3 1 FREQUENCY (MHz) 10 REJECTION RATIO (dB) -50 DISTORTION (dBc) 0 -10 -20 -30 -40 -50 -60 -70 -80 0.001 AV = +1 CMRR NEGATIVE PSRR POSITIVE PSRR 0.01 0.1 FREQUENCY (MHz) 1 10 30 FIGURE 18. DISTORTION vs FREQUENCY FIGURE 19. REJECTION RATIOS vs FREQUENCY 9 FN3393.8 June 2, 2006 HA5023 Typical Performance Curves 8.0 VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, Unless Otherwise Specified (Continued) 12 RLOAD = 100Ω VOUT = 1.0VP-P PROPAGATION DELAY (ns) 10 AV = +10, RF = 383Ω PROPAGATION DELAY (ns) RL = 100Ω VOUT = 1.0VP-P AV = +1 7.5 7.0 8 AV = +2, RF = 681Ω 6 AV = +1, RF = 1kΩ 6.5 6.0 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) 4 3 5 7 9 11 SUPPLY VOLTAGE (±V) 13 15 FIGURE 20. PROPAGATION DELAY vs TEMPERATURE FIGURE 21. PROPAGATION DELAY vs SUPPLY VOLTAGE 500 VOUT = 2VP-P 450 400 SLEW RATE (V/µs) 350 300 250 200 150 100 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) - SLEW RATE + SLEW RATE NORMALIZED GAIN (dB) 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 5 10 15 20 FREQUENCY (MHz) 25 30 AV = +10, RF = 383Ω AV = +1, RF = 1kΩ AV = +5, RF = 1kΩ AV = +2, RF = 681Ω VOUT = 0.2VP-P CL = 10pF FIGURE 22. FIGURE 22. SLEW RATE vs TEMPERATURE FIGURE 23. NON-INVERTING GAIN FLATNESS vs FREQUENCY 0.8 0.6 NORMALIZED GAIN (dB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 5 10 15 20 25 30 FREQUENCY (MHz) AV = -10 AV = -2 AV = -5 AV = -1 VOUT = 0.2VP-P CL = 10pF RF = 750Ω 100 AV = +10, RF = 383Ω VOLTAGE NOISE (nV/√Hz) 80 -INPUT NOISE CURRENT 1000 800 60 +INPUT NOISE CURRENT 40 INPUT NOISE VOLTAGE 20 600 400 200 0 0.01 0.1 1 FREQUENCY (kHz) 10 0 100 FIGURE 24. INVERTING GAIN FLATNESS vs FREQUENCY FIGURE 25. INPUT NOISE CHARACTERISTICS 10 FN3393.8 June 2, 2006 CURRENT NOISE (pA/√Hz) HA5023 Typical Performance Curves 1.5 VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, Unless Otherwise Specified (Continued) 2 1.0 VIO (mV) BIAS CURRENT (µA) -40 -20 0 20 40 60 80 100 120 140 0 0.5 -2 0.0 -60 -4 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 26. INPUT OFFSET VOLTAGE vs TEMPERATURE FIGURE 27. +INPUT BIAS CURRENT vs TEMPERATURE 22 4000 TRANSIMPEDANCE (kΩ) -40 -20 0 20 40 60 80 100 120 140 BIAS CURRENT (µA) 20 3000 18 2000 16 -60 1000 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 28. -INPUT BIAS CURRENT vs TEMPERATURE FIGURE 29. TRANSIMPEDANCE vs TEMPERATURE 25 74 72 REJECTION RATIO (dB) 125°C +PSRR 20 55°C 70 68 66 64 62 60 58 -100 CMRR -PSRR ICC (mA) 15 10 25°C 5 3 4 5 6 7 8 9 10 11 12 13 14 15 -50 0 50 100 150 200 250 SUPPLY VOLTAGE (±V) TEMPERATURE (°C) FIGURE 30. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 31. REJECTION RATIO vs TEMPERATURE 11 FN3393.8 June 2, 2006 HA5023 Typical Performance Curves 40 VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, Unless Otherwise Specified (Continued) 4.0 SUPPLY CURRENT (mA) +5V OUTPUT SWING (V) 30 +10V +15V 20 3.8 10 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3.6 -60 -40 -20 0 20 40 60 80 100 120 140 DISABLE INPUT VOLTAGE (V) TEMPERATURE (°C) FIGURE 32. SUPPLY CURRENT vs DISABLE INPUT VOLTAGE 30 FIGURE 33. OUTPUT SWING vs TEMPERATURE 1.2 VCC = ±15V 20 VOUT (VP-P) VIO (mV) 10.00 1.1 VCC = ±10V 10 1.0 0.9 VCC = ±4.5V 0 0.01 0.10 1.00 LOAD RESISTANCE (kΩ) 0.8 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) FIGURE 34. OUTPUT SWING vs LOAD RESISTANCE FIGURE 35. INPUT OFFSET VOLTAGE CHANGE BETWEEN CHANNELS vs TEMPERATURE -30 1.5 AV = +1 VOUT = 2VP-P -40 ∆BIAS CURRENT (µA) 1.0 SEPARATION (dB) -40 -20 0 20 40 60 80 100 120 140 -50 -60 0.5 -70 0.0 -60 -80 0.1 TEMPERATURE (°C) 1 FREQUENCY (MHz) 10 30 FIGURE 36. INPUT BIAS CURRENT CHANGE BETWEEN CHANNELS vs TEMPERATURE FIGURE 37. CHANNEL SEPARATION vs FREQUENCY 12 FN3393.8 June 2, 2006 HA5023 Typical Performance Curves VSUPPLY = ±5V, AV = +1, RF = 1kΩ, RL = 400Ω, TA = 25°C, Unless Otherwise Specified (Continued) 0 -10 FEEDTHROUGH (dB) -20 -30 -40 -50 -60 -70 -80 0.1 DISABLE = 0V VIN = 5VP-P RF = 750Ω TRANSIMPEDANCE (MΩ) 10 1 0.1 0.01 0.001 180 135 90 45 0 -45 -90 PHASE ANGLE (°) RL = 100Ω 1 FREQUENCY (MHz) 10 20 0.001 0.01 0.1 1 FREQUENCY (MHz) 10 100 -135 FIGURE 38. DISABLE FEEDTHROUGH vs FREQUENCY FIGURE 39. TRANSIMPEDANCE vs FREQUENCY TRANSIMPEDANCE (MΩ) 10 1 0.1 0.01 0.001 180 135 90 45 0 -45 -90 0.001 0.01 0.1 1 10 FREQUENCY (MHz) 100 -135 PHASE ANGLE (°) RL = 400Ω FIGURE 40. TRANSIMPEDENCE vs FREQUENCY 13 FN3393.8 June 2, 2006 HA5023 Die Characteristics DIE DIMENSIONS: 1650µm x 2540µm x 483µm METALLIZATION: Type: Metal 1: AlCu (1%) Thickness: Metal 1: 8kÅ ±0.4kÅ Type: Metal 2: AlCu (1%) Thickness: Metal 2: 16kÅ ±0.8kÅ SUBSTRATE POTENTIAL (Powered Up): VPASSIVATION: Type: Nitride Thickness: 4kÅ ±0.4kÅ TRANSISTOR COUNT: 124 PROCESS: High Frequency Bipolar Dielectric Isolation Metallization Mask Layout HA5023 OUT NC V+ -IN1 +IN1 NC OUT2 NC V- +IN -IN 14 FN3393.8 June 2, 2006 HA5023 Dual-In-Line Plastic Packages (PDIP) N INDEX AREA E1 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 -CA2 L A C L E E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E E1 e eA eB L N eA eC C A BS C MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280 e A1 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 - 2.54 BSC 7.62 BSC 10.92 3.81 8 2.93 15 FN3393.8 June 2, 2006 HA5023 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45° H 0.25(0.010) M BM M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 L MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8° 0° 8° MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0° MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050 B C D E e H C α A1 0.10(0.004) 0.050 BSC 1.27 BSC e B 0.25(0.010) M C AM BS h L N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN3393.8 June 2, 2006