ISL28272FAZ-T7

® ISL28271, ISL28272 Data Sheet December 8, 2006 FN6390.0 Dual Micropower, Single Supply, Rail-toRail Input and Output (RRIO) Instrumentation Amplifier The ISL28271 and ISL28272 are dual micropower instrumentation amplifiers (in-amps) optimized for low 2.4V to 5V single supplies. Both devices feature an Input Range Enhancement Circuit (IREC) which maintains CMRR performance for input voltages equal to the positive and negative supply rails. The input signal is capable of swinging 10% above the positive supply rail and to 100mV below the negative supply with only a slight degradation of the CMRR performance. The output operation is rail to rail. The ISL28271 is compensated for a minimum gain of 10 or more. For higher gain applications, the ISL28272 is compensated for a minimum gain of 100. The in-amps have CMOS input devices for maximum input common voltage range. The amplifiers can be operated from one lithium cell or two Ni-Cd batteries. Features • 120µA typical supply current for both channels • 30pA max input bias current • 100dB CMRR, PSRR • 0.7µV/°C offset voltage temperature coefficient • 180kHz 3dB Bandwidth - ISL28271 • 100kHz 3dB Bandwidth - ISL28272 • 0.5V/µs slew rate • Single supply operation • Rail-to-rail input and output (RRIO) • Input is capable of swinging above V+ and below V(ground sensing) • 0.081%1 typical gain error - ISL28271 • -0.19%1 typical gain error - ISL28272 • Pb-free plus anneal available (RoHS compliant) Ordering Information PART NUMBER (Note) ISL28271FAZ (Note) ISL28271FAZ-T7 (Note) ISL28272FAZ (Note) ISL28272FAZ-T7 (Note) PART MARKING 28271 FAZ 28271 FAZ 28272 FAZ 28272 FAZ TAPE & REEL 97/Tube PACKAGE (Pb-Free) PKG. DWG. # Applications • Battery- or solar-powered systems • Strain gauge • Sensor signal conditioning • Medical devices • Industrial instrumentations 16 Ld QSOP MDP0040 (Pb-free) 7” 16 Ld QSOP MDP0040 (1000 pcs) (Pb-free) 97/Tube 16 Ld QSOP MDP0040 (Pb-free) Pinout ISL28271, ISL28272 (16 LD QSOP) TOP VIEW NC 1 OUT_A 2 FB+_A 3 FB-_A 4 IN-_A 5 IN+_A 6 EN_A 7 V- 8 +-+ 16 V+ 15 OUT_B 14 FB+_B 13 FB-_B 12 IN-_B 11 IN+_B 10 EN_B 9 NC 7” 16 Ld QSOP MDP0040 (1000 pcs) (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL28271, ISL28272 Absolute Maximum Ratings (TA = +25°C) Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/μs Input Current (IN, FB) ISL28272 . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage (IN, FB) ISL28272 . . . . . . . . . . . . . . . 0.5V Input Current (IN, FB) ISL28271 . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input (IN, FB) Voltage ISL28271 . . . . . . . . . . . . . . . 1.0V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V ESD tolerance, Human Body Model . . . . . . . . . . . . . . . . . . . . . .3kV ESD tolerance, Machine Model . . . . . . . . . . . . . . . . . . . . . . . . .300V Thermal Information Thermal Resistance θJA (°C/W) 16 Ld QSOP Package . . . . . . . . . . . . . . . . . . . . . . . 112 Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . .-40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . +125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VOS V+ = +5V, V- = GND, VFB+ = 1/2V+, TA = +25°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. CONDITIONS ISL28271 ISL28272 MIN -600 -1200 -500 -750 TYP ±35 DESCRIPTION Input Offset Voltage MAX 600 1200 500 750 UNIT µV µV µV/°C ±35 TCVOS IOS IB eN Input Offset Voltage Temperature Coefficient -40°C to +125°C Input Offset Current between IN+ and IN-, and between FB+ and FBInput Bias Current (IN+, IN-, FB+, and FB- terminals) Input Noise Voltage See graphs for extended temperature range -40°C to +85°C See graphs for extended temperature range -40°C to +85°C ISL28271 ISL28272 Input Noise Voltage Density ISL28271 ISL28272 fo = 1kHz f = 0.1Hz to 10Hz -30 -80 -30 -80 0.7 ±5 ±10 10 6 240 78 fo = 1kHz 0.92 0.2 1 V+ = 2.4V to 5.0V ISL28271 ISL28272 VCM = 0V to 5V 0 80 70 80 75 80 75 RL = 100kΩ to 2.5V 100 100 100 +0.081 -0.19 V+ 30 80 30 80 pA pA µVP-P µVP-P nV/√Hz nV/√Hz pA/√Hz pA/√Hz GΩ V dB dB dB % iN Input Noise Current Density ISL28271 ISL28272 RIN VIN CMRR Input Resistance Input Voltage Range Common Mode Rejection Ratio PSRR EG Power Supply Rejection Ratio Gain Error V+ = 2.4V to 5V ISL28271 ISL28272 2 FN6390.0 December 8, 2006 ISL28271, ISL28272 Electrical Specifications PARAMETER VOUT V+ = +5V, V- = GND, VFB+ = 1/2V+, TA = +25°C, unless otherwise specified. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) CONDITIONS Output low, RL = 100kΩ Output low, RL = 1kΩ Output high, RL = 100kΩ Output high, RL = 1kΩ SR -3db BW Slew Rate -3dB Bandwidth RL = 1kΩ to GND RL = 10kΩ ISL28271 ISL28272 IS,EN IS,DIS VINH VINL IENH IENL V+ ISC+ ISCSupply Current, Enabled Supply Current, Disabled EN Enable Pin High Level EN Enable Pin Low Level EN Input Current High EN Input Current Low Minimum Supply Voltage Short Circuit Output Current Short Circuit Output Current V+ = 5V, RL = 10Ω V+ = 5V, RL = 10Ω EN = V+ EN = V2.4 28 25 24 20 31 26 0.8 26 Both A and B channels enabled, EN = VBoth A and B channels disabled, EN = V+ 2 0.8 1 1.3 50 100 4.980 4.980 4.85 4.80 0.4 0.35 MIN TYP 3 130 4.99 4.88 0.5 180 100 120 4 156 200 7 9 0.7 0.75 MAX 6 30 175 225 UNIT mV mV V V V/µs kHz kHz µA µA V V µA nA V mA mA DESCRIPTION Maximum Voltage Swing 3 FN6390.0 December 8, 2006 ISL28271, ISL28272 Typical Performance Curves 70 60 50 GAIN (dB) 40 30 20 10 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) GAIN = 1000 GAIN = 500 GAIN = 200 GAIN = 100 GAIN = 50 GAIN = 20 GAIN = 10 40 30 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M GAIN (dB) VCM = 5V VOUT = 10mVPP RL = 10k 90 GAIN = 10,000 80 GAIN = 5,000 70 60 50 GAIN = 2,000 GAIN = 1,000 GAIN = 500 GAIN = 200 GAIN = 100 VCM = 5V VOUT = 10mVPP RL = 10k FIGURE 1. ISL28271 FREQUENCY RESPONSE vs CLOSED LOOP GAIN. V+ = VCM = 5V FIGURE 2. ISL28272 FREQUENCY RESPONSE vs CLOSED LOOP GAIN. VCM = V+ 70 60 50 GAIN (dB) 40 30 20 10 GAIN = 1000 GAIN = 500 GAIN = 200 GAIN = 100 GAIN = 50 GAIN = 20 GAIN = 10 VCM = 2.5V VOUT = 10mVPP RL = 10k GAIN (dB) 90 GAIN = 10,000 80 GAIN = 5,000 70 60 50 40 30 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M GAIN = 2,000 GAIN = 1,000 GAIN = 500 GAIN = 200 GAIN = 100 VCM = 2.5V VOUT = 10mVPP RL = 10k 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 3. ISL28271 FREQUENCY RESPONSE vs CLOSED LOOP GAIN. V+ = 5V, VCM = 1/2V+ FIGURE 4. ISL28272 FREQUENCY RESPONSE vs CLOSED LOOP GAIN. VCM = 1/2V+ 70 60 50 GAIN (dB) 40 30 20 10 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M GAIN = 1000 GAIN = 500 GAIN = 200 GAIN = 100 GAIN = 50 GAIN = 20 GAIN = 10 VCM = +10mV VOUT = 10mVPP RL = 10k 90 GAIN = 10,000 80 GAIN = 5,000 70 60 50 40 30 1 10 100 1k 10k FREQUENCY (Hz) 100k 1M VCM = +10mV VOUT = 10mVPP RL = 10k GAIN (dB) GAIN = 2,000 GAIN = 1,000 GAIN = 500 GAIN = 200 GAIN = 100 FIGURE 5. ISL28271 FREQUENCY RESPONSE vs CLOSED LOOP GAIN. V+ = 5V, VCM = 10mV FIGURE 6. ISL28272 FREQUENCY RESPONSE vs CLOSED LOOP GAIN. VCM = V- 4 FN6390.0 December 8, 2006 ISL28271, ISL28272 Typical Performance Curves (Continued) 25 V S = 5V VS = 2.4V 45 40 35 30 GAIN (dB) 25 20 15 10 5 0 1k 10k 100k 1M FREQUENCY (Hz) AV = 100 RL = 10kΩ CL = 10pF RF/RG = 100 RF = 10kΩ RG = 100Ω 10 100 1k 10k 100k 1M FREQUENCY (Hz) VS = 2.4V VS = 5V 20 GAIN (dB) 15 10 AV = 10 RL = 10kΩ CL = 10pF 5 RF/RG = 10 RF = 1 k Ω RG = 100Ω 0 10 100 FIGURE 7. ISL28271 FREQUENCY RESPONSE vs SUPPLY VOLTAGE FIGURE 8. ISL28272 FREQUENCY RESPONSE vs SUPPLY VOLTAGE 25 820pF 470pF 20 220pF GAIN (dB) GAIN (dB) 50 45 2200pF 1200pF 40 820pF AV = 100 R = 10kΩ CL = 10pF RF/RG = 100 RF = 10kΩ RG = 100Ω 10 100 1k 10k 100k FREQUENCY (Hz) 56pF 15 AV = 10 R = 10kΩ CL = 10pF RF/RG = 10 RF = 1kΩ RG = 100Ω 10 100 1k 10k 100k 100pF 35 10 30 5 25 1M FREQUENCY (Hz) 1M FIGURE 9. ISL28271 FREQUENCY RESPONSE vs CLOAD FIGURE 10. ISL28272 FREQUENCY RESPONSE vs CLOAD 90 80 70 60 CMRR (dB) 50 40 30 20 10 0 -10 10 100 1k 10k 100k 1M AV = 10 CMRR (dB) 120 100 80 60 AV = 100 40 20 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 11. ISL28271 CMRR vs FREQUENCY FIGURE 12. ISL28272 CMRR vs FREQUENCY 5 FN6390.0 December 8, 2006 ISL28271, ISL28272 Typical Performance Curves (Continued) 120 100 80 PSRR (dB) 120 100 PSRR+ PSRR (dB) 80 PSRR+ 60 40 AV = 100 20 0 PSRR- 60 PSRR40 AV = 10 20 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 13. ISL28271 PSRR vs FREQUENCY FIGURE 14. ISL28272 PSRR vs FREQUENCY 1400 INPUT VOLTAGE NOISE (nV/√Hz) INPUT VOLTAGE NOISE (nV/√Hz) 1200 1000 800 600 AV = 10 400 200 0 700 600 500 400 300 200 100 0 1 10 100 1k 10k 100k 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) AV = 100 FIGURE 15. ISL28271 INPUT VOLTAGE NOISE SPECTRAL DENSITY FIGURE 16. ISL28272 INPUT VOLTAGE NOISE SPECTRAL DENSITY 6 CURRENT NOISE (pA/√Hz) CURRENT NOISE (pA/√Hz) 5 4 3 2 1 0 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 1 10 100 1k 10k 100k FREQUENCY (Hz) 1 10 100 1k 10k 100k AV = 100 AV = 10 FREQUENCY (Hz) FIGURE 17. ISL28271 INPUT CURRENT NOISE SPECTRAL DENSITY FIGURE 18. ISL28272 INPUT CURRENT NOISE SPECTRAL DENSITY 6 FN6390.0 December 8, 2006 ISL28271, ISL28272 Typical Performance Curves (Continued) VOLTAGE NOISE (5µV/DIV) TIME (1s/DIV) VOLTAGE NOISE (2µV/DIV) TIME (1s/DIV) FIGURE 19. ISL28271 0.1 Hz TO 10Hz INPUT VOLTAGE NOISE. GAIN = 10 FIGURE 20. ISL28272 0.1 Hz TO 10Hz INPUT VOLTAGE NOISE. GAIN = 100 160 190 SUPPLY CURRENT (µA) 170 150 130 110 MIN 90 70 50 -40 -20 0 20 40 60 80 100 120 MEDIAN n = 3000 MAX SUPPLY CURRENT (µA) 150 140 130 MEDIAN 120 110 100 90 -40 MIN n = 3000 MAX -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 21. ISL28271 SUPPLY CURRENT ENABLED vs TEMPERATURE VS = ±2.5V, VIN = 0V FIGURE 22. ISL28272 SUPPLY CURRENT ENABLED vs TEMPERATURE VS = ±2.5V, VIN = 0V 5.0 n = 3000 SUPPLY CURRENT (µA) 4.5 MAX 7 n = 3000 6 SUPPLY CURRENT (µA) 5 4 3 MEDIAN 2 1 0 -20 0 20 40 60 80 100 120 -40 -20 0 TEMPERATURE (°C) 20 40 60 80 TEMPERATURE (°C) 100 120 MIN MAX 4.0 MEDIAN 3.5 3.0 MIN 2.5 -40 FIGURE 23. ISL28271 SUPPLY CURRENT DISABLED vs TEMPERATURE VS = ±2.5V, VIN = 0V FIGURE 24. ISL28272 SUPPLY CURRENT DISABLED vs TEMPERATURE VS = ±2.5V, VIN = 0V 7 FN6390.0 December 8, 2006 ISL28271, ISL28272 Typical Performance Curves (Continued) 160 150 170 140 CMRR (dB) 130 120 110 100 90 80 70 -40 -20 0 20 40 60 80 100 120 70 -40 -20 0 20 40 60 80 100 120 MIN MEDIAN MAX CMRR (dB) 150 130 MEDIAN 110 90 MIN MAX n = 3000 190 n = 3000 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 25. ISL28271 CMRR vs TEMPERATURE VCM = +2.5V TO -2.5V FIGURE 26. ISL28272 CMRR vs TEMPERATURE VCM = +2.5V TO -2.5V 150 140 130 PSRR (dB) MAX 180 n = 3000 160 140 120 MEDIAN 100 80 MIN -20 0 20 40 60 80 100 120 60 -40 -20 0 20 MIN 40 60 80 100 120 n = 3000 MAX 110 100 90 80 70 60 -40 MEDIAN TEMPERATURE (°C) PSRR (dB) 120 TEMPERATURE (°C) FIGURE 27. ISL28271 PSRR vs TEMPERATURE VS = ±1.2V TO ±2.5V FIGURE 28. ISL28272 PSRR vs TEMPERATURE VS = ±1.2V TO ±2.5V 4.91 n = 3000 4.90 MAX 4.89 VOUT (V) VOUT (V) 4.88 4.87 4.86 MIN 4.85 4.84 -40 MEDIAN 4.91 n = 3000 4.90 MAX 4.89 4.88 4.87 4.86 4.85 4.84 -40 MEDIAN MIN -20 0 20 40 60 80 100 120 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 29. ISL28271 VOUT HIGH vs TEMPERATURE RL = 1k, VS = ±2.5V FIGURE 30. ISL28272 VOUT HIGH vs TEMPERATURE RL = 1k, VS = ±2.5V 8 FN6390.0 December 8, 2006 ISL28271, ISL28272 Typical Performance Curves (Continued) 4.9980 4.9975 4.9970 VOUT (V) 4.9965 4.9960 4.9955 4.9950 -40 MIN 4.998 n = 3000 MEDIAN VOUT (V) MAX 4.9975 4.997 4.9965 4.996 4.9955 4.995 -40 MIN n = 3000 MEDIAN MAX -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 31. ISL28271 VOUT HIGH vs TEMPERATURE RL = 100k, VS = ±2.5V FIGURE 32. ISL28272 VOUT HIGH vs TEMPERATURE RL = 100k, VS = ±2.5V 170 n = 3000 160 150 VOUT (mV) 140 130 120 110 100 90 -40 -20 0 20 40 60 80 100 120 MIN MEDIAN VOUT (mV) MAX 180 170 160 150 140 130 120 110 100 90 80 -40 -20 0 20 40 60 80 100 120 MIN MEDIAN n = 3000 MAX TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 33. ISL28271 VOUT LOW vs TEMPERATURE RL = 1k, VS = ±2.5V FIGURE 34. ISL28272 VOUT LOW vs TEMPERATURE RL = 1k, VS = ±2.5V 6.0 5.8 5.6 5.4 VOUT (mV) 5.2 5.0 4.8 4.6 4.4 4.2 4.0 -40 -20 0 20 40 60 80 100 120 MIN MEDIAN VOUT (mV) n = 3000 MAX 6 5.8 5.6 5.4 5.2 5 4.8 4.6 4.4 4.2 4 -40 -20 0 20 40 60 80 100 120 MIN n = 3000 MAX MEDIAN TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 35. ISL28271 VOUT LOW vs TEMPERATURE RL = 100k, VS = ±2.5V FIGURE 36. ISL28272 VOUT LOW vs TEMPERATURE RL = 100k, VS = ±2.5V 9 FN6390.0 December 8, 2006 ISL28271, ISL28272 Pin Descriptions ISL28271 16 Ld QSOP 2, 15 ISL28272 16 Ld QSOP 2, 15 PIN NAME OUT_A,B EQUIVALENT CIRCUIT Circuit 3 PIN FUNCTION Output Voltage. A complementary Class AB common-source output stage drives the output of each channel. When disabled, the outputs are in a high impedance state. Positive Feedback high impedance terminals. ISL28272 input circuit is shown in Circuit 1A, and the ISL28271 input circuit is shown in Circuit 1B. ISL28271: to avoid offset drift, it is recommended that the terminals of the ISL28271 are not overdriven beyond 1V and the input current must never exceed 5mA. 4, 13 4, 13 FB-_A,B Circuit 1A, Circuit 1B Negative Feedback high impedance terminals. The FB- pins connect to an external resistor divider to individually set the desired gain of the in-amp. ISL28272 input circuit is shown in Circuit 1A, and the ISL28271 input circuit is shown in Circuit 1B. ISL28271: to avoid offset drift, it is recommended that the terminals of the ISL28271 are not overdriven beyond 1V and the input current must never exceed 5mA. 5, 12 5, 12 IN-_A,B Circuit 1A, Circuit 1B High impedance Inverting input terminals. Connect to the low side of the input source signal. ISL28272 input circuit is shown in Circuit 1A, and the ISL28271 input circuit is shown in Circuit 1B. ISL28271: to avoid offset drift, it is recommended that the terminals of the ISL28271 are not overdriven beyond 1V and the input current must never exceed 5mA. 6, 11 6, 11 IN+_A,B Circuit 1A, Circuit 1B High impedance Non-inverting input terminals. Connect to the high side of the input source signal. ISL28272 input circuit is shown in Circuit 1A, and the ISL28271 input circuit is shown in Circuit 1B. ISL28271: to avoid offset drift, it is recommended that the terminals of the ISL28271 are not overdriven beyond 1V and the input current must never exceed 5mA. 7, 10 7, 10 EN_A,B Circuit 2 Active LOW logic pins. When pulled above 2V, the corresponding channel turns off and OUT is high impedance. A channel is enabled when pulled below 0.8V. Built-in pull downs define each EN pin LOW when left floating. Positive Supply terminal shared by all channels. Negative Supply terminal shared by all channels. Grounded for single supply operation. No Connect, pins can be left floating or grounded. V+ V+ LOGIC PIN VCIRCUIT 2 V+ INFBIN+ FB+ VCIRCUIT 3 OUT VVCIRCUIT 4 3, 14 3, 14 FB+_A,B Circuit 1A, Circuit 1B 16 8 1, 9 16 8 1, 9 V+ VNC Circuit 4 Circuit 4 V+ INFBIN+ FB+ V- V+ CAPACITIVELY COUPLED ESD CLAMP CIRCUIT 1A CIRCUIT 1B 10 FN6390.0 December 8, 2006 ISL28271, ISL28272 Application Information Product Description The ISL28271 and ISL28272 are dual channel micropower instrumentation amplifiers (in-amps) which deliver rail-to-rail input amplification and rail-to-rail output swing. The in-amps also deliver excellent DC and AC specifications while consuming only about 120µA for both channels. Because the independent pair of feedback terminals set the gain and adjust the output zero level, the ISL28271 and ISL28272 achieve high CMRR regardless of the tolerance of the gain setting resistors. The ISL28271 is internally compensated for a minimum gain of 10. The ISL28272 is internally compensated for a minimum gain of 100. EN pins are available to independently enable or disable a channel. When all channels are off, current consumption is down to typically 4µA. performance charts. IREC also cures the abrupt change and even reverse polarity of the input bias current over the whole range of input. Output Stage and Output Voltage Range A Class AB common-source output stage drives the output. The pair of complementary MOSFET devices drive the output VOUT to within a few millivolts of the supply rails. At a 100kΩ load, the PMOS sources current and pulls the output up to 4mV below the positive supply. The NMOS sinks current and pulls the output down to 4mV above the negative supply, or ground in the case of a single supply operation. The current sinking and sourcing capability are internally limited to 31mA. When disabled, the outputs are in a high impedance state. Gain Setting VIN, the potential difference across IN+ and IN-, is replicated (less the input offset voltage) across FB+ and FB-. The function of the in-amp is to maintain the differential voltage across FB- and FB+ equal to IN+ and IN-; (FB- - FB+) = (IN+ - IN-). Consequently, the transfer function can be derived. The in-amp gain is set by two external resistors, the feedback resistor RF, and the gain resistor RG. 2.4V to 5V EN Input Protection All input terminals and feedback terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. Input signals originating from low impedance sources should have current limiting resistors in series with the IN+ and IN- pins to prevent damaging currents during power supply sequencing and other transient conditions. The ISL28272 has additional back-to-back diodes across the input terminals and also across the feedback terminals. If overdriving the inputs is necessary, the external input current must never exceed 5mA. External series resistors may be used as an external protection to limit excessive external voltage and current from damaging the inputs. On the other hand, the ISL28271 has no clamps to limit the differential voltage on the input terminals allowing higher differential input voltages at lower gain applications. It is recommended however, that the terminals of the ISL28271 are not overdriven beyond 1V to avoid offset drift. IN+ IN+ IN- V+ + - EN IN- FB+ FB- VOUT + VISL28271 ISL28272 VCM RG RF Input Stage and Input Voltage Range The input terminals (IN+ and IN-) of the in-amps are a single differential pair of CMOS devices aided by an Input Range Enhancement Circuit, IREC, to increase the headroom of operation of the common-mode input voltage. The feedback terminals (FB+ and FB-) also have a similar topology. As a result, the input common-mode voltage range is rail-to-rail regardless of the feedback terminal settings and regardless of the gain settings. They are able to handle input voltages that are at or slightly beyond the supply and ground sensing making these in-amps well suited for single 5V down to 2.4V supply systems. The IREC enables rail-to-rail input amplification without the problems usually associated with the dual differential stage topology. The IREC ensures that there are no drastic changes in offset voltage over the entire range of the input. See Input Offset Voltage vs Common-Mode Input Voltage in FIGURE 37. GAIN IS SET BY TWO EXTERNAL RESISTORS, RF AND RG VIN = IN+ – INRF ⎞ ⎛ VOUT = ⎜ 1 + ------- ⎟ VIN R G⎠ ⎝ (EQ. 1) In Figure 37, the FB+ pin and one end of resistor RG are connected to GND. With this configuration, the above gain equation (Equation 1) is only true for a positive swing in VIN; negative input swings will be ignored because the output will be at ground. Reference Connection Unlike a three op-amp in-amp realization, a finite series resistance seen at the REF terminal does not degrade the high CMRR performance eliminating the need for an 11 FN6390.0 December 8, 2006 ISL28271, ISL28272 additional external buffer amplifier. Figure 38 uses the FB+ pin to provide a high impedance REF terminal. VIN = IN+ – INRS + RF VOUT = 1 + --------------------- + VREF RG 2.4V to 5V EN (EQ. 3) IN+ IN+ ININ2.9V to 5V VCM R1 REF R2 RG FB+ FB+ - V+ EN RF ⎞ ⎛ VOUT = ⎜ 1 + ------- ⎟ ( VIN ) + ( VREF ) R G⎠ ⎝ (EQ. 4) ISL28271 + VISL28271 ISL28272 VOUT A finite resistance RS in series with the VREF source, adds an output offset of VIN*(RS/RG). As the series resistance RS approaches zero, Equation 3 is simplified to Equation 4 for Figure 39. VOUT is simply shifted by an amount VREF. External Resistor Mismatches Because of the independent pair of feedback terminals provided by the in-amps, the CMRR is not degraded by any resistor mismatches. Hence, unlike a three op-amp and especially a two op-amp in-amp realization, the ISL28271 and ISL28272 reduce the cost of external components by allowing the use of 1% or more tolerance resistors without sacrificing CMRR performance. The CMRR will be typically 110dB regardless of the tolerance of the resistors used. Instead, a resistor mismatch results in a higher deviation from the theoretical gain - Gain Error. RF FIGURE 38. GAIN SETTING AND REFERENCE CONNECTION . VIN = IN+ – INRF ⎞ RF ⎞ ⎛ ⎛ VOUT = ⎜ 1 + ------- ⎟ ( VIN ) + ⎜ 1 + ------- ⎟ ( VREF ) R G⎠ R G⎠ ⎝ ⎝ (EQ. 2) Gain Error and Accuracy The FB+ pin is used as a REF terminal to center or to adjust the output. Because the FB+ pin is a high impedance input, an economical resistor divider can be used to set the voltage at the REF terminal without degrading or affecting the CMRR performance. Any voltage applied to the REF terminal will shift VOUT by VREF times the closed loop gain, which is set by resistors RF and RG. See Figure 38. The FB+ pin can also be connected to the other end of resistor, RG. See Figure 39. Keeping the basic concept that the in-amp maintains constant differential voltage across the input terminals and feedback terminals (FB- - FB+) = (IN+ - IN-), the transfer function of Figure 39 can be derived. 2.4V to 5V EN The gain error indicated in the electrical specifications table is the inherent gain error alone. The gain error specification listed does not include the gain error contributed by the resistors. There is an additional gain error due to the tolerance of the resistors used. The resulting non-ideal transfer function effectively becomes: RF ⎞ ⎛ VOUT = ⎜ 1 + ------- ⎟ × [ 1 ± ( E RG + E RF + E G ) ] × VIN R G⎠ ⎝ (EQ. 5) Where: ERG = Tolerance of RG ERF = Tolerance of RF EG = Gain Error of the ISL28271 IN+ IN+ IN- V+ + ISL28271 + - EN IN- The term [1 - (ERG +ERF +EG)] is the deviation from the theoretical gain. Thus, (ERG +ERF +EG) is the total gain error. For example, if 1% resistors are used, the total gain error would be: VOUT FB+ FB- TotalGainError = ± ( E RG + E RF + E G ( typical ) ) TotalGainError = ± ( 0.01 + 0.01 + 0.005 ) = ± 2.5% VCM VISL28271 ISL28272 RS RG RF Disable/Power-Down The ISL28271 and ISL28272 have an enable/disable pin for each channel. They can be powered down to reduce the supply current to typically 4µA when all channels are off. When disabled, the corresponding output is in a high impedance state. The active low EN pin has an internal pull down and hence can be left floating and the in-amp enabled by default. When the EN is connected to an external logic, VREF FIGURE 39. REFERENCE CONNECTION WITH AN AVAILABLE VREF 12 FN6390.0 December 8, 2006 ISL28271, ISL28272 the in-amp will shutdown when EN pin is pulled above 2V, and will power up when EN bar is pulled below 0.8V. Unused Channels The ISL28271and ISL28272 are Dual channel op-amps. If the application only requires one channel when using the ISL28271 or ISL28272, the user must configure the unused channel to prevent it from oscillating. The unused channel will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to configure the feedback pins (FB+, FB-) with the minimum gain stable values for the amplifier with RF and RG resistors and tieing the input terminals to ground (as shown in Figure 40). IN+ IN- + - FB+ FB- + RF RG FIGURE 40. PREVENTING OSCILLATIONS IN UNUSED CHANNELS 13 FN6390.0 December 8, 2006 ISL28271, ISL28272 Quarter Size Outline Plastic Packages Family (QSOP) A D N (N/2)+1 MDP0040 QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES A PIN #1 I.D. MARK 0.068 0.006 0.056 0.010 0.008 0.193 0.236 0.154 0.025 0.025 0.041 16 0.068 0.006 0.056 0.010 0.008 0.341 0.236 0.154 0.025 0.025 0.041 24 0.068 0.006 0.056 0.010 0.008 0.390 0.236 0.154 0.025 0.025 0.041 28 Max. ±0.002 ±0.004 ±0.002 ±0.001 ±0.004 ±0.008 ±0.004 Basic ±0.009 Basic Reference 1, 3 2, 3 Rev. E 3/01 A1 A2 b c E E1 1 B 0.010 CAB (N/2) D E E1 e C SEATING PLANE 0.004 C 0.007 CAB b H e L L1 N NOTES: L1 A c SEE DETAIL "X" 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 0.010 A2 GAUGE PLANE L 4°±4° DETAIL X A1 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN6390.0 December 8, 2006