ISL59830
True Single Supply Video Driver
DATASHEET
S
SIGN
W DE
E
N
R
D FO
9833
ENDE R TO ISL5 RADE
M
M
U PG
E FE
R EC O
NOT PLEASE R PATIBLE
C OM
A PIN
F OR
FN7489
Rev.1.00
May 4, 2006
The ISL59830 is a revolutionary device that allows true singlesupply operation of video amplifiers. The device runs off a
single 3.3V supply and generates the required negative
voltage internally. This allows for DC-accurate coupling of
video onto a 75 double-terminated line. Since the buffers
have an integrated 6dB gain, no external gain setting resistors
are required. An input reference voltage can be supplied to
shift the analog video level down by an amount equal to the
reference (typically 0.6V).
Features
Ordering Information
• 50MHz 0.1dB bandwidth
PART NUMBER
PART
TAPE &
MARKING REEL
PACKAGE
PKG.
DWG. #
• Triple single-supply buffer
• Operates from single +3.3V supply
• No output DC blocking capacitor needed
• Fixed gain of 2 output buffer
• Output three-statable
• Enable/disable function
• 200MHz -3dB bandwidth
• Pb-free plus anneal available (RoHS compliant)
ISL59830IA
59830IA
-
16 Ld QSOP M16.15A
ISL59830IA-T7
59830IA
7”
16 Ld QSOP M16.15A
Applications
ISL59830IA-T13
59830IA
13”
16 Ld QSOP M16.15A
• Driving video
ISL59830IAZ
(See Note)
59830IAZ
-
16 Ld QSOP M16.15A
(Pb-Free)
Pinout
ISL59830IAZ-T7
(See Note)
59830IAZ
7”
16 Ld QSOP M16.15A
(Pb-Free)
ISL59830IAZ-T13 59830IAZ
(See Note)
13”
16 Ld QSOP M16.15A
(Pb-Free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
ISL59830
(16 LD QSOP)
TOP VIEW
RIN 1
16 ROUT
GIN 2
15 GOUT
BIN 3
14 BOUT
REF 4
13 VCC
VEE 5
12 EN
GND 6
11 VCC
VEEOUT 7
DGND 8
FN7489 Rev.1.00
May 4, 2006
10 NC
9 DVCC
Page 1 of 15
ISL59830
Absolute Maximum Ratings (TA = 25°C)
VCC, Supply Voltage between VS and GND . . . . . . . . . . . . . . . . .5V
VIN, VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC+0.3V, VEE-0.3V
Voltage between VIN and VREF . . . . . . . . . . . . . . . . . . . . . . . . . .±2V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
AC Electrical Specifications
PARAMETER
BW -3dB
VCC = DVCC = +3.3V, REF = GND, TA = 25°C, RL = 150, unless otherwise specified.
DESCRIPTION
3dB Bandwidth
CONDITIONS
MIN
TYP
MAX
UNIT
VOUT = 200mVPP
200
MHz
VOUT = 2VPP
100
MHz
50
MHz
BW 0.1dB
0.1dB Bandwidth
VOUT = 2VPP
SR
Slew Rate
VOUT = 2VPP
dG
Differential Gain
0.07
%
dP
Differential Phase
0.06
°
XT
Hostile Crosstalk
6MHz
-90
dB
I
Input to Output Isolation
6MHz
-70
dB
VN
Input Noise Voltage
20
nV/Hz
Fcp
Charge Pump Switch Frequency
168
MHz
Load Reg
VRIPPLE
500
IEE = 0mA to 10mA
12
Output Amp Ripple Voltage
With Bead Core to DVCC
DC Electrical Specifications
PARAMETER
V/µs
60
mV
30
mV
10
mV
VCC = DVCC = +3.3V, REF = GND, TA = 25°C, RL = 150, unless otherwise specified.
DESCRIPTION
CONDITIONS
MIN
TYP
UNIT
3.6
V
1.5
%
V+
Supply Range
VG%
Gain Error
RL = 150, VIN = +2.5V to -1V
G
Gain Matching
RL = 150
RIN
Input Resistance
VIN = 0V to 1.5V
1.0
1.7
15
M
VOS
Output Offset Voltage
VREF = 0
-25
7
+25
mV
IOUT +
Output Current
RL = 10, VIN = 1.2V
50
IOUT -
Output Current
RL = 10, VIN = -0.3V
ZOUT
Output Impedance
Enabled
1
Three-stated
10
M
90
dB
PSRR
Power Supply Rejection Ratio
IS
Supply Current
RREF
Input Reference Resistor
FN7489 Rev.1.00
May 4, 2006
3.0
MAX
0.5
%
mA
-18
60
Amp Enabled
120
Amp Disabled
80
4
5
150
mA
mA
mA
6
k
Page 2 of 15
ISL59830
Pin Descriptions
PIN NUMBER
PIN NAME
1
RIN
PIN FUNCTION
EQUIVALENT CIRCUIT
Analog input
VCC
VEE
CIRCUIT 1
2
GIN
Analog input
Reference Circuit 1
3
BIN
Analog input
Reference Circuit 1
4
REF
Reference input
VCC
RIN
GIN
BIN
ROUT
GOUT
BOUT
+
-
3
REF
VEE
CIRCUIT 2
5
VEE
Chip substrate
VCC
VEE OUT
- +
DVCC
VEE
CHARGE
PUMP
DGND
CIRCUIT 3
6
GND
Analog ground
7
VEE OUT
Charge pump output
Reference Circuit 3
8
DGND
Charge pump ground
Reference Circuit 3
9
DVCC
Charge pump supply voltage
Reference Circuit 3
10
NC
11, 13
VCC
12
EN
Not connected
Positive power supply
Chip enable
VCC
VEE
CIRCUIT 4
FN7489 Rev.1.00
May 4, 2006
Page 3 of 15
ISL59830
Pin Descriptions (Continued)
PIN NUMBER
PIN NAME
14
BOUT
PIN FUNCTION
EQUIVALENT CIRCUIT
Analog output
VCC
VEE
CIRCUIT 5
15
GOUT
Analog output
Reference Circuit 5
16
ROUT
Analog output
Reference Circuit 5
Typical Performance Curves
5
AV=+2
CL=0pF
2
1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
3
1k
0
500
-1
150
-2
AV=+2
RL=500
9pF
4.7pF
3
2.2pF
1
0pF
-1
-3
75
-3
1M
10M
100M
-5
100K
1G
FREQUENCY (Hz)
-5
-10
-15
-20
-25
300
AV=+2
RL=500
240
-3dB ROLL-OFF
180
120
60
-0.1dB ROLL-OFF
-30
-35
1G
FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS CLOAD
GAIN ROLL-OFF (MHz)
NORMALIZED OUTPUT (dB)
AV=+2
CL=0pF
RL=500
0
100M
FREQUENCY (Hz)
FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS RLOAD
5
10M
1M
1
100
200
300
400
500
FREQUENCY (MHz)
FIGURE 3. VREF PIN OUTPUT FREQUENCY RESPONSE
FN7489 Rev.1.00
May 4, 2006
0
2.25
2.8
3.35
3.9
4.45
5
TOTAL SUPPLY VOLTAGE, VCC - VEE (V)
FIGURE 4. GAIN ROLL-OFF
Page 4 of 15
ISL59830
Typical Performance Curves (Continued)
-30
1.6
-50
CROSS TALK (dB)
1.2
PEAKING (dB)
AV=+2
-40 RL=500
AV=+2
RL=500
CL=3.9pF
0.8
0.4
-60
ENABLED
-70
-80
DISABLED
-90
-100
-110
0
2.2
2.6
2.4
2.8
3
3.2
3.4
3.6
3.8
-120
100K
4
-20
120
SUPPLY CURRENT (mA)
AV=+2
-30 RL=500
ISOLATION (dB)
-40
-50
-60
-70
-80
-90
10M
100M
100
80
60
40
20
0
1G
AV=+2
RL=500
1
1.5
FREQUENCY (Hz)
3
3.5
FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE
200
95
AV=+2
RL=500
120
80
40
SUPPLY CURRENT (mA)
-3dB
BANDWIDTH (MHz)
2.5
2
SUPPLY VOLTAGE (V)
FIGURE 7. INPUT TO OUTPUT ISOLATION vs FREQUENCY
160
1G
FIGURE 6. CROSS TALK CHANNEL TO CHANNEL (TYPICAL)
FIGURE 5. PEAKING vs SUPPLY VOLTAGE
1M
100M
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
-100
100K
10M
1M
90
AV=+2
RL=500
VCL=3.3V
85
80
-0.1dB
0
25
55
85
115
TEMPERATURE (°C)
FIGURE 9. BANDWIDTH vs TEMPERATURE
FN7489 Rev.1.00
May 4, 2006
145
75
25
55
85
115
145
TEMPERATURE (°C)
FIGURE 10. SUPPLY CURRENT vs TEMPERATURE
Page 5 of 15
ISL59830
Typical Performance Curves (Continued)
100
-10
-30
PSRR (dB)
IMPEDANCE ()
10
1
-50
PSRR-70
PSRR+
0.1
-90
0.01
10K
100K
1M
-110
1K
100M
10M
10K
FREQUENCY (Hz)
10M
100M
FIGURE 12. POWER SUPPLY REJECTION RATIO vs
FREQUENCY
-30
HARMONIC DISTORTION (dBc)
1K
VOLTAGE NOISE (nV/Hz),
CURRENT NOISE (pA/Hz)
1M
FREQUENCY (Hz)
FIGURE 11. OUTPUT IMPEDANCE vs FREQUENCY
100
eN
10
IN+
1
IN0.1
10
100K
100
1K
10K
100K
1M
-40
-60
-70
2ND HD
3RD HD
-80
-90
-100
10M
THD
-50
0
10
20
30
40
FUNDAMENTAL FREQUENCY (MHz)
FREQUENCY (Hz)
FIGURE 13. VOLTAGE AND CURRENT NOISE vs FREQUENCY
FIGURE 14. HARMONIC DISTORTION vs FREQUENCY
-30
-40
THD
FIN=10MHz
-60
DIFFERENTIAL
GAIN (%)
THD (dBc)
-50
-70
THD
FIN=1MHz
-80
-90
0.5
1
1.5
2
2.5
OUTPUT VOLTAGE (VP-P)
FIGURE 15.
FN7489 Rev.1.00
May 4, 2006
3
3.5
0
-0.02
-0.04
-0.06
-0.08
IRE
FIGURE 16. DIFFERENTIAL GAIN
Page 6 of 15
ISL59830
VOLTS (500mV/DIV)
DIFFERENTIAL
PHASE (°)
Typical Performance Curves (Continued)
0
-0.02
-0.04
-0.06
-0.08
TIME (2µs/DIV)
IRE
FIGURE 18. DISABLE TIME
VOLTS (50mV/DIV)
VOLTS (500mV/DIV)
FIGURE 17. DIFFERENTIAL PHASE
TIME (200ns/DIV)
TIME (10ns/DIV)
FIGURE 21. LARGE SIGNAL RISE & FALL TIMES
FN7489 Rev.1.00
May 4, 2006
FIGURE 20. SMALL SIGNAL RISE & FALL TIMES
VOLTS (10mV/DIV)
VOLTS (500mV/DIV)
FIGURE 19. ENABLE TIME
TIME (10ns/DIV)
TIME (20ns/DIV)
FIGURE 22. AMP OUTPUT NOISE (CHARGE PUMP
OSCILLATION)
Page 7 of 15
ISL59830
Typical Performance Curves (Continued)
1.6
BACKDRIVE CURRENT (mA)
OUTPUT RANGE (V)
3.25
3
2.75
2.5
50
AV=+2
CL=3.9pF
450
250
650
850
BACKDRIVE ACROSS 5 RESISTOR
TYPICAL CHANNEL
1.2
VCC = 3.3V
0.8
0.4
0
1050
0
FIGURE 23. MAXIMUM OUTPUT MAGNITUDE vs LOAD
RESISTANCE
POWER DISSIPATION (W)
3
4
5
BACKDRIVE VOLTAGE (V)
LOAD RESISTANCE ()
1.4
2
1
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
FIGURE 24. BACKDRIVE VOLTAGE vs CURRENT
AMP DISABLED OUTPUT LOADING
Block Diagram
VCC
1.2
1
791mW
0.8
QS
Y
OP
J
16
A =1
58
°C
/W
0.6
0.4
RIN
+
ROUT
6dB
REFERENCE
0.2
Pb
GIN
GOUT
+
6dB
0
0
25
50
75 85 100
125
-
150
AMBIENT TEMPERATURE (°C)
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
1.8
Pr
BIN
BOUT
6dB
-
DVCC
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
CHARGE
PUMP
1.6
POWER DISSIPATION (W)
+
VEE-OUT
VEE
1.4
VOUT = 2VIN - VREFERENCE
1.116W
1.2
1
J
QS
A =1
0.8
OP
12
0.6
16
°C
/W
0.4
0.2
0
0
25
50
75 85
100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7489 Rev.1.00
May 4, 2006
Page 8 of 15
ISL59830
FN7489 Rev.1.00
May 4, 2006
ISL59830 + DC-Restore Solution
1 IN1
IN2 16
2 COM1
COM2 15
3 NC1
NC2 14
4 V-
R7
2k
V+ 13
5 GND
NC 12
(No Connect)
6 NC4
NC3 11
7 COM4
YO
Pb
Pr
R1
75
8 IN4
VCC
IN3 9
R9
2k
ISL43140
R2
75
R3
75
COM3 10
R11
499
C4
0.1µF
C5
0.1µF
C6
0.1µF
REF
MMBP
3904
C7
1.0µF
VEE (-1.6V)
1k
R12
R8
REFERENCE
CONTROL
D1
1N4148
C11
0.1µF
(or similar)
CN = Option for lower
charge pump noise
R10
2k
1 RIN
ROUT 16
2 GIN
GOUT 15
3 BIN
BOUT 14
4 REF
VCC 13
5 VEE
EN 12
6 GND
VCC 11
7 VEEOUT
8 DGND
75
R5
75
R6
75
C12
20pF
C13
20pF
VCC
C1
0.1µF
ENABLE
2
1
NC 10
DVCC 9
R4
C15
0.1µF
3
C14
20pF
VCC
VCC
GND
+ C16
YO
Pb
Pr
VCC
1µF
ISL59830
C4
0.1µF
Page 9 of 15
C10
0.1µF
1 COMP
VDD 8
2 COMP
OUT 7
SYNC OUT
VIDEO IN
3 VSYNC
OUT
4 GND
RESET 6
BACK
PORCH 5
OUT
EL1881
C8
0.1µF
R13
C9
0.1µF 681k
Option: Panasonic 120Bead
EXC3BP121H
Lower Amp output noise from charge pump
ISL59830
Demo Board Schematic
RED_IN
R1
75
RED_OUT
GREEN_IN
R2
75
BLUE_IN
R3
75
VCC
R7
1k
C4
1.0µF
R4
499
VCC
R8
1k
ROUT 16
2 GIN
GOUT 15
3 BIN
BOUT 14
4 REF
VCC 13
5 VEE
EN 12
6 GND
VCC 11
7 VEEOUT
C2
0.1µF
REFERENCE
CONTROL
1 RIN
8 DGND
D1
1N4148
(or similar)
75
R5
75
R6
75
GREEN_OUT
VCC
BLUE_OUT
C3
0.1µF
ENABLE
2
1
NC 10
DVCC 9
R4
C5
0.1µF
VCC
3
Option: Panasonic 120Bead
EXC3BP121H
Lower Amp output noise from charge pump
Block Diagram
VCC
Y
RIN
+
ROUT
6dB
REFERENCE
Pb
GIN
+
GOUT
6dB
-
Pr
BIN
BOUT
+
6dB
-
DVCC
CHARGE
PUMP
VEE-OUT
VEE
VOUT = 2VIN - VREFERENCE
FN7489 Rev.1.00
May 4, 2006
Page 10 of 15
ISL59830
IN+
IN-
OUT
BIAS
FIGURE 27.
Description of Operation and Application
Information
Theory Of Operation
The ISL59830 is a highly practical and robust marriage of three
high bandwidth, high speed, low power, rail-to-rail voltage
feedback amplifiers with a charge pump, to provide a negative
rail without an additional power supply. Designed to operate
with a single supply voltage range of from 0V to 3.3V, the
ISL59830 eliminates the need for a split supply with the
incorporation of a charge pump capable of generating a bottom
rail as much as 1.6V below ground; for a 4.9V range on a
single 3.3V supply. This performance is ideal for NTSC video
with its negative-going sync pulses.
The Amplifier
The ISL59830 fabricated on a dielectrically isolated high speed
5V Bi-CMOS process with 4GHz PNPs and NPN transistor
exceeding 20GHz - perfect for low distortion, low power
demand and high frequency circuits. While the ISL59830
utilizes somewhat standard voltage mode feedback topologies,
there are many non-standard analog features providing its
outstanding bandwidth, rail-to-rail operation, and output drive
capabilities. The input signal initially passes through a folded
cascode, a topology providing enhanced frequency response
essentially by fixing the base collector voltage at the junction of
the input and gain stage. The collector of each input device
looks directly into an emitter that is tied closely to ground
through a resistor and biased with a very stable DC source.
Since the voltage of this collector is "locked stable" the
effective bandwidth limiting of the Miller capacitance is greatly
reduced. The signal is then passed through a second fullyrealized differential gain stage and finally through a proprietary
common emitter output stage for improved rail-to-rail output
performance. The result is a highly-stable, low distortion, low
FN7489 Rev.1.00
May 4, 2006
power, and high frequency amplifier capable of driving
moderately capacitive loads with near rail-to-rail performance.
Input Output Range
The three amplifier channels have an input common mode
voltage range from 0.15V below the bottom rail to within
100mV of the positive supply, VS+ pin (Note: bottom rail is
established by the charge pump at negative one half the
positive supply). As the input signal moves outside the
specified range, the output signal will exhibit increasingly
higher levels of harmonic distortion. And of course, as load
resistance becomes lower, the current drive capability of the
device will be challenged and its ability to drive close to each
rail is reduced. For instance, with a load resistance of 1k the
output swing is within a 100mV of the rails, while a load
resistance of 150 limits the output swing to within around
300mV of the rails.
Amplifier Output Impedance
To achieve near rail-to-rail performance, the output stage of the
ISL59830 uses transistors in the common emitter
configuration, typically producing higher output impedance
than the standard emitter follower output stage. The
exceptionally high open loop gain of the ISL59830 and local
feedback reduces output impedance to less than a 2 at low
frequency. However, since output impedance of the device is
exponentially modulated by the magnitude of the open loop
gain, output impedance increases with frequency as the open
loop gain decreases with frequency. This inductive-like effect of
the output impedance is countered in the ISL59830 with
proprietary output stage topology, keeping the output
impedance low over a wide frequency range and making it
possible to easily and effectively drive relatively heavy
capacitive loads.(See Figure 11).
Page 11 of 15
ISL59830
The Charge Pump
The VREF Pin
The ISL59830 charge pump provides a bottom rail up to 1.65V
below ground while operating on a 0V to 3.3V power supply.
The charge pump is internally regulated to one-half the
potential of the positive supply. This internal multi-phase
charge pump is driven by a 160MHz differential ring oscillator
driving a series of inverters and charge storage circuitry. Each
series inverter charges and places parallel adjoining charge
circuitry slightly out of phase with the immediately preceding
block. The overall effect is sequential discharge and
generation of a very low ripple of about 10mV that is applied to
the amplifiers providing a negative rail of up to -1.65V.
Applying a voltage to the VREF pin simply places that voltage
on what would usually be the ground side of the gain resistor of
the amplifier, resulting in a DC-level shift of the output signal.
Applying 100mV to the Vref pin would apply a -100mV DC level
shift to the outgoing signal. The charge pump provides
sufficient bottom room to accommodate the shifted signal.
VREF may be connected to ground for back porch at ground.
There are two options to reduce the output supply noise.
• Add a 120bead in series between VCC and DVCC to
further reduce ripple.
Add a 20pF capacitor between the back load 75 resistor and
ground (see the ISL59830A + DC-Restore Solution schematic
on page 10).
Note: The VREF input is the common point of the 3 amps
minus input resistors. Any common resistance on VREF input
will share the voltage induced on it with all the other amps, so
using a resistor source to get offset will cause cross talk and
gain change for the offset for all amps and amp +input gain
change. Offset on the VREF pin must be low impedance to
prevent gain error and cross talk. A transistor emitter follower
should work like an NPN MMBT3904 with the emitter
connected to the VREF pin and 1k pull down to V- with 1µF cap
bypass to ground and the collector to V+ and base to V offset
source. If better tempco is needed then a diode may be used in
series with the pot to ground. A 499 resistor may be added in
series with the collector to prevent damage when testing.
See the Block Diagram on page 8.
VOLTS (10mV/DIV)
The VEE Pin
The VEE pin is the output pin for the charge pump. A voltmeter
applied to this pin will display the output of the charge pump.
This pin does not affect the functionality of the part. One may
use this pin as an additional voltage source. Keep in mind that
the output of this pin is generated by the internal charge pump
and a fully regulated supply that must be properly bypassed.
We recommend a 0.1µF ceramic capacitor placed as close to
the pin and connected to the ground plane of the board.
TIME (20ns/DIV)
FIGURE 28. CHARGE PUMP OSCILLATION (AMP OUTPUT)
The system operates at sufficiently high frequencies that any
related charge pump noise is far beyond standard video
bandwidth requirements. Still, appropriate bypassing discipline
must be observed, and all pins related to either the power
supply or the charge pump must be properly bypassed. See
"Power Supply Bypassing and Printed Circuit Board Layout" in
this section.
To maximize resistance to latch-up, a diode should be added
between the VEEOUT pin (anode) and GND (cathode), as
shown in the Demo Board Schematic. This prevents VEE from
rising more than 0.7V above ground during startup. (VEE > 1V
above GND can cause latchup under some conditions.)
FN7489 Rev.1.00
May 4, 2006
Input, Output, and Supply Voltage Range
The ISL59830 is designed to operate with a single supply
voltage range of from 0V to 3.3V. The need for a split supply
has been eliminated with the incorporation of a charge pump
capable of generating a bottom rail as much as 1.6V below
ground, for a 4.9V range on a single 3.3V supply. This
performance is ideal for NTSC video with its negative-going
sync pulses.
Video Performance
For good video performance, an amplifier is required to
maintain the same output impedance and the same frequency
and phase response as DC levels are changed at the output.
This is especially difficult when driving a standard video load of
150 because of the change in output current with changing
DC levels. Special circuitry has been incorporated into the
ISL59830 for the reduction of output impedance variation with
the current output. This results in outstanding differential gain
and differential phase specifications of 0.06% and 0.1°, while
driving 150 at a gain of +2. Driving higher impedance loads
would result in similar or better differential gain and differential
phase performance.
Page 12 of 15
ISL59830
NTSC
Output Drive Capability
The ISL59830, generating a negative rail internally, is ideally
suited for NTSC video with its accompanying negative-going
sync signals; easily handled by the ISL59830 without the need
of an additional supply as the ISL59830 generates a negative
rail with an internal charge pump referenced at negative 1/2
the positive supply.
The ISL59830 does not have internal short-circuit protection
circuitry. A short-circuit current of 80mA sourcing and 150mA
sinking for the output is connected to half way between the
rails with a 10 resistor. If the output is shorted indefinitely, the
power dissipation could easily increase such that the part will
be destroyed. Maximum reliability is maintained if the output
current never exceeds ±40mA, after which the electromigration limit of the process will be exceeded and the part will
be damaged. This limit is set by the design of the internal metal
interconnections.
YPbPr
YPbPr signals originating from a DVD player requiring three
channels of very tightly-controlled amplifier gain accuracy
present no difficulty for the ISL59830. Specifically, this
standard encodes sync on the Y channel and it is a negativegoing signal; easily handled by the ISL59830 without the need
of an additional supply as the ISL59830 generates a negative
rail placed at negative 1/2 the positive supply. Additionally, the
Pb and Pr are bipolar analog signals and the video signals are
negative-going; and again easily handled by the ISL59830.
Driving Capacitive Loads and Cables
The ISL59830, internally-compensated to drive 75 cables,
will drive 10pF loads in parallel with 1k with less than 5dB of
peaking. If less peaking is required, a small series resistor,
usually between 5 to 50, can be placed in series with the
output. This will reduce peaking at the expense of a slight
closed loop gain reduction. When used as a cable driver,
double termination is always recommended for reflection-free
performance. For those applications, a back-termination series
resistor at the amplifier's output will isolate the amplifier from
the cable and allow extensive capacitive drive. However, other
applications may have high capacitive loads without a backtermination resistor. Again, a small series resistor at the output
can help to reduce peaking. The ISL59830 is a triple amplifier
designed to drive three channels; simply deal with each
channel separately as described in this section.
Power Dissipation
With the high output drive capability of the ISL59830, it is
possible to exceed the 150°C absolute maximum junction
temperature under certain load current conditions. Therefore, it
is important to calculate the maximum junction temperature for
an application to determine if load conditions or package types
need to be modified to assure operation of the amplifier in a
safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX – T AMAX
PD MAX = -------------------------------------------- JA
Where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
JA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC is
the total quiescent supply current times the total power supply
voltage, plus the power in the IC due to the load, or:
DC-Restore
for sourcing:
When the ISL59830 is AC-coupled it becomes necessary to
restore the DC reference for the signal. This is accomplished
with a DC-restore system applied between the capacitive "AC"
coupling and the input of the device. Refer to Application
Circuit for reference DC-restore solution.
V OUT i
PD MAX = V S I SMAX + V S – V OUT i ----------------R i
Amplifier Disable
The ISL59830 can be disabled and its output placed in a high
impedance state. The turn-off time is around 25ns and the turnon time is around 200ns. When disabled, the amplifier's supply
current is reduced to 80mA typically, reducing power
consumption. The amplifier's power-down can be controlled by
standard TTL or CMOS signal levels at the EN pin. The applied
logic signal is relative to GND pin. Letting the EN pin float or
applying a signal that is less than 0.8V above GND will enable
the amplifier. The amplifier will be disabled when the signal at
EN pin is 2V above GND. The VEE charge pump remains
active.
FN7489 Rev.1.00
May 4, 2006
L
for sinking:
PD MAX = V S I SMAX + V OUT i – V S I LOAD i
Where:
VS = Supply voltage
ISMAX = Maximum quiescent supply current
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
i = Number of output channels
Page 13 of 15
ISL59830
By setting the two PDMAX equations equal to each other, we
can solve the output current and RLOAD to avoid the device
overheat.
Power Supply Bypassing and Printed Circuit Board
Layout
Strip line design techniques are recommended for the input
and output signal traces. As with any high frequency device, a
good printed circuit board layout is necessary for optimum
performance. Lead lengths should be as short as possible. The
power supply pin must be well bypassed to reduce the risk of
oscillation. For normal single supply operation, where the VSpin is connected to the ground plane, a single 4.7µF tantalum
FN7489 Rev.1.00
May 4, 2006
capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to
GND will suffice. This same capacitor combination should be
placed at each supply pin to ground if split-internal supplies are
to be used. In this case, the VS- pin becomes the negative
supply rail.
For good AC performance, parasitic capacitance should be
kept to a minimum. Use of wire-wound resistors should be
avoided because of their additional series inductance. Use of
sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is also very important.
Page 14 of 15
ISL59830
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M16.15A
N
INDEX
AREA
H
0.25(0.010) M
E
2
INCHES
GAUGE
PLANE
-B1
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
B M
SYMBOL
3
0.25
0.010
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A2
A1
B
0.17(0.007) M
L
C
0.10(0.004)
C A M
B S
NOTES:
MIN
MIN
MAX
NOTES
A
0.061
0.068
1.55
1.73
-
A1
0.004
0.0098
0.102
0.249
-
A2
0.055
0.061
1.40
1.55
-
B
0.008
0.012
0.20
0.31
9
C
0.0075
0.0098
0.191
0.249
-
D
0.189
0.196
4.80
4.98
3
E
0.150
0.157
3.81
3.99
4
e
0.025 BSC
0.635 BSC
-
H
0.230
0.244
5.84
6.20
-
h
0.010
0.016
0.25
0.41
5
L
0.016
0.035
0.41
0.89
6
N
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
MILLIMETERS
MAX
16
0°
16
8°
0°
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
7
8°
Rev. 2 6/04
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.10mm (0.004 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
© Copyright Intersil Americas LLC 2005-2006. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7489 Rev.1.00
May 4, 2006
Page 15 of 15
工商网监
湘ICP备2023018690号
