X5083PZ-4.5A

® X5083 Data Sheet June 15, 2006 FN8127.3 CPU Supervisor with 8Kbit SPI EEPROM This device combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low VCC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET is asserted until VCC returns to the proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to finetune the threshold for applications requiring higher precision. Features • Low VCC detection and reset assertion - Four standard reset threshold voltages 4.63V, 4.38V, 2.93V, 2.63V - Re-program low VCC reset threshold voltage using special programming sequence - Reset signal valid to VCC = 1V • Selectable time out watchdog timer • Long battery life with low power consumption - none of the array 000WD1 WD2001 --->block lock Q1: 0000h-00FFh--->lower quadrant (Q1) 000WD1 WD2010 --->block lock Q2: 0100h-01FFh--->Q2 000WD1 WD2011 --->block lock Q3: 0200h-02FFh--->Q3 000WD1 WD2100 --->block lock Q4: 0300h-03FFh--->upper quadrant (Q4) 000WD1 WD2101 --->block lock H1: 0000h-01FFh--->lower half of the array (H1) 000WD1 WD2110 --->block lock P0: 0000h-000Fh--->lower page (P0) 000WD1 WD2111 --->block lock Pn: 03F0h-03FFh--->upper page (PN) READ STATUS: reads status register & provides write in progress status on SO pin WRITE: write operation followed by address and data READ: read operation followed by address 0000 0101 0000 0010 0000 0011 8 FN8127.3 June 15, 2006 X5083 Watchdog Timer The watchdog timer bits, WD0 and WD1, select the watchdog time out period. These nonvolatile bits are programmed with the WRSR instruction. A change to the Watchdog Timer, either setting a new time out period or turning it off or on, takes effect, following either the next command (read or write) or cycling the power to the device. The recommended procedure for changing the Watch-dog Timer settings is to do a WREN, followed by a write status register command. Then execute a soft-ware loop to read the status register until the MSB of the status byte is zero. A valid alternative is to do a WREN, followed by a write status register command. Then wait 10ms and do a read status command. TABLE 2. WATCHDOG TIMER DEFINITION STATUS REGISTER BITS WD1 0 0 1 1 WD0 0 1 0 1 WATCHDOG TIME OUT (TYPICAL) 1.4s 600ms 200ms disabled (factory default) To write data to the EEPROM memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be “0’s”. The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the same page and overwrite any data that may have been previously written. For a write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 8). To write to the status register, the WRSR instruction is followed by the data to be written (Figure 9). Data bits 5, 6 and 7 must be “0”. Read Status Operation If there is not a nonvolatile write in progress, the read status instruction returns the block lock setting from the status register which contains the watchdog timer bits WD1, WD0, and the block lock bits IDL2-IDL0 (Figure 6). The block lock bits define the block lock condition (Table 1). The watchdog timer bits set the operation of the watchdog timer (Table 2). The other bits are reserved and will return ’0’ when read. See Figure 6. During an internal nonvolatile write operaiton, the Read Status Instruction returns a HIGH on SO in the first bit following the RDSR instruction (the MSB). The remaining bits in the output status byte are undefined. Repeated Read Status Instructions return the MSB as a ‘1’ until the nonvolatile write cycle is complete. When the nonvolatile write cycle is completed, the RDSR instruction returns a ‘0’ in the MSB position with the remaining bits of the status register undefined. Subsequent RDSR instructions return the Status Register Contents. See Figure 10. Read Sequence When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the read EEPROM array sequence (Figure 5). To read the status register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Refer to the read status register sequence (Figure 6). RESET Operation The RESET output is designed to go LOW whenever VCC has dropped below the minimum trip point and/or the watchdog timer has reached its programmable time out limit. The RESET output is an open drain output and requires a pull up resistor. Operational Notes The device powers-up in the following state: • The device is in the low power standby state. • A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. • SO pin is high impedance. • The write enable latch is reset. • Reset signal is active for tPURST. Write Sequence Prior to any attempt to write data into the device, the “Write Enable” Latch (WEL) must first be set by issuing the WREN instruction (Figure 7). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. 9 FN8127.3 June 15, 2006 X5083 Data Protection The following circuitry has been included to prevent inadvertent writes: • A WREN instruction must be issued to set the write enable latch. • CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle. • When VCC is below VTRIP, communications to the device are inhibited. CS 0 SCK 1 2 3 4 5 6 7 8 9 20 21 22 23 24 25 26 27 28 29 30 Read Instruction (1 Byte) SI Byte Address (2 Byte) 15 14 3 2 1 0 Data Out SO High Impedance 7 6 5 4 3 2 1 0 FIGURE 5. READ OPERATION SEQUENCE CS 0 SCK 1 2 3 4 5 6 7 ... ... W D 1 W D 0 B L 2 B L 1 B L 0 Read Status Instruction SI SO ... SO = Status Reg When no Nonvolatile Write Cycle FIGURE 6. READ STATUS OPERATION SEQUENCE 10 FN8127.3 June 15, 2006 X5083 CS 0 SCK 1 2 3 4 5 6 7 Instruction (1 Byte) SI High Impedance SO FIGURE 7. WREN/WRDI SEQUENCE CS 0 SCK Instruction SI 16 Bit Address 15 14 13 3 2 1 0 7 6 Data Byte 1 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4 3 2 1 0 7 6 Data Byte 3 5 4 3 2 1 0 6 5 Data Byte N 4 3 2 1 0 FIGURE 8. EEPROM ARRAY WRITE SEQUENCE CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Instruction SI 6 5 4 Data Byte 3 2 B L 2 1 B L 1 0 B L 0 WW DD 10 SO High Impedance FIGURE 9. STATUS REGISTER WRITE SEQUENCE 11 FN8127.3 June 15, 2006 X5083 CS 01234567 01234567 SCK READ STATUS INSTRUCTION READ STATUS INSTRUCTION SI NONVOLATILE WRITE IN PROGRESS SO SO MSB HIGH while in the Nonvolatile write cycle SO MSB still HIGH indicates Nonvolatile write cycle still in progress CS 01234567 01234567 SCK READ STATUS INSTRUCTION READ STATUS INSTRUCTION SI NONVOLATILE WRITE ENDS 43210 WD1 WD0 BL2 BL1 BL0 SO 1st detected SO MSB LOW indicates end of Nonvolatile write cycle FIGURE 10. READ NONVOLATILE WRITE STATUS 12 FN8127.3 June 15, 2006 X5083 tWC CS 0 SCK 1 2 3 4 5 6 7 NEXT INSTRUCTION SI Non-volatile Write Operation Wait tWC after a write for new operation, if not using polling procedure FIGURE 11. END OF NONVOLATILE WRITE (NO POLLING) Symbol Table WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance 13 FN8127.3 June 15, 2006 X5083 Absolute Maximum Ratings Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . .-65°C to 135°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to 150°C Voltage on Any Pin with Respect To Vss . . . . . . . . . . . . . -1.0V to 7V D.C. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C Operating Conditions Temperature Range Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C VCC Range -2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Blank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. DC Electrical Specifications (Over the recommended operating conditions unless otherwise specified.) LIMITS SYMBOL ICC1 ICC2 ISB1 ISB2 ISB3 ILI ILO PARAMETER VCC Write Current (Active) VCC Read Current (Active) TEST CONDITIONS SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open SCK = VCC x 0.1/VCC x 0.9 @ 5MHz, SO = Open MIN TYP MAX 5 0.4 1 50 20 UNIT mA mA µA µA µA µA µA V V V V V V V V VCC Standby Current WDT = OFF CS = VCC, VIN = VSS or VCC, VCC = 5.5V VCC Standby Current WDT = ON VCC Standby Current WDT = ON Input Leakage Current Output Leakage Current CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC = 3.6V VIN = VSS to VCC VOUT = VSS to VCC -0.5 VCC x 0.7 VCC > 3.3V, IOL = 2.1mA 2V < VCC ≤ 3.3V, IOL = 1mA VCC ≤ 2V, IOL = 0.5mA VCC > 3.3V, IOH = -1.0mA 2V < VCC ≤ 3.3V, IOH = -0.4mA VCC ≤ 2V, IOH = -0.25mA IOL = 1mA VCC - 0.8 VCC - 0.4 VCC - 0.2 0.1 0.1 10 10 VCC x 0.3 VCC + 0.5 0.4 0.4 0.4 VIL (Note 1) Input LOW Voltage VIH (Note 1) Input HIGH Voltage VOL1 VOL2 VOL3 VOH1 VOH2 VOH3 VOLRS Output LOW Voltage Output LOW Voltage Output LOW Voltage Output HIGH Voltage Output HIGH Voltage Output HIGH Voltage Reset Output LOW Voltage 0.4 V Power-Up Timing SYMBOL tPUR (Note 2) tPUW (Note 2) . PARAMETER Power-up to read operation Power-up to write operation MIN MAX 1 5 UNIT ms ms Capacitance TA = +25°C, f = 1MHz, VCC = 5V SYMBOL TEST MAX 8 6 UNIT pF pF CONDITIONS VOUT = 0V VIN = 0V COUT (Note 2) Output capacitance (SO, RESET, RESET) CIN (Note 2) NOTES: 1. VIL min. and VIH max. are for reference only and are not tested. 2. This parameter is periodically sampled and not 100% tested. Input capacitance (SCK, SI, CS, WP) 14 FN8127.3 June 15, 2006 X5083 Equivalent A.C. Load Circuit at 5V VCC 5V 5V A.C. Test Conditions Input pulse levels Input rise and fall times VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 1.64kΩ SO OUTPUT RESET 100pF 3.3kΩ Input and output timing level 1.64kΩ 30pF AC Electrical Specifications SYMBOL DATA INPUT TIMING fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI (Note 3) tFI (Note 3) tCS tWC (Note 4) Clock frequency Cycle time CS lead time CS lag time Clock HIGH time Clock LOW time Data setup time Data hold time Input rise time Input fall time CS deselect time Write cycle time (Over recommended operating conditions, unless otherwise specified) 2.7V-5.5V PARAMETER MIN MAX UNIT 0 300 150 150 130 130 20 20 3.3 MHz ns ns ns ns ns ns ns 2 2 100 10 µs µs ns ms DATA OUTPUT TIMING fSCK tDIS tV tHO tRO (Note 3) tFO (Note 3) NOTES: 3. This parameter is periodically sampled and not 100% tested. 4. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. Clock frequency Output disable time Output valid from clock low Output hold time Output rise time Output fall time 0 50 50 0 3.3 150 130 MHz ns ns ns ns ns 15 FN8127.3 June 15, 2006 X5083 Serial Output Timing CS tCYC SCK tV SO MSB Out MSB–1 Out tHO tWL LSB Out tDIS tWH tLAG SI ADDR LSB IN Serial Input Timing tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG SO High Impedance Power-Up and Power-Down Timing VCC VTRIP 0 Volts tR RESET tPURST tPURST VTRIP tF tRPD 16 FN8127.3 June 15, 2006 X5083 RESET Output Timing SYMBOL VTRIP PARAMETER Reset trip point voltage, X5083PT-4.5A (Note 6) Reset trip point voltage, X5083PT Reset trip point voltage, X5083PT-2.7A Reset trip point voltage, X5083PT-2.7 Power-up reset time out VCC detect to reset/output VCC fall time VCC rise time Reset valid VCC 0.1 0.1 1 MIN 4.5 4.25 2.85 2.55 100 TYP 4.63 4.38 2.93 2.63 200 MAX 4.75 4.5 3.00 2.7 280 500 UNIT V tPURST tRPD (Note 5) tF (Note 5) tR (Note 5) VRVALID NOTES: ms ns ns ns V 5. This parameter is periodically sampled and not 100% tested. 6. PT = Package/Temperature CS vs. RESET Timing CS tCST RESET tWDO tRST tWDO tRST RESET Output Timing SYMBOL tWDO PARAMETER Watchdog time out period, WD1 = 1, WD0 = 1(default) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS pulse width to reset the watchdog Reset time out MIN TYP OFF 200 600 1.4 MAX UNIT 100 450 1 400 100 300 800 2 ms ms sec ns tCST tRST 200 300 ms 17 FN8127.3 June 15, 2006 X5083 VTRIP Programming Timing Diagram VCC (VTRIP) VTRIP tTSU VP VPE tVPS CS tPCS tVPH tVPO tTHD tRP SCK SI 06h WREN 02h Write 0001h (set) 0003h (reset) Addr. 00 Data VTRIP Programming Parameters PARAMETER tVPS tVPH tPCS tTSU tTHD tWC tVPO tRP VP VTRAN Vtv NOTES: 7. VTRIP programming parameters are periodically sampled and are not 100% tested. 8. For custom VTRIP settings, Contact Factory. VTRIP program enable voltage setup time VTRIP program enable voltage hold time VTRIP programming CS inactive time VTRIP setup time VTRIP hold (stable) time VTRIP write cycle time VTRIP program enable voltage off time (between successive adjustments) VTRIP program recovery period (between successive adjustments) Programming voltage VTRIP programmed voltage range VTRIP program variation after programming (0-75°C). (programmed at 25°C) 0 10 15 2.0 -25 18 5.0 +25 DESCRIPTION MIN 1 1 1 1 10 10 MAX UNIT µs µs µs µs ms ms µs ms V V mV 18 FN8127.3 June 15, 2006 X5083 Small Outline Package Family (SO) A D N (N/2)+1 h X 45° A E E1 PIN #1 I.D. MARK c SEE DETAIL “X” 1 B (N/2) L1 0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X SEATING PLANE L 4° ±4° 0.010 MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150”) 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300”) (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX ±0.003 ±0.002 ±0.003 ±0.001 ±0.004 ±0.008 ±0.004 Basic ±0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01 19 FN8127.3 June 15, 2006 X5083 Plastic Dual-In-Line Packages (PDIP) D E N PIN #1 INDEX SEATING PLANE L e b A2 A c E1 A1 NOTE 5 eA eB 1 2 b2 N/2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN ±0.005 ±0.002 +0.010/-0.015 +0.004/-0.002 ±0.010 +0.015/-0.010 ±0.005 Basic Basic ±0.025 ±0.010 Reference Rev. B 2/99 NOTES: 1. Plastic or metal protrusions of 0.010” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. 2 1 NOTES 20 FN8127.3 June 15, 2006 X5083 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M8.173 8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.031 0.0075 0.0035 0.116 0.169 0.246 0.0177 8 0o 8o 0o MAX 0.047 0.006 0.051 0.0118 0.0079 0.120 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 2.95 4.30 6.25 0.45 8 8o MAX 1.20 0.15 1.05 0.30 0.20 3.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 1 12/00 e b 0.10(0.004) M C AM BS α A1 0.10(0.004) A2 c E1 e E L N 0.026 BSC 0.65 BSC NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) α All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN8127.3 June 15, 2006