NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT PART
ISL22102
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
DATASHEET
X9460
FN8203
Rev 2.00
October 17, 2005
Low Noise, Low Cost, High End Features, Dual Audio Log Potentiometer Dual
Audio Control Digitally Controlled Potentiometer (XDCP™)
The X9460 integrates two digitally controlled potentiometer
(XDCP) on a monolithic CMOS integrated circuit. The two
XDCPs can be used as stereo gain controls in audio
applications. Read/Write operations can directly access
each channel independently or both channels
simultaneously. Increment/Decrement can adjust each
channel independently or both channels simultaneously.
Features
• Dual Audio Control – Two 32 Taps Log Pots
• Zero Amplitude Wiper Switching
• 2-Wire Serial Interface
4 Slave Byte Addresses for Writes[A1,A0]
• Total Resistance: 33k Each XDCP (Typical)
The X9460 contains a zero amplitude wiper switching circuit
that delays wiper changes until the next zero crossing of the
audio signal.
• Dual Voltage Operation
V+/V- = ±2.7 to ±5.5V
• Temp Range = -40°C to +85°C
The digitally controlled potentiometer is implemented using
31 polysilicon resistors in a log array. Between each of the
resistors are tap points connected to the wiper terminal
through switches. The XDCPs are designed to minimize
wiper noise to avoid pops and clicks during audio volume
transitions. The position of the wiper on the array is
controlled by the user through the 2-wire serial bus interface.
• Package Options
14 L d TSSOP
• Zero Amplitude Wiper Switching
• Pb-Free Plus Anneal Available (RoHS Compliant)
Audio Performance
Power-up reset the wiper to the mute position.
• 0 to - 62dB Volume Control
Pinout
• -92dB Mute
- Power-Up to Mute Position
X9460
(14 LD TSSOP)
TOP VIEW
• SNR -96dB
• THD+N: -95dB @1kHz
SDA
1
14
V-
SCL
VCC
2
13
RH-right
12
RL-right
V+
VSS
4
11
RW-right
5
10
A0
6
A1
7
9
8
RH-left
RL-left
3
X9460
• Crosstalk Rejection: -102dB @ 1kHz
• Channel-to-Channel Variation: ± 0.1dB
• 3dB-Cutoff: 100kHz
Applications
RW-left
• Set Top Boxes
• Stereo Amplifiers
• DVD Players
• Portable Audio Products
Ordering Information
PART NUMBER
PART MARKING
X9460KV14I*
X9460KV I
X9460KV14IZ* (Note)
X9460KV Z I
X9460KV14I-2.7*
X9460KV G
X9460KV14IZ-2.7* (Note)
X9460KV Z G
VCC LIMITS (V)
TEMP RANGE (°C)
5V ± 10%
-40 to +85
14 Ld TSSOP
-40 to +85
14 Ld TSSOP (Pb-free)
-40 to +85
14 Ld TSSOP
-40 to +85
14 Ld TSSOP (Pb-free)
2.7 to 5.5
PACKAGE
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8203 Rev 2.00
October 17, 2005
Page 1 of 16
X9460
Simplified Functional Diagram
RH-Left
VCC
RH-Right
V+
62dB total
Power-on
Recall
mute
data
address
I2C
bus
select
inc/dec
BUS
INTERFACE
CONTROL &
REGISTER
VSS
POT
Left
RW-Left
RL-Left
POT
Right
RW-Right
RL-Right
STEP SIZE
# OF
STEPS
-1dB
11
-2dB
10
-3dB
5
-4dB
4
Mute
1
V-
Detailed Functional Diagram
V+
VCC
Power-on
Recall
mute
SCL
SDA
A0
A1
INTERFACE
AND
CONTROL
CIRCUITRY
RH-Left
WIPER
COUNTER
REGISTER
(WCR)
RL-Left
POT Left
RW-Left
8
RW-Right
D ATA
RH-Right
WIPER
COUNTER
REGISTER
(WCR)
RL-Right
POT Right
VSS
FN8203 Rev 2.00
October 17, 2005
V-
Page 2 of 16
X9460
Typical Application
Audio
Audio
DAC
Gain / Volume Control
X9460
2 XDCP
Amplifier
Left
Left Channel Control
Right Channel Control
Audio => RHL, RHR
Simultaneous Left and Right Channel
Control
RWL, RWR => Amplifier
Audio
Power-up in Mute
Amplifier
Right
µController
Serial Bus
EEPROM
Pin Assignments
PIN
(TSSOP)
SYMBOL
1
SDA
Serial Data
2
SCL
Serial Clock
3
VCC
System Supply Voltage
4
V+
Positive Analog Supply
5
VSS
System Ground
6
A0
Device Address
7
A1
Device Address
8
RW-left
Wiper terminal of the Left Potentiometer
9
RL-left
Negative terminal of the Left Potentiometer
10
RH-left
Positive terminal of the Left Potentiometer
11
RW-right
Wiper terminal of the Right Potentiometer
12
RL-right
Negative terminal of the Right Potentiometer
13
RH-right
Positive terminal of the Right Potentiometer
14
V-
FN8203 Rev 2.00
October 17, 2005
FUNCTION
Negative Analog Supply
Page 3 of 16
X9460
Detailed Pin Description
Host Interface Pins
SERIAL CLOCK (SCL)
The SCL input clocks data into and out of the X9460.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into and out of
the device. It is an open drain output and may be wire-ORed
with any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
DEVICE ADDRESS (A1 - A0)
The Address inputs are used to set the least significant 2 bits
of the 8-bit Slave Byte Address. A match in the slave address
serial data stream must be made with the Address input in
order to initiate communication with the X9460. Up to 4 X9460s
may be connected to a single I2C serial bus and written to
(NOTE: you cannot read from more than one device on the
same 2-wire bus). If left floating, these pins are internally pulled
to ground.
Slave Byte (bits, MSB-LSB) = 0101 0 A1 A0 R/W
Potentiometer Pins
RH-LEFT, RL-LEFT, RH-RIGHT, RL-RIGHT
The RH and RL inputs are equivalent to the terminal connections
on either end of a mechanical potentiometer.
RW-LEFT, RW-RIGHT
The VSS pin is always connected to the system common or
ground. VH, VL, VW are the voltages on the RH, RL, and RW
potentiometer pins.
X9460 Principles of Operation
The X9460 is a highly integrated microcircuit incorporating two
resistor arrays with their associated registers, counters and the
serial interface logic providing direct communication between
the host and the DCP potentiometers. This section provides
detailed description as following:
- Resistor Array Description
- Serial Interface Description
- Command Set and Register Information Description
Resistor Array Description
The X9460 is comprised of two resistor arrays. Each array
contains 31 discrete resistive segments that are connected in
series. The physical ends of each array are equivalent to the
fixed terminals of a mechanical potentiometer (RH and RL
inputs). Tables 1 and 2 provide a description of the step size
and tap positions.
At both ends of each array and between each resistor segment
is a CMOS switch connected to the wiper (RW) output. Within
each individual array only one switch may be turned on at a
time. These switches are controlled by the Wiper Counter
Register (WCR). The five bits of the WCR are decoded to
select, and enable, one of thirty-two switches.
TABLE 1. TOTAL -62dB RANGE PLUS MUTE POSITION
STEP SIZE
# OF STEPS
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
-1dB
11 steps
- 2dB
10 steps
Supply Pins
- 3dB
5 steps
ANALOG SUPPLY V- AND V+
- 4dB
4 steps
The positive power supply for the DCP analog control section
is connected to V+. The negative power supply for the DCP
analog control section is connected to V-.
Mute
1 step
DIGITAL SUPPLIES VCC, VSS
The power supplies for the digital control sections.
Power-up and Down Recommendations
There are no restrictions on the power-up condition of VCC, V+
and V- and the voltages applied to the potentiometer pins
provided that the VCC and V+ are more positive or equal to the
voltage at RH, RL, and RW, ie. VCC, V+ > RH, RL, RW. At all
times, the voltages on the potentiometer pins must be less
than V+ and more than V-.
TABLE 2. WIPER TAP POSITION vs dB
TAP POSITION, n
dB
MIN/MAX dB
for n = 20 to 31
n - 31
-11/0
for n = 10 to 19
2n-51
-31/-13
for n = 5 to 9
3n-61
-46/-34
for n = 1 to 4
4n-66
-62/-50
n=0
-92
-92
The following VCC ramp rate spec is always in effect.
0.2 V/ms < VCC ramp < 50 V/ms
FN8203 Rev 2.00
October 17, 2005
Page 4 of 16
X9460
Serial Interface Description
Stop Condition
Serial Interface
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is HIGH.
The X9460 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The
device controlling the transfer is a master and the device being
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. The X9460 is a slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions.
Start Condition
All commands to the X9460 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while SCL
is HIGH. The X9460 continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition is met.
SCL FROM
MASTER
1
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices on
the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will release
the SDA bus after transmitting eight bits. The master generates
a ninth clock cycle and during this period the receiver pulls the
SDA line LOW to acknowledge that it successfully received the
eight bits of data.
The X9460 will respond with an acknowledge: 1) after
recognition of a start condition and after an identification and
slave address byte, and 2) again after each successful receipt
of the instruction or databyte. See Figure 1.
Invalid Commands
For any invalid commands or unrecognizable addresses, the
X9460 will NOT acknowledge and return the X9460 to the idle
state.
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
ACKNOWLEDGE
ST AR T
FIGURE 1. ACKNOWLEDGE RESPONSE FROM RECEIVER
FN8203 Rev 2.00
October 17, 2005
Page 5 of 16
X9460
Command Set and Register Description
Device Addressing
Following a start condition the master must output the Slave
Byte Address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier
(refer to Figure 2). For the X9460 this is fixed as 0101.
DEVICE TYPE
IDENTIFIER
0
1
0
1
0
A1
A0
R/W
DEVICE ADDRESS
FIGURE 2. SLAVE BYTE ADDRESS
The next three bits of the Slave Byte Address are the device
address. The device address is defined by the A1 - A0 inputs.
The X9460 compares the serial data stream with the Slave
Byte Address; a successful compare is required for the X9460
to respond with an acknowledge. The A1 - A0 inputs can be
actively driven by CMOS input signals or tied to VCC or VSS.
The R/W bit sets the device for read or write operations. Note
that the X9460 supports reads and writes to a single device on
the 2-wire bus. If more than one X9460 is used on the same 2wire bus, those devices must have unique device addresses
and only writes are supported. You may not read from multiple
devices or contention will result and the data is not valid.
and the X9460. These instructions are: Read Wiper Counter
Register, Write Wiper Counter Register. The sequence of
operations is shown in Figure 4 and 5. The four-byte command
is used for write command for both right and left pots (Figure
6).
Special Commands
Increment/Decrement Instruction. The Increment/Decrement
command is different from the other commands. Once the
command is issued and the X9460 has responded with an
acknowledge, the master can clock the selected wiper up
and/or down. For each SCL clock pulse (tHIGH) while SDA is
HIGH, the selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCL clock pulse
while SDA is LOW, the selected wiper will move one resistor
segment towards the RL terminal. A detailed illustration of the
sequence and timing for this operation are shown in Figures 7
and 8 respectively.
Wiper Counter Register
The X9460 contains two Wiper Counter Registers. The Wiper
Counter Register output is decoded to select one of thirty-two
switches along its resistor array. The Write Wiper Counter
Register command directly sets the WCR to a value. The
Increment/Decrement instruction steps the register value up or
down one to multiple times.
The WCR is a volatile register (Table 3) and is reset to the
mute position (tap 0, “zero”) at power-up.
TABLE 3. WIPER COUNTER REGISTERS, 5-bit - VOLATILE:
WCR4
Command Set
After a Slave Byte Address match, the next byte sent contains
the Command and register pointer information. The four most
significant bits are the Command. The next bit is a “X” (don’t
care) set to zero.
(MSB)
WCR3
WCR2
WCR1
WCR0
(LSB)
The X9460 contains one 5-bit Wiper Counter Register for each
DCP. (Two 5-bit registers in total.)
this bit not used, set to 0
I3
I2
I1
INSTRUCTIONS
I0
0
ZD
RT
LT
WIPER COUNTER
SELECT
FIGURE 3. COMMAND BYTE FORMAT
The ZD bit enables and disables the Zero Amplitude Wiper
Switching circuit. When ZD=1, the wiper switches will turn on
when close-to-zero amplitude is detected across the
potentiometer pins. When ZD=0, this circuit is disabled. The
last two bits, LT (left POT enable) and RT (right POT enable),
select which of the two potentiometers is affected by the
instruction.
Several instructions require a three-byte sequence to
complete. These instructions transfer data between the host
FN8203 Rev 2.00
October 17, 2005
Page 6 of 16
X9460
TABLE 4. COMMAND SET
INSTRUCTION SET
INSTRUCTION
I2
I3
I1
I0
X
ZD
RT
LT
OPERATION
Read Wiper
LSB of Slave Byte=1, no command required
Slave will return Left then Right Data( not to be used with more
than one device on the 2-wire bus)
Write Left Wiper Counter
1
0
1
0
0
1/0
0
1
Write new value to the Wiper Counter Register
Write Right Wiper Counter
1
0
1
0
0
1/0
1
0
Write new value to the Wiper Counter Register
Write Both Wiper Counters
1
0
1
0
0
1/0
1
1
Write new value to the Wiper Counter Register
Inc/Dec Left Wiper Counter
0
0
1
0
0
1/0
0
1
Enable Increment/decrement of the Control Latch
Inc/Dec Right Wiper Counter
0
0
1
0
0
1/0
1
0
Enable Increment/decrement of the Control Latch
Inc/Dec Both Wiper Counters
0
0
1
0
0
1/0
1
1
Enable Increment/decrement of the Control Latch
Notes: “1/0” = data is one or zero
SCL
SDA
S
T
A
R
T
0
1
0
1
0
A1
A0
1
0
0
0
R/W A
C
K
0
0
0
DEVICE TYPE
IDENTIFIER
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
A
C
K
0
0
0
0
0
0
LEFT POT
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
A
C
K
S
T
O
P
A
C
K
S
T
O
P
RIGHT POT
DATA BYTE
DATA BYTE
FIGURE 4. THREE-BYTE COMMAND SEQUENCE (READ, SINGLE DEVICE ON THE 2-WIRE BUS ONLY)
SCL
SDA
S
T
A
R
T
0
1
0
1
0
A1
A0
0
1
0
R/W A
C
K
I3
I2
1
0
0
I1
I0
0
ZD
DEVICE TYPE
IDENTIFIER
RT LT
A
C
K
0
0
0
0
0
0
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
RIGHT or LEFT POT
INSTRUCTION BYTE
DATA BYTE
FIGURE 5. THREE-BYTE COMMAND SEQUENCE (WRITE)
FN8203 Rev 2.00
October 17, 2005
Page 7 of 16
X9460
SCL
SDA
0
S 0 1 0 1 0
T
A
R DEVICE TYPE
T IDENTIFIER
1
0
1
A1 A0 R/W A I3 I2
C
K
0
I1 I0
0
1
1
0 ZD RT LT A
C
K
0
0
0
0
0
W
0 C
R
4
INSTRUCTION BYTE
W
C
R
3
W
C
R
2
W
C
R
1
W
C A
R C
0 K
0
0
0
0
0
W
0 C
R
4
W
C
R
3
W
C
R
2
LEFT POT
RIGHT POT
DATA BYTE
DATA BYTE
W W
C C
R R
1 0
A S
C T
K O
P
FIGURE 6. FOUR-BYTE COMMAND SEQUENCE (WRITE)
SCL
SDA
S
T
A
R
T
0
1
0
1
0
A1
A0
0
0
0
1
0
0
R/W A
C
K
I3
I2
I1
I0
0
DEVICE TYPE
IDENTIFIER
ZD
RT LT
A
C
K
INSTRUCTION BYTE
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
INC and DEC ACTIVE
FIGURE 7. INCREMENT/DECREMENT COMMAND SEQUENCE (WRITE)
INC/DEC
CMD
ISSUED
t WRID
SCL
SD A
RW
VOLTAGE OUT
Wiper can move within 10µs after the falling edge of SCL
FIGURE 8. INCREMENT/DECREMENT TIMING LIMITS
FN8203 Rev 2.00
October 17, 2005
Page 8 of 16
X9460
Instruction Formats
Read Wiper Counter Register (Single device on 2-wire bus only)
device
S device type
identifier
addresses
T
A
R 0 1 0 1 0 A A
1 0
T
R/W=1
S
A
C
K
Left wiper position
(sent by slave on SDA)
Right wiper position
M (sent by slave on SDA)
A
L L L L L C
R R R R R
0 0 0 D D D D D
0 0 0 D D D D D
K
4 3 2 1 0
4 3 2 1 0
M
A
C
K
S
T
O
P
Write Wiper Counter Register
device
S device type
identifier
addresses
T
A
R
A A
T 0 1 0 1 0 1 0
R/W=0
S
A
C
K
Left or Right wiper
position
S
S S
(sent
by
master on SDA) A T
A
C
C O
Z R L K
D D D D D K P
1 0 1 0 0
0 0 0
D T T
4 3 2 1 0
instruction
opcode
wiper
addresses
Write Both Wiper Counter Registers
R/W=0
device
S device type
addresses
T identifier
A
R
A A
0 1 0 1 0
1 0
T
instruction
wiper
S opcode addresses
A
C
Z
K 1 0 1 0 0
1 1
D
Left wiper position
(sent by master on
SDA)
S
A
C
L L L L L
K 0 0 0 D D D D D
4 3 2 1 0
Right wiper position
(sent by master on
SDA)
S
A
C
R R R R R
K 0 0 0 D D D D D
4 3 2 1 0
S
A
C
K
S
T
O
P
Increment/Decrement Wiper Counter Register
device
addresses
0
A1 A0
R/W=0
S device type
identifier
T
A
R 0 1 0 1
T
instruction
wiper
S
opcode
addresses
A
C
0 0 1 0 0 ZD RT LT
K
increment/decrement
S
(sent by master on SDA)
A
C
I/D I/D . . . . I/D I/D
K
S
T
O
P
Definitions:
1. “MACK”/“SACK”: stands for the acknowledge sent by the master/slave.
2. “A1 ~ A0”: stands for the device addresses sent by the master.
3. “I”: stands for the increment operation, SDA held high during active SCL phase (high).
4. “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
FN8203 Rev 2.00
October 17, 2005
Page 9 of 16
X9460
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under Bias. . . . . . . . . . . . . . . . . . . . . .-65C to +135C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
Voltage on SDA, SCL or any Address Input
with Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +6V
Voltage on V+ (referenced to VSS). . . . . . . . . . . . . . . . . . . . . . . .+6V
Voltage on V- (referenced to VSS) . . . . . . . . . . . . . . . . . . . . . . . . -6V
(V+) - (V-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Any RH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+
Any RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VLead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300C
IW max (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40°C to 85°C
X9460V14-2.7
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
V- Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -2.7V
V+ Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7V to +5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation
of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Analog Specifications
Over the recommended operating conditions unless otherwise specified (Note 1)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE (Notes 2, 3)
Control Range
-62
0
dB
Mute Mode
@1V rms
-92
SNR
Signal Noise Ratios (Unweighted)
@1V rms @ 1kHz, Tap = -6dB
-96
dB
THD + N
Total Harmonic Distortion + Noise
@1V rms @ 1kHz, Tap = -6dB
-95
dB
DCP Isolation
@1kHz, tap = -6dB
-102
dB
Digital Feedthrough
(Peak Component)
tap = -6dB
-105
dB
100
kHz
XTalk
-3db Cutoff Frequency
dB
DC ACCURACY
Step Size
Steps of -1, -2, -3, -4 dB
-1
-4
dB
Step Size Error
For -1dB steps
-0.2
+0.2
dB
Step Size Error
For -2dB steps
-0.4
+0.4
dB
Step Size Error
For -3dB steps
-0.6
+0.6
dB
Step Size Error
For -4dB steps
-0.8
+0.8
dB
-0.1
0.1
dB
DCP to DCP Matching
NOTES:
1. VCC = | V- |
VCC Ramp up timing 0.2V/ms < Vcc Ramp Rate < 50V/ms
2. This parameter is guaranteed by design and characterization
3. TA = 25oC, VCC = 5.0V; 2 Hz to 20kHz Measurement Bandwidth with 80kHz filter, input signal 1Vrms, 1kHz Sine Wave.
Analog Specifications
Over the recommended operating conditions unless otherwise specified (Note 1)
ANALOG INPUTS
SYMBOL
PARAMETER
VTERM
Voltage on RL, RW, and RH pins
RTOTAL
End to End Resistance
Cin (Note 4) Input Capacitance RL, RH, RW
IW (NOte 2)
TEST CONDITIONS
Typical 33k
TA =
MIN
MAX
UNIT
V-
V+
V
-20
+20
%
25oC
Wiper Current
TYP
25
-3
pF
+3
mA
200
RW
Wiper Resistance
V-
Voltage on V- pin
-5.5
-2.7
V
V+
Voltage on V+ pin
+2.7
+5.5
V
FN8203 Rev 2.00
October 17, 2005
Wiper Current = ±3mA
100
Page 10 of 16
X9460
Analog Specifications
Over the recommended operating conditions unless otherwise specified (Note 1) (Continued)
ANALOG INPUTS
SYMBOL
PARAMETER
TEST CONDITIONS
Noise
MIN
20Hz to 20kHz, Grounded Input @ -6dB tap
TCR (Note 2) Temperature Coefficient of resistance
DC Electrical Specifications
TYP
MAX
UNIT
2
Vrms
-300
PPM/°C
Over the recommended operating conditions unless otherwise specified. (Note 1)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
200
300
A
ICC1
VCC Supply Current (Move Wiper,
Write, Read)
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
ISB
VCC Current (Standby)
SCL = SDA = VCC, Addr. = VSS
3
ILI
Input Leakage Current
VIN = VSS to VCC
1
Iai
Analog Input Leakage
VIN = V- to V+ with all other
analog inputs floating
ILO
Output Leakage Current
VOUT = VSS to VCC
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VOL
Output LOW Voltage
A
A
10
A
0.1
10
A
VCC x 0.7
VCC + 0.5
V
-0.5
VCC x 0.1
V
0.4
V
IOL = 3mA
Capacitance
SYMBOL
TEST
TEST CONDITIONS
MAX
UNITS
CI/O (Note 4)
Input/Output Capacitance (SDA)
VI/O = 0V
8
pF
CIN (NOte 4)
Input Capacitance (A0, A1, A2 and SCL)
VIN = 0V
6
pF
NOTE:
4. This parameter is not 100% tested.
FN8203 Rev 2.00
October 17, 2005
Page 11 of 16
X9460
Equivalent A.C. Load Circuit
A.C. Test Conditions
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
Input and Output Timing Level
5V
10ns
1533
VCC x 0.5
SDA OUTPUT
100pF
AC TIMING
Over recommended operating conditions
SYMBOL
PARAMETER
MIN
MAX
UNITS
400
kHz
fSCL
Clock Frequency
tCYC
Clock Cycle Time
2500
ns
tHIGH
Clock High Time
600
ns
tLOW
Clock Low Time
1300
ns
tSU:STA
Start Setup Time
600
ns
tHD:STA
Start Hold Time
600
ns
tSU:STO
Stop Setup Time
600
ns
tSU:DAT
SDA Data Input Setup Time
500
ns
tHD:DAT
SDA Data Input Hold Time
50
ns
tR (Note 2)
SCL and SDA Rise Time
300
ns
tF (Note 2)
SCL and SDA Fall Time
300
ns
tAA (Note 2)
SCL Low to SDA Data Output Valid Time
900
ns
tDH (Note 2)
SDA Data Output Hold Time
50
ns
Noise Suppression Time Constant at SCL and SDA inputs
50
ns
1300
ns
TI (Note 2)
tBUF (Note 2) Bus Free Time (Prior to Any Transmission)
tSU:WPA
A0, A1 (Note 2)
0
ns
tHD:WPA
A0, A1 (Note 2)
0
ns
DC Timing (Note 2)
SYMBOL
PARAMETER
MIN
MAX
UNITS
tWRPO
Wiper Response Time After The Third (Last) Power Supply Is Stable
10
s
tWRL
Wiper Response Time After Instruction Issued (All Load Instructions)
10
s
tWRID
Wiper Response Time From An Active SCL Edge (Increment/Decrement Instruction)
10
s
FN8203 Rev 2.00
October 17, 2005
Page 12 of 16
X9460
Timing Diagrams
(START)
(STOP)
tF
tR
SCL
tSU:STA
tHD:STA
tSU:STO
tF
tR
SDA
FIGURE 9. START AND STOP TIMING
tCYC
tHIGH
SCL
tLOW
SDA
tSU:DAT
tHD:DAT
tBUF
FIGURE 10. INPUT TIMING
SCL
SDA
tDH
tAA
FIGURE 11. OUTPUT TIMING
(STOP)
SCL
SDA
LSB
tWRL
VWx
FIGURE 12. DCP TIMING (FOR ALL LOAD INSTRUCTIONS)
FN8203 Rev 2.00
October 17, 2005
Page 13 of 16
X9460
Typical Performance Characteristics
(Vcc, V+ = 5.0V, V- = -5.0V, TA = + 25 °C, unless otherwise noted)
FFT Spectrum
(with 1kHz 1Vrms input, tap = -6dB)
+0
-1 0
-2 0
-3 0
-4 0
-5 0
-6 0
-7 0
d
B
V
-8 0
-9 0
-1 0 0
-1 1 0
-1 2 0
-1 3 0
-1 4 0
-1 5 0
-1 6 0
-1 7 0
-1 8 0
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
FIGURE 13. SINGLE TONE FREQUENCY RESPONSE
THD+N vs Frequency
(with 80kHz low-pass filter, tap = -6dB)
-6 0
-6 5
-7 0
-7 5
-8 0
-8 5
d
B
-9 0
-9 5
-1 00
-1 05
-1 10
-1 15
-1 20
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
FIGURE 14. THD + N
FN8203 Rev 2.00
October 17, 2005
Page 14 of 16
X9460
Typical Performance Characteristics
(Vcc, V+ = 5.0V, V- = -5.0V, TA = + 25 °C, unless otherwise noted)
Mut e Mod e
+0
-10
-20
-30
-40
-50
-60
d
B
V
-70
-80
-90
-100
-110
-120
-130
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
FIGURE 15. MUTE
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For additional products, see www.intersil.com/en/products.html
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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN8203 Rev 2.00
October 17, 2005
Page 15 of 16
X9460
Packaging Information
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
.019 (.50)
.029 (.75)
Seating Plane
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8203 Rev 2.00
October 17, 2005
Page 16 of 16
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