X9460KV14I

Typical Applications: –Set Top Boxes –Stereo Amplifiers New Feature –DVD Players –Portable Audio Products Zero Amplitude Wiper Switching Low Noise, Low Cost, High End Features, Dual Audio Log Potentiometer X9460 Dual Audio Control Digitally Controlled Potentiometer (XDCPTM) FEATURES DESCRIPTION • Dual audio control – Two 32 taps Log pots • Zero Amplitude Wiper Switching • 2-wire serial interface 4 cascadable slave byte addresses [A1,A0] • Total resistance: 33KΩ each XDCP (Typical) • Dual Voltage Operation V+/V- = ±2.7 to ±5.5V • Temp Range = -40oC to +85 oC • Package Options 14-Lead TSSOP The X9460 integrates two digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The two XDCPs can be used as stereo gain controls in audio applications. Read/Write operations can directly access each channel independently or both channels simultaneously. Increment/ Decrement can adjust each channel independently or both channels simultaneously. AUDIO PERFORMANCE The X9460 contains a zero amplitude wiper switching circuit that delays wiper changes until the next zero crossing of the audio signal. • 0 to - 62dB volume control • -92dB Mute —Power up to mute position • SNR -96dB • THD+N: -95dB @1k HZ • Crosstalk rejection: -102dB @ 1k HZ • Channel-to-channel variation: ± 0.1dB • 3dB-cutoff: 100kHz The digitally controlled potentiometer is implemented using 31 polysilicon resistors in a log array. Between each of the resistors are tap points connected to the wiper terminal through switches. The XDCPs are designed to minimize wiper noise to avoid pops and clicks during audio volume transitions. The position of the wiper on the array is controlled by the user through the 2-wire serial bus interface. Power up reset the wiper to the mute position. SIMPLIFIED FUNCTIONAL DIAGRAM RH-Left VCC RH-Right V+ 62dB total Power On Recall mute data address 2 IC bus BUS INTERFACE CONTROL & REGISTER VSS REV 4.2 7/8/04 select inc / dec POT Left RW-Left RL-Left POT Right RW-Right www.xicor.com RL-Right Step Size # of Steps -1dB 11 -2dB 10 -3dB 5 -4dB 4 Mute 1 V- Characteristics subject to change without notice. 1 of 17 X9460 DETAILED FUNCTIONAL DIAGRAM V+ VCC Power On Recall mute SCL SDA A0 A1 INTERFACE AND CONTROL CIRCUITRY RH-Left WIPER COUNTER REGISTER (WCR) RL-Left POT Left RW-Left 8 RW-Right DATA RH-Right WIPER COUNTER REGISTER (WCR) RL-Right POT Right V- VSS TYPICAL APPLICATION X9460 2 XDCP Audio DAC Gain / Volume Control Audio Amplifier Left Left Channel Control Right Channel Control Simultaneous Left and Right Channel Control Audio => RHL, RHR RWL, RWR => Amplifier Power up in Mute. µController Audio Amplifier Right Serial Bus EEPROM REV 4.2 7/8/04 www.xicor.com Characteristics subject to change without notice. 2 of 17 X9460 PIN CONFIGURATION TSSOP SDA SCL VCC V+ VSS A1 A0 14 1 13 2 3 12 4 X9460 11 5 10 6 9 8 7 VRH-right RL-right RW-right RH-left RL-left RW-left PIN ASSIGNMENTS Pin (TSSOP) Symbol 1 SDA Serial Data 2 SCL Serial Clock 3 VCC System Supply Voltage 4 V+ Positive Analog Supply Function 5 VSS System Ground 6 A1 Device Address 7 A0 Device Address 8 RW-left Wiper terminal of the Left Potentiometer 9 RL-left Negative terminal of the Left Potentiometer 10 RH-left Positive terminal of the Left Potentiometer 11 RW-right Wiper terminal of the Right Potentiometer 12 RL-right Negative terminal of the Right Potentiometer 13 RH-right Positive terminal of the Right Potentiometer 14 V- REV 4.2 7/8/04 Negative Analog Supply www.xicor.com Characteristics subject to change without notice. 3 of 17 X9460 DETAILED PIN DESCRIPTION: Host Interface Pins SERIAL CLOCK (SCL) The SCL input clocks data into and out of the X9460. SERIAL DATA (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. DEVICE ADDRESS (A1- A0) The Address inputs are used to set the least significant 2 bits of the 8-bit Slave Byte Address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9460. Up to 4 X9460s may be directly connected to a single I2C serial bus. If left floating, these pins are internally pulled to ground. Slave Byte (bits, MSB-LSB) = 0101 0 A1 A0 R/W Potentiometer Pins RH-LEFT, RL-LEFT, RH-RIGHT, RL-RIGHT The RH and RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. RW-LEFT, RW-RIGHT The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Supply Pins ANALOG SUPPLY V- AND V+ Power Up and Down Recommendations There are no restrictions on the power-up condition of VCC, V+ and V- and the voltages applied to the potentiometer pins provided that the Vcc and V+ are more positive or equal to the voltage at RH, RL , and Rw, ie. Vcc, V+ > RH, RL, Rw. At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. The following VCC ramp rate spec is always in effect. 0.2 V/ms < VCC ramp < 50 V/ms The VSS pin is always connected to the system common or ground. VH, VL, VW are the voltages on the RH, RL, and RW potentiometer pins. X9460 PRINCIPLES OF OPERATION The X9460 is a highly integrated microcircuit incorporating two resistor arrays with their associated registers, counters and the serial interface logic providing direct communication between the host and the DCP potentiometers. This section provides detailed description as following: – Resistor Array Description – Serial Interface Description – Command Set and Register Information Description RESISTOR ARRAY DESCRIPTION The X9460 is comprised of two resistor arrays. Each array contains 31 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). Tables 1 and 2 provide a description of the step size and tap positions. At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The five bits of the WCR are decoded to select, and enable, one of thirty-two switches. Table 1. Total -62dB range Plus Mute Position The positive power supply for the DCP analog control section is connected to V+. The negative power supply for the DCP analog control section is connected to V-. Digital Supplies VCC, VSS The power supplies for the digital control sections. REV 4.2 7/8/04 www.xicor.com Step Size # of Steps -1 dB 11 steps - 2 dB 10 steps - 3 dB 5 steps - 4 dB 4 steps Mute 1 step Characteristics subject to change without notice. 4 of 17 X9460 Table 2. Wiper Tap Position vs dB. Tap Position, n dB Min/Max dB for n = 20 to 31 for n = 10 to 19 for n = 5 to 9 for n = 1 to 4 n=0 n - 31 2n-51 3n-61 4n-66 -92 -11 / 0 -31 / -13 -46 / -34 -62 / -50 -92 SERIAL INTERFACE DESCRIPTION Serial Interface The X9460 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. The X9460 is a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Start Condition All commands to the X9460 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9460 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9460 will respond with an acknowledge: 1) after recognition of a start condition and after an identification and slave address byte, and 2) again after each successful receipt of the instruction or databyte. See Figure 1. Invalid Commands For any invalid commands or unrecognizable addresses, the X9460 will NOT acknowledge and return the X9460 to the idle state. Figure 1. Acknowledge Response from Receiver SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START REV 4.2 7/8/04 ACKNOWLEDGE www.xicor.com Characteristics subject to change without notice. 5 of 17 X9460 COMMAND SET AND REGISTER DESCRIPTION DEVICE ADDRESSING Following a start condition the master must output the Slave Byte Address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 2 below). For the X9460 this is fixed as 0101. Figure 2. Slave Byte Address DEVICE TYPE IDENTIFIER 0 1 0 1 0 A1 A0 R/W DEVICE ADDRESS The next three bits of the Slave Byte Address are the device address. The device address is defined by the A1–A0 inputs. The X9460 compares the serial data stream with the Slave Byte Address; a successful compare is required for the X9460 to respond with an acknowledge. The A1–A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The R/W bit sets the device for read or write operations. Command Set After a Slave Byte Address match, the next byte sent contains the Command and register pointer information. The four most significant bits are the Command. The next bit is a “X” (don’t care) set to zero. this circuit is disabled. The last two bits, LT (left POT enable) and RT (right POT enable), select which of the two potentiometers is affected by the instruction. Several instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9460. These instructions are: Read Wiper Counter Register, Write Wiper Counter Register. The sequence of operations is shown in Figure 4 and 5. The four-byte command is used for write command for both right and left pots (Figure 6). Special Commands Increment / Decrement Instruction. The Increment/ Decrement command is different from the other commands. Once the command is issued and the X9460 has responded with an acknowledge, the master can clock the selected wiper up and/or down. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 7 and 8 respectively. Wiper Counter Register The X9460 contains two Wiper Counter Registers. The Wiper Counter Register output is decoded to select one of thirty-two switches along its resistor array. The Write Wiper Counter Register command directly sets the WCR to a value. The Increment/Decrement instruction steps the register value up or down one to multiple times. The WCR is a volatile register (Table 3) and is reset to the mute position (tap 0, “zero”) at power-up. Figure 3. Command Byte Format this bit not used, set to 0 Table 3. Wiper Counter Registers, 5-bit - volatile: WCR4 I3 I2 I1 I0 INSTRUCTIONS 0 ZD RT (MSB) LT WIPER COUNTER SELECT WCR3 WCR2 WCR1 WCR0 (LSB) The X9460 contains one 5-bit Wiper Counter Register for each DCP. (Two 5-bit registers in total.) The ZD bit enables and disables the Zero Amplitude Wiper Switching circuit. When ZD=1, the wiper switches will turn on when close-to-zero amplitude is detected across the potentiometer pins. When ZD=0, REV 4.2 7/8/04 www.xicor.com Characteristics subject to change without notice. 6 of 17 X9460 Table 2a. Command Set Instruction I3 I2 Instruction Set I1 I0 X ZD RT LT Read Wiper Operation Write Left Wiper Counter Write Right Wiper Counter Write Both Wiper Counters 1 0 1 0 0 1/0 0 1 LSB of Slave Byte=1, no command required Slave will return Left then Right Data Write new value to the Wiper Counter Register 1 0 1 0 0 1/0 1 0 Write new value to the Wiper Counter Register 1 0 1 0 0 1/0 1 1 Write new value to the Wiper Counter Register Inc/Dec Left Wiper Counter Inc/Dec Right Wiper Counter Inc/Dec Both Wiper Counters 0 0 1 0 0 1/0 0 1 Enable Increment/decrement of the Control Latch 0 0 1 0 0 1/0 1 0 Enable Increment/decrement of the Control Latch 0 0 1 0 0 1/0 1 1 Enable Increment/decrement of the Control Latch Notes: “1/0” = data is one or zero Figure 4. Three-Byte Command Sequence (Read) SCL SDA 1 S T A R T 0 1 0 1 0 A1 A0 R/W A C K 0 0 0 0 0 0 DEVICE TYPE IDENTIFIER W C R 4 W C R 3 W C R 2 W C R 1 W C R 0 A C K 0 0 0 0 0 0 W C R 4 W C R 3 W C R 2 LEFT POT RIGHT POT DATA BYTE DATA BYTE W C R 1 W C R 0 A C K S T O P W C R 1 W C R 0 A C K S T O P Figure 5. Three-Byte Command Sequence (Write) SCL SDA 0 S T A R T 0 1 0 1 0 A1 A0 R/W A C K 1 0 I3 I2 1 0 0 I1 I0 0 ZD RT LT A C K DEVICE TYPE IDENTIFIER 0 0 0 0 0 W C R 4 W C R 3 W C R 2 RIGHT or LEFT POT INSTRUCTION BYTE REV 4.2 7/8/04 0 www.xicor.com DATA BYTE Characteristics subject to change without notice. 7 of 17 X9460 Figure 6. Four-Byte Command Sequence (Write) SCL SDA 0 1 0 1 0 0 1 0 0 1 0 0 0 0 W W W I1 I0 0 ZD RT LT A 0 0 0 C C C C R R R K 4 3 2 LEFT POT S 0 1 0 1 0 A1 A0 R/W A I3 I2 T C A K R DEVICE TYPE T IDENTIFIER INSTRUCTION BYTE W C R 1 W W W W C A 0 0 0 C C C R R R R C 4 3 2 0 K RIGHT POT DATA BYTE W C R 1 W C A S R C T 0 K O P DATA BYTE Figure 7. Increment/Decrement Command Sequence (Write) SCL SDA 0 S T A R T 0 1 0 1 0 A1 A0 R/W A C K 0 0 1 0 0 I3 I2 I1 I0 0 DEVICE TYPE IDENTIFIER ZD RT LT A C K I N C 1 INSTRUCTION BYTE I N C 2 I N C n D E C 1 D E C n S T O P INC and DEC active Figure 8. Increment/Decrement Timing Limits INC/DEC CMD ISSUED t WRID SCL SDA RW VOLTAGE OUT Wiper can move within 10µsecs after the falling edge of SCL REV 4.2 7/8/04 www.xicor.com Characteristics subject to change without notice. 8 of 17 X9460 INSTRUCTION FORMATS Read Wiper Counter Register device S device type identifier addresses T A R 0 1 0 1 0 A A 1 0 T R/W=1 S A C K Left wiper position (sent by slave on SDA) Right wiper position M (sent by slave on SDA) A L L L L L C R R R R R 0 0 0 D D D D D K 0 0 0 D D D D D 4 3 2 1 0 4 3 2 1 0 M A C K S T O P Write Wiper Counter Register device S device type identifier addresses T A R A A T 0 1 0 1 0 1 0 R/W=0 S A C K Left or Right wiper position S S S (sent by master on SDA) A T A C C O Z R L K D D D D D K P 1 0 1 0 0 0 0 0 D T T 4 3 2 1 0 instruction opcode wiper addresses Write Both Wiper Counter Registers R/W=0 device S device type identifier addresses T A R A A 0 1 0 1 0 1 0 T instruction wiper S opcode addresses A C Z K 1 0 1 0 0 1 1 D Left wiper position (sent by master on SDA) S A C L L L L L K 0 0 0 D D D D D 4 3 2 1 0 Right wiper position (sent by master on SDA) S A C R R R R R K 0 0 0 D D D D D 4 3 2 1 0 S A C K S T O P Increment/Decrement Wiper Counter Register device addresses 0 A1 A0 R/W=0 S device type identifier T A R 0 1 0 1 T instruction wiper S opcode addresses A C 0 0 1 0 0 ZD RT LT K increment/decrement S (sent by master on SDA) A C I/D I/D . . . . I/D I/D K S T O P Definitions: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave. (2) “A1 ~ A0”: stands for the device addresses sent by the master. (3) “I”: stands for the increment operation, SDA held high during active SCL phase (high). (4) “D”: stands for the decrement operation, SDA held low during active SCL phase (high). REV 4.2 7/8/04 www.xicor.com Characteristics subject to change without notice. 9 of 17 X9460 ABSOLUTE MAXIMUM RATINGS* *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature under Bias .................... -65°C to +135°C Storage Temperature.........................–65°C to +150°C Voltage on SDA, SCL or any Address Input with Respect to VSS ................................–1V to +6V Voltage on V+ (referenced to VSS)......................... +6V Voltage on V- (referenced to VSS)........................... -6V (V+) – (V-).............................................................. 12V Any RH .................................................................... V+ Any RL ...................................................................... VLead Temperature (Soldering, 10 seconds) ...... 300°C IW max (10 secs) ............................................... ± 3mA RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Industrial –40°C +85°C Device Supply Voltage (VCC) V- Limits V+ Limits X9460V14–2.7 2.7V to 5.5V -5.5V to -2.7V +2.7V to +5.5V ANALOG CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)(1) Symbol Dynamic Parameter Min. Typ. Max. Unit 0 dB Test Conditions Performance(2)(3) Control Range -62 Mute Mode -92 dB @1V rms SNR Signal Noise Ratios (Unweighted) -96 dB @1V rms @ 1kHz, Tap = -6dB THD + N Total Harmonic Distortion + Noise -95 dB @1V rms @ 1kHz, Tap = -6dB XTalk DCP Isolation -102 dB @1kHz, tap = -6dB Digital Feedthrough (Peak Component) -105 dB tap = -6dB -3db Cutoff Frequency 100 kHz DC Accuracy Step Size -1 -4 dB Steps of -1, -2, -3, -4 dB Step Size Error -0.2 +0.2 dB For -1dB steps Step Size Error -0.4 +0.4 dB For -2dB steps Step Size Error -0.6 +0.6 dB For -3dB steps Step Size Error -0.8 +0.8 dB For -4dB steps DCP to DCP Matching -0.1 0.1 dB Notes: (1) VCC = | V- | VCC Ramp up timing 0.2 V/ms < Vcc Ramp Rate < 50 V/ms (2) This parameter is guaranteed by design and characterization (3) TA = 25oC, VCC = 5.0V; 20 Hz to 20kHz Measurement Bandwidth with 80kHZ filter, input signal 1Vrms, 1kHz Sine Wave. REV 4.2 7/8/04 www.xicor.com Characteristics subject to change without notice. 10 of 17 X9460 ANALOG CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified)(1) ANALOG INPUTS Symbol Parameter Min. VTERM Voltage on RL, RW, and RH pins RTOTAL End to End Resistance (4) Max. Unit V- V+ V -20 +20 % Typical 33KΩ pF TA = 25oC Cin Input Capacitance RL, RH, RW IW(2) Wiper Current RW Wiper Resistance V- Voltage on V- pin -5.5 V+ Voltage on V+ pin +2.7 Typ. 25 -3 100 Temperature Coefficient of resistance mA 200 Ω -2.7 V +5.5 Wiper Current = ± 3mA V 2 µVrms -300 PPM/°C Noise TCR(2) +3 Test Conditions 20 HZ to 20KHZ, Grounded Input @ -6dB tap D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)(1) Limits Symbol Parameter Min. Typ. Max. Units 200 300 µA fSCL = 400kHz, SDA = Open, Other Inputs = VSS µA SCL = SDA = VCC, Addr. = VSS µA VIN = VSS to VCC µA VIN = V- to V+ with all other analog inputs floating µA VOUT = VSS to VCC ICC1 VCC Supply Current (Move Wiper, Write, Read) ISB VCC Current (Standby) 3 ILI Input Leakage Current 1 Iai Analog Input Leakage 0.1 ILO Output Leakage Current VIH Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VIL Input LOW Voltage –0.5 VCC x 0.1 V VOL Output LOW Voltage 0.4 V 10 10 Test Conditions IOL = 3mA CAPACITANCE Symbol (4) Test Max. Units Test Conditions CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V CIN(4) Input Capacitance (A0, A1, A2 and SCL) 6 pF VIN = 0V Notes: (4) This parameter is not 100% tested. REV 4.2 7/8/04 www.xicor.com Characteristics subject to change without notice. 11 of 17 X9460 A.C. TEST CONDITIONS Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns VCC x 0.5 Input and Output Timing Level EQUIVALENT A.C. LOAD CIRCUIT 5V 1533Ω SDA OUTPUT 100pF AC TIMING (Over recommended operating conditions) Symbol Parameter Min. Max. Units 400 kHz fSCL Clock Frequency tCYC Clock Cycle Time 2500 ns tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 500 ns tHD:DAT SDA Data Input Hold Time 50 ns (2) SCL and SDA Rise Time 300 ns (2) SCL and SDA Fall Time 300 ns 900 ns tR tF (2) tAA SCL Low to SDA Data Output Valid Time tDH(2) SDA Data Output Hold Time 50 ns TI(2) Noise Suppression Time Constant at SCL and SDA inputs 50 ns (2) tBUF tSU:WPA tHD:WPA Bus Free Time (Prior to Any Transmission) 1300 ns A0, A1(2) 0 ns A0, A1(2) 0 ns DCP TIMING(2) Symbol Parameter Min. Max. Units tWRPO Wiper Response Time After The Third (Last) Power Supply Is Stable 10 µs tWRL Wiper Response Time After Instruction Issued (All Load Instructions) 10 µs tWRID Wiper Response Time From An Active SCL Edge (Increment/Decrement Instruction) 10 µs REV 4.2 7/8/04 www.xicor.com Characteristics subject to change without notice. 12 of 17 X9460 TIMING DIAGRAMS Figure 9. START and STOP Timing (START) (STOP) tF tR SCL tSU:STA tHD:STA tR tF tSU:STO SDA Figure 10. Input Timing tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF Figure 11. Output Timing SCL SDA tDH tAA Figure 12. DCP Timing (for All Load Instructions) (STOP) SCL SDA LSB tWRL VWx REV 4.2 7/8/04 www.xicor.com Characteristics subject to change without notice. 13 of 17 X9460 TYPICAL PERFORMANCE CHARACTERISTICS (VCC,V+ = 5.0V,V- = -5.0V, TA = + 25 °C, unless otherwise noted) FFT Spectrum (with 1kHz 1Vrms input, tap = -6dB) +0 -1 0 -2 0 -3 0 -4 0 -5 0 -6 0 -7 0 d B V -8 0 -9 0 -1 0 0 -1 1 0 -1 2 0 -1 3 0 -1 4 0 -1 5 0 -1 6 0 -1 7 0 -1 8 0 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 13. Single Tone Frequency Response THD+N vs Frequency (with 80kHz low-pass filter, tap = -6dB) -6 0 -6 5 -7 0 -7 5 -8 0 -8 5 d B -9 0 -9 5 -1 00 -1 05 -1 10 -1 15 -1 20 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 14. THD + N REV 4.2 7/8/04 www.xicor.com Characteristics subject to change without notice. 14 of 17 X9460 TYPICAL PERFORMANCE CHARACTERISTICS (VCC,V+ = 5.0V,V- = -5.0V, TA = + 25 °C, unless otherwise noted) Mut e Mod e +0 -10 -20 -30 -40 -50 -60 d B V -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 15. Mute REV 4.2 7/8/04 www.xicor.com Characteristics subject to change without notice. 15 of 17 X9460 PACKAGING INFORMATION 14-Lead Plastic, TSSOP, Package Type V .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .193 (4.9) .200 (5.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0° - 8° Seating Plane .019 (.50) .029 (.75) Detail A (20X) .031 (.80) .041 (1.05) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 4.2 7/8/04 www.xicor.com Characteristics subject to change without notice. 16 of 17 X9460 ORDERING INFORMATION X9460 K P T V VCC Limits Device Blank = 5V ± 10% -2.7 = 2.7 to 5.5V Temperature Range Blank = Commercial = 0°C to +70°C I= Industrial = –40°C to +85°C Package V14 = 14-Lead TSSOP Potentiometer Organization K= Left Pot 33KΩ ± 20% Right Pot 33KΩ± 20% X9460 TSSOP 14L Top Mark Instructions Commercial Industrial 5.0 volt X9460KV EYWW X9460KV EYWW I 2.7 volt X9460KV EYWW F X9460KV EYWW G LIMITED WARRANTY ©Xicor, Inc. 2000 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 4.2 7/8/04 www.xicor.com Characteristics subject to change without notice. 17 of 17