IS62LV256AL-45ULI-TR

IS65LV256AL IS62LV256AL 32K x 8 LOW VOLTAGE CMOS STATIC RAM FEBRUARY 2020 FEATURES • • • • • • High-speed access time: 20, 45 ns Automatic power-down when chip is deselected CMOS low power operation — 17 µW (typical) CMOS standby — 50 mW (typical) operating TTL compatible interface levels Single 3.3V power supply Fully static operation: no clock or refresh required • Three-state outputs • Industrial and Automotive temperatures available • Lead-free available DESCRIPTION The ISSI IS62/65LV256AL is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 15 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 150 µW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS62/65LV256AL is available in the JEDEC standard 28-pin SOJ, 28-pin SOP, and the 28-pin TSOP (Type I) package. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K x 8 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 CE OE WE CONTROL CIRCUIT Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. D2 02/07/2020 IS65LV256AL IS62LV256AL PIN CONFIGURATION PIN CONFIGURATION 28-Pin SOJ/ 28-pin SOP 28-Pin TSOP A14 1 28 VDD A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS A0-A14 Address Inputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input I/O0-I/O7 Input/Output Vdd Power GND Ground OE A11 A9 A8 A13 WE VDD A14 A12 A7 A6 A5 A4 A3 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 23 24 25 26 27 28 1 2 3 4 5 6 7 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 TRUTH TABLE Mode WE CE OE I/O Operation Vdd Current Not Selected X H X High-Z Isb1, Isb2 (Power-down) Output Disabled H L H High-Z Icc1, Icc2 Read H L L Dout Icc1, Icc2 Write L L X Din Icc1, Icc2 ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Vterm Terminal Voltage with Respect to GND Tbias Temperature Under Bias Tstg Storage Temperature Pt Power Dissipation Iout DC Output Current (LOW) Value –0.5 to +4.6 –55 to +125 –65 to +150 0.5 20 Unit V °C °C W mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D2 02/07/2020 IS65LV256AL IS62LV256AL OPERATING RANGE Part No. IS62LV256AL IS62LV256AL IS65LV256AL Range Commercial Industrial Automotive Ambient Temperature 0°C to +70°C –40°C to +85°C –40°C to +125°C Vdd 3.3V ± 10% 3.3V ± 10% 3.3V ± 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit Voh Output HIGH Voltage Vdd = Min., Ioh = –2.0 mA 2.4 — V Vol Output LOW Voltage Vdd = Min., Iol = 4.0 mA — 0.4 V Vih Input HIGH Voltage 2.2 Vdd + 0.3 V (1) Vil Input LOW Voltage –0.3 0.8 V Ili Input Leakage GND ≤ Vin ≤ Vdd Com. –1 1 µA Ind. –2 2 Auto. –10 10 Ilo Output Leakage GND ≤ Vout ≤ Vdd, Outputs Disabled Com. –1 1 µA Ind. –2 2 Auto. –10 10 Notes: 1. Vil = –3.0V for pulse width less than 10 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3 Rev. D2 02/07/2020 IS65LV256AL IS62LV256AL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)         -20 ns     -45 ns    Symbol Parameter Test Conditions Min. Max. Min. Max. Unit Icc1 Vdd Operating Vdd = Max., CE = Vil Supply Current Iout = 0 mA, f = 0 Icc2 Vdd Dynamic Operating Vdd = Max., CE = Vil Supply Current Iout = 0 mA, f = fmax Isb1 TTL Standby Current Vdd = Max., (TTL Inputs) Vin = Vih or Vil CE ≥ Vih, f = 0 Isb2 CMOS Standby Vdd = Max., Current (CMOS Inputs) CE ≤ Vdd – 0.2V, Vin > Vdd – 0.2V, or Vin ≤ 0.2V, f = 0 Com. Ind. Auto. Com. Ind. Auto. typ.(2) Com. Ind. Auto. Com. Ind. Auto. typ.(2) — 4 — 5 — — — 20 — 25 — — 15 — 1.5 — 1.8 — — — 15 — 20 — — 2 — 4 mA — 5 — 8 — 10 mA — 12 — 20 7 — 1.5 mA — 1.8 — 2 — 15 µA — 20 — 50 2 Note: 1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at Vdd = 3.3V, Ta = 25oC and not 100% tested. CAPACITANCE(1,2) Symbol Parameter Cin Input Capacitance Cout Output Capacitance Conditions Vin = 0V Vout = 0V Max. Unit 6 pF 5 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D2 02/07/2020 IS65LV256AL IS62LV256AL READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)     -20 ns    -45 ns             Symbol Parameter Min. Max. Min. Max. Unit trc taa toha tace tdoe tlzoe(2) thzoe(2) tlzce(2) thzce(2) tpu(3) tpd(3) Read Cycle Time 20 — 45 — ns Address Access Time — 20 — 45 ns Output Hold Time 2 — 2 — ns CE Access Time — 20 — 45 ns OE Access Time — 10 — 25 ns OE to Low-Z Output 0 — 0 — ns OE to High-Z Output — 9 0 20 ns CE to Low-Z Output 3 — 3 — ns CE to High-Z Output — 9 0 20 ns CE to Power-Up 0 — 0 — ns CE to Power-Down — 18 — 30 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Unit Input Pulse Level 0V to 3.0V Input Rise and Fall Times 3 ns Input and Output Timing 1.5V and Reference Levels Output Load See Figures 1 and 2 AC TEST LOADS 635 Ω 635 Ω 3.3V 3.3V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1. 702 Ω 5 pF Including jig and scope 702 Ω Figure 2. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5 Rev. D2 02/07/2020 IS65LV256AL IS62LV256AL AC WAVEFORMS READ CYCLE NO. 1(1,2) tRC ADDRESS tAA tOHA tOHA DOUT DATA VALID READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tDOE tLZOE CE tACE tLZCE DOUT tHZCE HIGH-Z DATA VALID tPU SUPPLY CURRENT tHZOE tPD 50% ICC 50% ISB Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = Vil. 3. Address is valid prior to or coincident with CE LOW transitions. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D2 02/07/2020 IS65LV256AL IS62LV256AL WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)        -20 ns        -45 ns     Symbol Parameter Min. Max. Min. Max. Unit twc Write Cycle Time 20 — 45 — ns tsce CE to Write End 14 — 35 — ns taw Address Setup Time to Write End 14 — 25 — ns tha Address Hold from Write End 0 — 0 — ns tsa Address Setup Time 0 — 0 — ns tpwe WE Pulse Width 14 — 25 — ns tsd Data Setup to Write End 13 — 20 — (4) thd ns Data Hold from Write End 0 — 0 — ­ns (2) thzwe WE LOW to High-Z Output — 8 — 20 ns tlzwe WE HIGH to Low-Z Output 0 — 0 — ns (2) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) tWC ADDRESS tHA tSCE CE tAW tPWE WE tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7 Rev. D2 02/07/2020 IS65LV256AL IS62LV256AL WRITE CYCLE NO. 2 (CE Controlled)(1,2) tWC ADDRESS tSA tHA tSCE CE tAW tPWE WE tHZWE DOUT DATA UNDEFINED tLZWE HIGH-Z tSD DIN tHD DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE ≥ Vih. 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D2 02/07/2020 IS65LV256AL IS62LV256AL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter Test Condition Min. Typ. Max. Unit Vdr Vdd for Data Retention See Data Retention Waveform 2.0 3.6 V Idr Data Retention Current Vdd = 2.0V, CE ≥ Vdd – 0.2V Com. — — 15 µA Vin ≥ Vdd – 0.2V, or Vin ≤ Vss + 0.2V Ind. — — 20 Auto. — — 50 typ.(1) 2 tsdr Data Retention Setup Time See Data Retention Waveform 0 — ns trdr Recovery Time See Data Retention Waveform trc — ns Note: 1. Typical Values are measured at Vdd = 3.3V, Ta = 25oC and not 100% tested. DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9 Rev. D2 02/07/2020 IS65LV256AL IS62LV256AL ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 20 45 Order Part No. IS62LV256AL-20TL IS62LV256AL-20JL IS62LV256AL-45TL Package TSOP, Lead-free 300-mil Plastic SOJ, Lead-free TSOP, Lead-free Industrial Range: –40°C to +85°C Speed (ns) 20 45 Order Part No. IS62LV256AL-20TLI IS62LV256AL-20JLI IS62LV256AL-45TLI IS62LV256AL-45ULI Package TSOP, Lead-free 300-mil Plastic SOJ, Lead-free TSOP, Lead-free 330-mil Plastic SOP, Lead-free Automotive Range: –40°C to +125°C Speed (ns) 45 10 Order Part No. Package IS65LV256AL-45TLA3 TSOP, Lead-free IS65LV256AL-45ULA3 330-mil Plastic SOP, Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D2 02/07/2020 IS65LV256AL IS62LV256AL Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 11 Rev. D2 02/07/2020 12 0.1 Y Package Outline 3. Dimension b2 does not include dambar protrusion/intrusion. 4. Formed leads shall be planar with respect to one another within 0.1mm at the seating plane after final test. 2. Dimension D1 adn E do not include mold protrusion . 1. Controlling dimension : mm NOTE : 07/05/2006 IS65LV256AL IS62LV256AL Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. D2 02/07/2020 IS65LV256AL IS62LV256AL Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 13 Rev. D2 02/07/2020