PLRXPL-VC-SH4-21-N

COMMUNICATIONS MODULES & SUBSYSTEMS 8.5 G SFP+ 850 nm Limiting Transceiver, 8 Gigabit Fibre Channel Compliant PLRXPL-VC-SH4-21-N and PLRXPL-VC-SH4-22-N Series Key Features • Compliant to industry-wide, 8 G Fibre Channel (FC) link specifications • Maintains FC compliance at 4 and 2 G without need for a rate select option • Uses a highly reliable, 850 nm oxide VCSEL • Lead-free and RoHS 6/6-compliant • 0 – 70°C case operating temperature • Single 3.3 V power supply • Low power consumption (typically 450 mW) • Bit error rate < 1 x 10-12 • Hot pluggable Applications • High-speed storage area networks - Switches and hubs - Network interface cards - Mass storage systems - Host bus adapters • Computer cluster crossconnect systems • Custom high-bandwidth data pipes Compliance • • • • • • • • • SFF 8431 Revision 2.2 FC-PI-4 SFF 8432 Revision 5.0 SFF 8472 Revision 10.3 CDRH and IEC60825-1 Class 1 Laser Eye Safety FCC Class B ESD Class 2 per MIL-STD 883 Method 3015 UL 94, V0 Reliability tested per Telcordia GR-468 The lead-free and RoHS-compliant small form factor pluggable (SFP+) transceiver from JDSU improves the performance for 8 Gigabit Fibre Channel (8 G FC) applications, and is ideal for high-speed, storage area network applications. This transceiver features a highly reliable, 850 nm, oxide, vertical-cavity surfaceemitting laser (VCSEL) coupled to an LC optical connector. The transceiver is fully compliant to the 8 G FC, FC-PI-4, and the SFP+ multisource agreement (MSA) specifications, with internal AC coupling on both transmit and receive data signals. The all-metal housing design provides low EMI emissions in demanding 8 G applications and conforms to IPF specifications. An enhanced digital diagnostic feature set allows for real-time monitoring of transceiver performance and system stability, and the serial ID allows for customer and vendor system information to be stored in the transceiver. Transmit disable, loss-of-signal, and transmitter fault functions are also provided. The small size of the transceiver allows for highdensity system designs that, in turn, enable greater total bandwidth. NORTH AMERICA: 800 498-JDSU (5378) WORLDWIDE: +800 5378-JDSU WEBSITE: www.jdsu.com 8.5 G SFP+ 850 NM LIMITING TRANSCEIVER, 8 GIGABIT FIBRE CHANNEL COMPLIANT 2 Section 1 Functional Description The PLRXPL-VC-SH4-xx-N 8.5 G SFP+ 850 nm optical transceiver is designed to transmit and receive 8B/10B scrambled 8.5 G serial optical data over 50/125 µm or 62.5/125 µm multimode optical fiber. Transmitter The transmitter converts 8B/10B scrambled serial PECL or CML electrical data into serial optical data compliant with the 8 G Fibre Channel standard. Transmit data lines (TD+ and TD-) are internally AC coupled, with 100 Ω differential termination. Transmitter rate select (RS1) pin 9 is assigned to control the SFP+ module transmitter rate. It is connected internally to a 30 kΩ pull-down resistor. A data signal on this pin does not affect the operation of the transmitter. An open collector-compatible transmit disable (Tx_Disable) is provided. This pin is internally terminated with a 10 kΩ resistor to Vcc,T. A logic “1,” or no connection, on this pin will disable the laser from transmitting. A logic “0” on this pin provides normal operation. The transmitter has an internal PIN monitor diode that ensures constant optical power output, independent of supply voltage. It is also used to control the laser output power over temperature to ensure reliability at high temperatures. An open collector-compatible transmit fault (Tx_Fault) is provided. The Tx_ Fault signal must be pulled high on the host board for proper operation. A logic “1” output from this pin indicates that a transmitter fault has occurred or that the part is not fully seated and the transmitter is disabled. A logic “0” on this pin indicates normal operation. Receiver The receiver converts 8B/10B scrambled serial optical data into serial PECL/CML electrical data. Receive data lines (RD+ and RD-) are internally AC coupled with 100 Ω differential source impedance, and must be terminated with a 100 Ω differential load. Receiver Rate Select (RS0) pin 7 is assigned to control the SFP+ module receiver rate. It is connected internally to a 30 kΩ pull-down resistor. A data signal on this pin has no affect on the operation of the receiver. An open collector compatible loss of signal (LOS) is provided. The LOS must be pulled high on the host board for proper operation. A logic “0” indicates that light has been detected at the input to the receiver (see Optical Characteristics, Loss of Signal Assert/Deassert Time). A logic “1” output indicates that insufficient light has been detected for proper operation. 8.5 G SFP+ 850 NM LIMITING TRANSCEIVER, 8 GIGABIT FIBRE CHANNEL COMPLIANT 3 10 kΩ 16 Transmitter Power Supply 3 Transmitter Disable In VCC_TX TX_DIS TD+ 18 Transmitter Positive Data TOSA Laser Driver TX_GND TX_FAULT TD - 100 Ω 19 Transmitter Negative Data 2 Transmitter Fault Out 1, 17, 20 Transmitter Signal Ground SCL Management Processor EEPROM SDA 5 SCL Serial ID Clock 4 SDA Serial ID Data 6 MOD_ABS 15 Receiver Power Supply VCC_RX VCC_RX RD RD + 50 Ω ROSA RX_GND Receiver RX_GND LOS 50 Ω 12 Receiver Negative Data Out 13 Receiver Positive Data Out 8 Loss of Signal Out 9 RS1 TX Rate Select Not Functional on -N modules 7 RS0 RX Rate Select Not Functional on -N modules 10, 11, 14 Receiver Signal Ground 30 kΩ 30 kΩ Figure 1 SFP+ optical transceiver functional block diagram 8.5 G SFP+ 850 NM LIMITING TRANSCEIVER, 8 GIGABIT FIBRE CHANNEL COMPLIANT 4 Section 2 Vcc Z* = 100 Ω 1 VeeT VeeT 20 R2* 50 Ω R1* 50 Ω Application Schematic 10 kΩ Receiver (Tx Fault) CMOS, TTL, or Open Collector Driver (Tx Disable) PECL Driver (TX DATA) � � � � � � � � � � Vcc 2 Tx Fault TD- 19 Open Collector Bidirectional SDA Rp*** 3 Tx Disable TD+ 18 Power Supply Filter Open Collector Bidirectional SCL Mod_ABS CMOS or TTL Driver (RS0 Rx Rate Select) Vcc Receiver (LOS) R6 ∗∗ CMOS or TTL Driver (RS1 Tx Rate Select) Power supply filter component values are provided on page 7. Notes  Power supply filtering components should be placed as close to the Vcc pins of the host connector as possible for optimal performance.  PECL driver and receiver components will require biasing networks. Please consult application notes from suppliers of these components. CML I/O on the PHY are supported. Good impedance matching for the driver and receiver is required. SDA and SCL should be bi-directional open collector connections in order to implement serial ID in JDSU SFP+ transceiver modules. R1/R2 and R3/R4 are normally included in the output and input of the PHY. Please check the application notes for the IC in use. � � � � � � Vcc 4 SDA VeeT 17 C3 � Rx C6 � � L1 Vcc +3.3V Input � � Rq *** Vcc Vcc 5 SCL VccT 16 L2 � C2 6 MOD_ABS VccR 15 C4 7 RS0 VeeR 14 � � C1 10 kΩ R5 ∗∗ C5 Ry 8 LOS RD+ 13 Z* = 100 Ω 9 RS1 10 kΩ Vcc 10 VeeR RD- 12 R3* 50 Ω � � � � � � VeeR 11 R4* 50 Ω � � � � PECL Receiver (RX DATA) Figure 2 Recommended application schematic for the 10 G SFP+ optical transceiver   * Transmission lines should be 100 Ω differential traces. Vias and other transmission line discontinuities should be avoided. In order to meet the host TP1 output jitter and TP4 jitter tolerance requirements it is recommended that the PHY has both transmitter pre-emphasis to equalize the transmitter traces and receiver equalization to equalize the receiver traces. With appropriate transmitter pre-emphasis and receiver equalization, up to 8 dB of loss at 5 GHz can be tolerated. ** R5 and R6 are required when an Open Collector driver is used in place of CMOS or TTL drivers. 5 kΩ value is appropriate. *** The value of Rp and Rq depend on the capacitive loading of these lines and the two wire interface clock frequency. See SFF-8431. A value of 10 kΩ is appropriate for 80 pF capacitive loading at 100 kHz clock frequency. 8.5 G SFP+ 850 NM LIMITING TRANSCEIVER, 8 GIGABIT FIBRE CHANNEL COMPLIANT 5 Power supply filtering is recommended for both the transmitter and receiver. Filtering should be placed on the host assembly as close to the Vcc pins as possible for optimal performance. Vcc,R and Vcc,T should have separate filters. Power supply filter component values from Figure 2 are shown in the table below for two different implementations. Power Supply Filter Component Values Component L1, L2 Rx, Ry C1, C5 C2, C3, C4 C6 Option A 1.0 0.5* 10 0.1 Not required Option B 4.7 0.5* 22 0.1 22 Units µH Ω µF µF µF Notes: Option A is recommended for use in applications with space constraints with power supply noise less than 33 mVp-p. Option B is used in the module compliance board in SFF-8431. *If the total series resistance of L1+C6 and L2+C5 exceeds the values of Rx and Ry in the table, then Rx and Ry can be omitted. 8.5 G SFP+ 850 NM LIMITING TRANSCEIVER, 8 GIGABIT FIBRE CHANNEL COMPLIANT 6 Section 3 Specifications Technical specifications related to the SFP+ optical transceiver include: • Section 3.1 Pin Function Definitions • Section 3.2 Absolute Maximum Ratings • Section 3.3 Operating Conditions • Section 3.4 Electrical Characteristics • Section 3.5 Optical Characteristics • Section 3.6 Link Length • Section 3.7 Regulatory Compliance 2.2 P IN F UNCTION D EFINITIONS • Section 3.8 PCB Layout • Section 3.9 Front Panel Opening • Section 3.10 The transceiver pin descriptions as defined in SFF-8431 are shown inModule OutlineTable 2 on page 8 has a Figure 3 below. • Section 3.11 Transceiver Belly-to-belly Mounting complete description of all the pins. Figure 3 Host PCB SFP+ Pad Assignment Top View 3.1 Pin Function Defi nitions 11 12 13 14 15 TOWARD HOST WITH DIRECTION OF MODULE INSERTION VEER VEER RDRD+ VEER VCCR VCCT VEET TD+ TDVEET RS1 RX_LOS RS0 MOD_ABS SCL SDA TX_DISABLE TX_FAULT VEET 10 9 8 7 6 5 4 3 2 1 TOWARD BEZEL 16 17 18 19 20 November 2007 21114472 R2 Figure 3 Host PCB SFP+ Pad assignment top view PLRXPL-Vx-SH4-21xN JDSU | p. 7 of 20 8.5 G SFP+ 850 NM LIMITING TRANSCEIVER, 8 GIGABIT FIBRE CHANNEL COMPLIANT 7 SFP+ Optical Transceiver Pin Descriptions P in Number Receiver 8 Symbol Name Description LOS Loss of Signal Out (OC) 10, 11, 14 12 VeeR RD- Receiver Signal Ground Receiver Negative DATA Out (PECL) Receiver Positive DATA Out (PECL) Receiver Power Supply 13 RD+ 15 VccR 7 Transmitter 3 RS0 RX Rate Select (LVTTL) Sufficient optical signal for potential BER < 1x10-12 = Logic “0” Insufficient optical signal for potential BER < 1x10-12 = Logic “1” This pin is open collector compatible, and should be pulled up to Host Vcc with a 10 kΩ resistor. These pins should be connected to signal ground on the host board. Light on = Logic “0” Output Receiver DATA output is internally AC coupled and series terminated with a 50 Ω resistor. Light on = Logic “1” Output Receiver DATA output is internally AC coupled and series terminated with a 50 Ω resistor. This pin should be connected to a filtered +3.3 V power supply on the host board. See Application schematics on page 4 for filtering suggestions. This pin has an internal 30 kΩ pull-down to ground. A signal on this pin will not affect module performance. Logic “1” Input (or no connection) = Laser off Logic “0” Input = Laser on This pin is internally pulled up to VccT with a 10 kΩ resistor. These pins should be connected to signal ground on the host board. Logic “1” Output = Laser Fault (Laser off before t_fault) Logic “0” Output = Normal Operation This pin is open collector compatible, and should be pulled up to Host Vcc with a 10 kΩ resistor. This pin should be connected to a filtered +3.3 V power supply on the host board. See Application schematics on page 4 for filtering suggestions. Logic “1” Input = Light on Transmitter DATA inputs are internally AC coupled and terminated with a differential 100 Ω resistor. Logic “0” Input = Light on Transmitter DATA inputs are internally AC coupled and terminated with a differential 100 Ω resistor. This pin has an internal 30 kΩ pulldown to ground. A signal on this pin will not affect module performance. Serial ID with SFF 8472 Diagnostics. Module definition pins should be pulled up to Host Vcc with appropriate resistors for the speed and capacitive loading of the bus. See SFF8431. Serial ID with SFF 8472 Diagnostics. Module definition pins should be pulled up to Host Vcc with appropriate resistors for the speed and capacitive loading of the bus. See SFF8431. Pin should be pulled up to Host Vcc with 10 kΩ resistor. MOD_ABS is asserted “high” when the SFP+ module is physically absent from the host slot. TX_Disable Transmitter Disable In (LVTTL) 1, 17, 20 2 VeeT TX_Fault Transmitter Signal Ground Transmitter Fault Out (OC) 16 VccT Transmitter Power Supply 18 TD+ Transmitter Positive DATA In (PECL) Transmitter Negative DATA In (PECL) TX Rate Select (LVTTL) 19 TD- 9 RS1 Module Definition 4 SDA Two-wire Serial Data 5 SCL Two-wire Serial Clock 6 MOD_ABS Module Absent 8.5 G SFP+ 850 NM LIMITING TRANSCEIVER, 8 GIGABIT FIBRE CHANNEL COMPLIANT 8 3.2 Absolute Maximum Ratings P arameter Storage temperature Case temperature Relative humidity Transmitter differential input voltage Power supply voltage Symbol TST TC RH VD VCC Ratings -40 to +95 -40 to +90 5 – 95 (non-condensing) 2.5 0 to +4.0 Unit ˚C ˚C % V VP-P Note: Absolute maximum ratings represent the damage threshold of the device. Damage may occur if the device is subjected to conditions beyond the limits stated here. 3.3 Operating Conditions Part Number PLRXPL-VC-SH4-xx-N Temperature Rating 0 – 70 Unit ˚C Note: Performance is not guaranteed and reliability is not implied for operation at any condition outside these limits. 8.5 G SFP+ 850 NM LIMITING TRANSCEIVER, 8 GIGABIT FIBRE CHANNEL COMPLIANT 9 3.4 Electrical Characteristics P arameter Supply voltage Power consumption Data rate Transmitter Supply current Common mode voltage tolerance Data input deterministic jitter Data input total jitter Input data dependent pulse width shrinkage Eye mask Symbol Vcc Pdiss Min. 2.97 Typical 3.3 480 8.5 Max. 3.63 1000 9.0 110 Unit V mW Gbps Notes All electrical and optical specifications valid within this range BER < 1x10-12 IccT ∆V DJ TJ DDPWS X1 X2 Y1 Y2 VIH VIL 30 0.17 0.31 0.11 0.155 0.5 90 2.0 -0.3 350 Vcc + 0.3 0.8 10 2 Vcc - 0.4 -0.3 Vcc 0.4 100 10 mA mVrms UI(p-p) JSAT pattern. ∆T, BER < 1x10-12, at 8.5 Gbps (Note 1) UI JSAT pattern. ∆T, at 8.5 Gbps (Note 1) UI (p-p) JSAT pattern. ∆T, at 8.5 Gbps (Note 1) UI UI mV mV V V µs ms V V µs µs Reference FC-PI-4 Revision 7.1, Figure 45 Transmit disable voltage level Transmit disable/enable assert time TTD TTEN Transmit fault output voltage level VOH VOL Transmit fault assert and reset times TFault TReset Initialization time Receiver Supply current Output common mode voltage Data output deterministic jitter Total jitter Data dependent pulse width shrinkage Eye mask TINI ICCR DJ TJ DDPWS X1 Y1 Y2 VOH VOL 300 120 30 0.42 0.71 0.36 0.355 200 Vcc -0.5 -0.3 425 Vcc +0.3 0.4 100 100 ms Laser output disabled after TTD if input level is VIH; Laser output enabled after TTEN if input level is VIL Laser output disabled after TTD if input level is VIH; Laser output enabled after TTEN if input level is VIL Transmit fault level is VOH and Laser output disabled TFault after laser fault. VOL is measured at 0.7 mA. Transmitter fault is VOL and Laser output restored TINI after transmitter disable is asserted for TReset, then disabled. After hot plug or Vcc ≥ 2.97 V Loss of signal voltage level Loss of signal assert/deassert time TLOSA TLOSD mA mVrms RLOAD = 25 Ω, differential UI(p-p) JSAT pattern. ∆R, at 8.5 Gbps (Note 1, 4) UI(p-p) JSAT pattern. ∆R, BER < 1x10-12, at 8.5 Gbps (Note 1, 4) UI (p-p) JSAT pattern. ∆R, at 8.5 Gbps (Note 1, 4) UI Reference FC-PI-4 Revision 7.1, mV Figure 46 mV V LOS output level VOL TLOSD after light input > LOSD (Note 2) V LOS output level VOH TLOSA after light input < LOSA (Note 2) µs LOS output level VOL TLOSD after light input > LOSD (Note 2) µs LOS output level VOH TLOSA after light input < LOSA (Note 2) 8.5 G SFP+ 850 NM LIMITING TRANSCEIVER, 8 GIGABIT FIBRE CHANNEL COMPLIANT 10 3.5 Optical Characteristics P arameter Transmitter Wavelength RMS spectral width Transmitter waveform dispersion penalty Average optical power Optical modulation amplitude Relative intensity noise Receiver Wavelength Maximum input power Sensitivity (OMA) Stressed sensitivity (OMA) Loss of signal assert/deassert level Low frequency cutoff Symbol λp TWDP PAVG OMA RIN12OMA λ Pmax S VECP = 3.1 dB LOSD LOSA FC Min. Typical Max. Unit Notes 840 850 860 0.45 4.2 Note 6 -128 nm nm dB dBm µW dB/Hz nm dBm µWP-P µWP-P dBm dBm MHz (Note 3) -8.2 302 12 dB reflection 840 0 850 860 76 151 -14 -30 0.3 (Note 7) (Note 4) Chatter-free operation; LOSD is OMA, LOSA is average power -3 dB, P