DC1366B

DEMO MANUAL DC1366B LTC4266 IEEE 802.3at PoE Quad PSE Controller DESCRIPTION Demonstration circuit DC1366B features the LTC®4266, a quad network power controller with I2C® interface, designed for use in IEEE 802.3at compliant Power Sourcing Equipment (PSE). Integrated into a tiny 5mm × 7mm 38-pin QFN package are four independent channels controlling external N-channel power MOSFETs. Each port features: Reliable 4-Point PD Detection n Selectable 1 or 2-Event Classification n Inrush Current Limiting n Extremely Fast Short-Circuit Protection with Programmable Foldback Current Threshold n Programmable Cutoff Current Threshold for Class Power Enforcement n Voltage and Current Readback n DC Disconnect Sensing n The DC1366B is configured like a midspan PSE with two RJ45 connectors for each port such that gigabit Ethernet data can pass through the board at full line rates while DC power is injected by the LTC4266 on the OUT TO PD side of the board. Often one of the most challenging aspects of designing a PSE system is the power management software; Analog Devices makes the job easier with the fully-featured LTC4266 register set and a QuikEval™ GUI software application. The GUI allows the user full and easy access to the LTC4266 register set with detailed contextual help info. LTC4266 example software is available only under a nondisclosure agreement (NDA). The DC1366B has increased surge protection and more compact Hot Swap MOSFETs over the DC1366A. The DC1366B is Ethernet Alliance™ certified. Design files for this circuit board are available. All registered trademarks and trademarks are the property of their respective owners. DC1366B Rev B 1 DEMO MANUAL DC1366B QUICK START PROCEDURE Figure 1 shows the basic setup. The LTC4266 requires two power supply rails: VDD (nominally 3.3V) and VEE (nominally –54V). The VDD supply can be provided by a DC590 board or an external bench supply. When running QuikEval on a Windows computer, the DC590 is used to interface a USB port on the PC to the I2C bus on the DC1366B. The DC590 also provides optoisolation of the I2C bus, and an isolated 3.3V supply to run the LTC4266; the user need only provide the VEE supply. Alternatively, the user can omit the DC590 and connect an I2C master device to the DC1366B. If the DC590 is omitted then a bench power supply must provide VDD. I2C control is not required, the For applications where LTC4266 features an AUTO mode allowing it to operate completely autonomously. Choose one of the setup procedures shown on the next page, depending on whether or not the QuikEval GUI application software is required. Setup Procedure to Run the QuikEval GUI Software 1. Install the GUI software on the PC according to the instructions in the README.txt file included with the GUI software. 2. On the DC590: a. Set both sides (ISO and SW) of JP5 to ON. b. Set JP6 to 3.3V. 3. Connect the DC590 to the PC with a standard USB A-B cable. a. Verify the computer recognized the USB device. (The first time the DC590 is connected the Hardware Wizard may ask for help to locate the driver. Direct it to the location specified in the README.txt that came with the GUI software.) b. Verify the ISO PWR LED on the DC590 is lit. 4. On the DC1366B board: a. Set JP5 to the USB VDD position. b. Set JP3 to the TIE position. c. Set JP4 (AUTO) to the HI position. d. If midspan operation is desired set JP2 to HI, for endpoint set to LO. 5. Connect the DC590 to the DC1366B with the 14-conductor ribbon cable supplied with the DC1366B. Verify the VDD LED on the DC1366B is lit. 6. Before connecting the main power supply to the DC1366B verify the voltage is between 51V and 57V, and that the main supply is turned off. 7. Connect the main power supply to the DC1366B with two banana patch cords as shown in Figure 1. Verify the polarity is correct before turning on the power; positive goes to RTN and negative to VEE. 8. Turn on the main power supply and verify the VEE LED on the DC1366B is lit. 9. Connect PDs to any of the ports on the OUT to PD side of the DC1366B and verify they turn on by the respective OUTn LED. 10. Launch QuikEval. Rev B 2 DEMO MANUAL DC1366B QUICK START PROCEDURE Setup Procedure without the DC590 1. On the DC1366B: a. Set JP5 to EXT VDD. b. Set JP4 (AUTO) to the HI position. c. If midspan operation is desired set JP2 to HI, for endpoint set to LO. 2. Connect a 3.3V power supply across +3.3V and DGND test points as shown in Figure 1. Turn on the 3.3V supply and verify the VDD LED on the DC1366B is lit. 4. Connect the main power supply to the DC1366B with two banana patch cords as shown in Figure 1. Verify the polarity is correct before turning on the power; positive goes to RTN and negative to VEE. 5. Turn on the main power supply and verify the VEE LED on the DC1366B is lit. 6. Connect PDs to any of the ports on the OUT TO PD side of the DC1366B and verify they turn on by the respective OUTn LED. 3. Before connecting the main power supply to the DC1366B verify the voltage is between 51V and 57V, and that the main supply is turned off. Rev B 3 DEMO MANUAL DC1366B QUICK START PROCEDURE Optional Equipment for Computer Control DC590 USB to I2C Interface USB CABLE Windows Computer 14-Pin Ribbon Cable CAT5 Cables Isolated VEE Supply (51V to 57V) –+ +– RJ45 RJ45 PD1 RJ45 RJ45 PD2 RJ45 RJ45 PD3 RJ45 RJ45 PD4 Optional VDD Supply (3.3V Nominal) Figure 1. DC1366B Setup Rev B 4 DEMO MANUAL DC1366B OPERATION Introduction Modes of Operation The DC1366B demonstrates the features and capabilities of the LTC4266, a quad controller for IEEE802.3at Power Sourcing Equipment (PSE). The DC1366B provides a quick and simple, fully compliant PSE solution requiring only a VEE supply when used in conjunction with the DC590 USB-to-I2C interface board. The LTC4266 has four modes of operation: Supply Voltages The IEEE802.3at standard requires the port output voltage of a type 2 PSE to be in the range of 50V to 57V. The positive side is RTN and the negative side is VEE. The VEE supply voltage should be in this range for the sake of compliance; however, the LTC4266 is capable of operating with VEE down to 30V, the max undervoltage lockout (UVLO) threshold. Make sure to choose a VEE supply with enough power to sustain all four ports at maximum load; if the total load is too great for the power supply its voltage may drop below the UVLO threshold, resetting the LTC4266 and shutting off all the ports. The worst case is when all four PDs are class 4: each class 4 PD may draw up to 600mA, totaling 2.4A. Therefore a VEE supply rated for at least 2.6A is recommended. The VDD supply should nominally be 3.3V but the LTC4266 is capable of operating over the range of 3.0V to 4.3V. (The UVLO threshold for the VDD supply is typically 2.2V.) The LTC4266 chip typically draws only 1.1mA from the VDD supply; however, LEDs and other components on the DC1366B board also draw current from VDD, so the total load is typically 9mA to 26mA at 3.3V depending on which LEDs are lit. VDD to DGND Configurations The DC1366B, LTC4266 VDD supply can be configured in one of two ways. The default DC1366B configuration ties the LTC4266 VDD pin to the AGND pin through a 0 Ohm resistor R10. The DGND pin is at –3.3V below the AGND pin. The DC1366B can also be configured for a +3.3V at VDD relative to AGND by removing R10 and installing a 0Ω resistor at R9. This ties the LTC4266 DGND pin and AGND pin. Shutdown: Ports are shutdown, detection and classification cycles are disabled. n Manual: The port does not advance automatically from detection to classification, to power on. It waits for instructions from a host controller via the I2C interface. n Semiauto: The port automatically advances to classification after detecting a PD, but does not turn on power to the PD until told to do so by from a host controller via the I2C interface. n AUTO Pin High: The LTC4266 operates autonomously. n AUTO Pin The AUTO pin determines several aspects of the LTC4266 initial behavior. AUTO is sensed by the LTC4266 at power up and after a reset. If the AUTO pin is high then: All ports come up in AUTO pin high mode. Any valid PD will be turned on without software intervention. n The current-sense resistors are assumed to be 0.25Ω (which they are on the DC1366B). n High power is enabled. After the LTC4266 classifies a PD it applies power and automatically sets ICUT and ILIM appropriately for the class. With high-power enabled a class 4 PD will be able to draw up to 600mA without being cut off. n If the AUTO pin is low then: All ports come up in shutdown mode. A host controller must take action in order to power up any PDs. n The current-sense resistors are assumed to be 0.50Ω; a host controller must change this to 0.25Ω for correct operation of the DC1366B. n High power is disabled and is enabled by a host controller. n Rev B 5 DEMO MANUAL DC1366B OPERATION Endpoint vs. Midspan The LTC4266 can be configured either for endpoint or midspan operation without software intervention by setting the MID pin high or low respectively. (You must reset the LTC4266 or cycle the power for the MID pin to be sensed.) The only difference in the behavior of the LTC4266 is that the detection back-off timer is enabled when midspan operation is selected. Each port can be configured individually as either endspan or midspan via I2C commands. The DC1366B is wired for Alternative-A, MDI-X (power is injected on the data pairs of the CAT5/6e cable; positive on pins 3 and 6 of the RJ45 connector, and negative on pins 1 and 2). The original 802.3af standard required all midspans to use Alternative-B, but 802.3at allows midspans to use Alternative-A. Disconnect Sensing The LTC4266 employs DC disconnect sensing only. For the sake of software backward compatibility with the older LTC4259, the LTC4266 includes register bits for enabling AC disconnect sensing, but these bits simply enable the DC disconnect sensing. Pushbutton Switches The DC1366B includes several pushbutton switches to facilitate experimentation with the LTC4266. The RESET button (SW6) resets all ports just as if the power supplies were cycled. n The Masked Shutdown (MSD) button (SW7) will turn off any ports that have their corresponding mask bit set in the MSD register. n Each port has an individual shut down switch (SW2 through SW5 for ports 1 through 4 respectively). n Masked Shutdown The MSD register can be used to pre-assign low-priority to selected ports so they can be shut down quickly when needed. A PSE system design can utilize the MSD feature in various ways. For example, a PSE system may include a circuit that monitors the VEE supply; if it becomes overloaded and the voltage begins to sag, the system can dump lowpriority ports by asserting the MSD pin. Shedding excess load quickly may allow the VEE voltage to recover before it reaches the UVLO threshold, thus avoiding shutting down higher-priority ports. I2C Addressing The 7-bit I2C address of the LTC4266 is 010A3A2A1A0b, where A3 through A0 are determined by pins AD3 through AD0 respectively. On the DC1366B these pins are controlled by the quad DIP switch, SW1. The LTC4266 has internal pull-up resistors on these pins, so with all four switches of SW1 open the address will be 0101111b. All LTC4266 chips also respond to the global address 0110000b regardless of the state of their AD3-AD0 pins. I2C Bus Lines The LTC4266 has separate pins for SDAIN and SDAOUT to facilitate the use of opto-couplers. The DC1366B provides test points for both SDAIN and SDAOUT to make it easy to connect to any type of breadboard or development tools. The DC1366B ties SDAIN and SDAOUT with shunt R11. The DC590 includes pull-up resistors on the SDA and SCL lines, while the DC1366B board has none. If the DC590 board is replaced by a different I2C master, the user must make sure there are appropriate pull-up resistors on SDA and SCL. Interrupts The LTC4266 includes an open-drain interrupt line for signaling the host controller when it needs service. This signal can be accessed on the DC1366B at the INT test point. An LED is also included to indicate an interrupt. Connecting Multiple DC1366B Boards To use multiple DC1366B on a common I2C bus, simply connect their J6 connectors together with ribbon cable (14-conductor, 1mm pitch). Rev B 6 DEMO MANUAL DC1366B OPERATION Up to sixteen DC1366B can be controlled by a single I2C master. Remember to set each board to a different I2C address using the DIP switch. The DC590 cannot supply enough current on VDD for more than five or six DC1366B boards; an external VDD power supply is recommended if more than five DC1366B boards are connected together. If a large number of DC1366B boards are connected to a single VEE supply, be aware that banana patch cords are only rated for approximately 14A. To avoid exceeding the ampacity of the patch cords, the boards should be connected in a star configuration rather than connecting the boards in a chain. QuikEval GUI Software The QuikEval GUI application software is a powerful tool for learning the LTC4266 registers. Also available is the LTC4266NDASI software interface data sheet that provides further details on these registers. Surge Protection Ethernet ports can be subject to significant cable surge events. To keep PoE voltages below a safe level and protect the application against damage, protection components are required at the main supply, at the LTC4266 supply pins and at each port. Bulk transient voltage suppression devices and bulk capacitance are required across the main PoE supply and should be sized to accommodate system level surge requirements. The DC1366B diode D18 and capacitor C2 are example components for this protection at the main PoE supply. Each LTC4266 requires a 10Ω, 0805 resistor (R35) in series from supply AGND to the LTC4266 AGND pin. Across the LTC4266 AGND pin and VEE pin are an SMAJ58A, 58V TVS (D1) and a 1μF, 100V bypass capacitor (C64). These components must be placed close to the LTC4266 pins. Each port requires a pair of S1B clamp diodes: one from OUTn to supply AGND and one from OUTn to supply VEE. The diodes at the ports steer harmful surges into the supply rails where they are absorbed by the surge suppressors and the VEE bypass capacitance. The layout of these paths must be low impedance. Finally, the VDD logic supply and logic pins may also require additional surge protection. Components D23, C16, R36, D2, and C65 demonstrate surge protection for VDD to DGND. For a positive VDD configuration where VDD is +3.3V above AGND and DGND is tied to AGND, the DC1366B has place holders at D28 and C66 for a 64V TVS and high voltage capacitance from VDD to VEE. Rev B 7 DEMO MANUAL DC1366B PCB LAYOUT Top Assembly Rev B 8 DEMO MANUAL DC1366B PCB LAYOUT Layer 1 Rev B 9 DEMO MANUAL DC1366B PCB LAYOUT Layer 2 Rev B 10 DEMO MANUAL DC1366B PCB LAYOUT Layer 3 Rev B 11 DEMO MANUAL DC1366B PCB LAYOUT Layer 4 Rev B 12 DEMO MANUAL DC1366B PCB LAYOUT IDA Bottom Assembly Rev B 13 A B C TP16 VEE VEE -54V RTN RTN TP18 J1 TP5 J2 TP20 DGND TP17 DGND +3.3V JP5 VEE D23 SMAJ5.0A +3.3V EXT VDD 1 2 5 16V C16 + 10uF 3 1 RPW1 300 D7 VDD ORANGE D28 SMBJ64A OPT RPW2 3.9K 1/4W D19 39V D5 VEE ORANGE 2 1 VEE 2 D SDAOUT SDAIN SCL A0 A1 C66 4.7uF 100V 1206 OPT 0805 VDD C2 10uF 100V 0805 R35 10 4 1 2 3 4 VDD R10 0 HI AGND_PIN ADDRESS SW1 TP9 LO 8 7 6 5 D18 SMCJ58A TP8 RECOMMENDED MINIMUM CABLE SURGE PROTECTION + R11 0 TP7 SDAIN SDAOUT INT TP6 SCL R9 0 OPT A0 A1 A2 A3 INT SDAOUT SDAIN SCL 7 6 AD0 5 AD1 4 AD2 AD3 10 DGND 1 3 38 INT RED D6 RL1 300 VDD 1 2 R36 10 SMAJ58A 1 RS1A RS1B RS1C RS1D 1uF 100V 1206 2 Q1 G1 SW5 SD4 SW4 SD3 5 6 7 8 RS2A RS2B RS2C RS2D 3 VDD Q2 G2 C65 0.1uF 2 D2 SMAJ5.0A 1 5 6 7 8 RS3A RS3B RS3C RS3D MID Q3 G3 U1 LTC4266 RESET TP31 5 6 7 8 RS4A RS4B RS4C RS4D MSD TP19 VDD VDD Q4 G4 5 6 7 8 HI LO JP2 SW6 MSD SW7 D8 S1B LO HI MIDSPAN JP4 AUTO RESET 3 2 1 3 2 1 C22 0.22uF X7R D24 S1B VEE 2 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. VEE D25 S1B D9 S1B SD4 SD3 SD2 SD1 AUTO SCALE = NONE DILIAN R. KIM T. APPROVALS LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED APP ENG. CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. CUSTOMER NOTICE PSMN075-100MSE 1.00 1.00 1 1.00 2 1.00 3 PSMN075-100MSE 1.00 1.00 1 1.00 2 1.00 3 PSMN075-100MSE 1.00 1.00 1 1.00 2 1.00 3 PSMN075-100MSE 1.00 1.00 1 1.00 2 1.00 3 C64 D1 SD1 SW3 SD2 SW2 SD4 2 13 +3.3V SOURCE 1 1 2 3 1 37 AGND 18 SD1 VEE 26 INT SD2 VEE 39 RESET USB VDD 1 2 VEE 25 SD3 14 SD1 15 SD2 16 SD3 17 SD4 SENSE 1 30 SENSE1 OUT 1 32 GATE 1 31 4 GATE1 OUT 2 29 VDD SENSE 2 27 SENSE2 GATE 2 28 GATE2 4 AUTO 33 AUTO 22 GATE 3 23 SENSE3 4 GATE3 SENSE 3 36 MID OUT 3 24 35 19 MSD 34 MSD OUT 4 21 RESET SENSE 4 SENSE4 GATE 4 20 GATE4 4 1 2 USBVDD 1 2 1 2 2 1 2 VEE D26 S1B D10 S1B 2 REV DATE: N/A SIZE 1 C47 0.22uF X7R TP4 OUT4 TP3 OUT3 TP2 OUT2 TP1 DATE OUT4 OUT3 OUT2 OUT1 08-10-15 IC NO. LTC4266CUHF DEMO CIRCUIT 1366B 1 Monday, August 10, 2015 SHEET 1 OF 3 REV. 2 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only VEE C58 0.22uF X7R OUT1 D27 S1B D11 S1B DILIAN R. APPROVED TP10 RTN REBUILD WITH CHANGE DESCRIPTION REVISION HISTORY IEEE802.3AT PoE QUAD PSE CONTROLLER TITLE: SCHEMATIC C36 0.22uF X7R ECO 1 2 3 1 2 1 2 4 1 14 2 5 A B C D DEMO MANUAL DC1366B SCHEMATIC DIAGRAM Rev B A B C D 5 IN FROM PHY CHASSIS GND D C B A 8 8 TP15 1 2 3 6 4 5 7 J4D 1 2 3 6 4 5 7 J4C 1 2 3 6 4 5 7 8 J4B 1 2 3 6 4 5 7 8 J4A RJ45 - 4 PORTS RJ45 - 4 PORTS RJ45 - 4 PORTS RJ45 - 4 PORTS J4 SHIELD J5 SHIELD 4 4 2kV R4N2 75 R4P2 75 R3N2 75 C49 1000pF R3P2 75 2kV R2N2 75 2kV C40 1000pF R2P2 75 R1N2 75 2kV C34 1000pF R1P2 75 C19 1000pF 1 2 5 6 1 2 5 6 1 2 5 6 1 2 5 6 4 4 3 4 4 75 R4N1 R4P1 L8 BEAD L7 BEAD ETH1-230LD L6 BEAD 75 75 75 75 R2N1 R3N1 75 R2P1 14 13 10 9 14 13 10 9 14 13 3 C60 0.01uF 200V C56 0.01uF 200V T4 C52 0.01uF 200V C45 0.01uF 200V T3 C38 0.01uF 200V C31 0.01uF 200V T2 C27 0.01uF 200V 10 C20 0.01uF 200V T1 R1P1 75 9 14 13 10 9 3 R1N1 75 R3P1 L5 BEAD ETH1-230LD L4 BEAD L3 BEAD ETH1-230LD L2 BEAD L1 BEAD ETH1-230LD 12 12 12 12 3 3 3 11 11 11 11 C53 1000pF 2kV C42 1000pF 2kV C28 1000pF 2kV C17 1000pF 2kV OUT4 OUT3 OUT2 OUT1 8 1 2 3 6 4 5 7 8 J5D 1 2 3 6 4 5 7 J5C 1 2 3 6 4 5 7 8 J5B 1 2 3 6 4 5 7 8 J5A RJ45 - 4 PORTS RJ45 - 4 PORTS RJ45 - 4 PORTS RJ45 - 4 PORTS 5 CUSTOMER NOTICE OUT TO PD 2 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. SCALE = NONE DILIAN R. KIM T. APPROVALS LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED APP ENG. CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. PORT 4 PORT 3 PORT 2 PORT 1 2 DATE: N/A SIZE IC NO. LTC4266CUHF DEMO CIRCUIT 1366B 1 Monday, August 10, 2015 SHEET 2 OF 3 RE V . 2 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only IEEE802.3AT PoE QUAD PSE CONTROLLER TITLE: SCHEMATIC 1 A B C D DEMO MANUAL DC1366B SCHEMATIC DIAGRAM Rev B 15 16 A B C D 5 5 A0 A1 SD1 SD2 SD3 SD4 AUTO VDDP VDDP VDDP VDDP 2 2 2 1 Q9 Si2343DS 1 Q10 Si2343DS 1 Q11 Si2343DS 1 Q12 Si2343DS 3 3 3 3 R7 18M R8 300 R17 18M R18 300 R20 18M R21 300 R23 18M R24 300 1 1 1 1 GREEN D12 OUT1 GREEN D13 OUT2 GREEN D14 OUT3 GREEN D15 OUT4 OPT OPT OPT OPT OPT RX2 RX3 RX4 RX5 RX6 1 3 5 7 9 11 13 15 4 DEMO PURPOSES ONLY OPT RX1 VDD OPTIONAL LED DRIVE 1% R6 1.1M 1% R16 1.1M 1% R19 1.1M 1% R22 1.1M 2 4 J7 2 2 2 2 2 4 6 8 10 12 14 16 OPT OUT1 OUT2 OUT3 OUT4 3 3 REP1 5.1K SDAOUT REP3 5.1K 5 6 7 8 U3 A1 A2 VSS SCL SDA TP29 A0 WP 24LC025 VCC 2 1 4 3 2 THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS. CUSTOMER NOTICE SDAIN SCL USBVDD SCALE = NONE DILIAN R. KIM T. APPROVALS LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER-SUPPLIED SPECIFICATIONS; HOWEVER, IT REMAINS THE CUSTOMER'S RESPONSIBILITY TO PCB DES. VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION. COMPONENT SUBSTITUTION AND PRINTED APP ENG. CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY. CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE. QUICKEVAL FOR DEMO ONLY REP2 5.1K C4 0.1uF 14 12 13 10 8 9 6 11 4 7 2 5 J6 3 1 2 DATE: N/A SIZE IC NO. 1 Monday, August 10, 2015 DEMO CIRCUIT 1366B LTC4266CUHF SHEET 3 OF 2 3 REV. IEEE802.3AT PoE QUAD PSE CONTROLLER TITLE: SCHEMATIC 1630 McCarthy Blvd. Milpitas, CA 95035 Phone: (408)432-1900 www.linear.com Fax: (408)434-0507 LTC Confidential-For Customer Use Only 1 A B C D DEMO MANUAL DC1366B SCHEMATIC DIAGRAM Rev B DEMO MANUAL DC1366B REVISION HISTORY REV DATE DESCRIPTION A 12/15 Replaced Q1-Q4 with NXP PSMN075-100MSE, LFPAK33 package. PAGE NUMBER Replaced SDAIN/SDAOUT jumper, JP3, tie option with resistor shunt R11. Changed diode D18 to SMCJ58A, 58V TVS. Removed 3.3V LDO, U2. Added AGND pin surge protection 10Ω resistor R35, moved logic pull-ups to VDD pin. Added VDD pin surge protection 10Ω resistor R36. Added SMAJ5.0A, 5V TVS, D2, across LTC4266 VDD and DGND pins. Changed diode D23 to SMAJ5.0A, 5V TVS. Renamed board logic ground to DGND, moved logic ground connections to DGND. Renamed VEE high side supply connection to RTN. Added R10, VDD pin shunt to AGND pin, and R9, DGND pin shunt option to AGND pin. Moved LED pull-up to +3.3V. B 11/18 Ethernet Alliance certification logo added. 1 Rev B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 17 DEMO MANUAL DC1366B ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. 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