LTC1142/LTC1142L/LTC1142HV
Dual High Efficiency
Synchronous Step-Down
Switching Regulators
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DESCRIPTIO
FEATURES
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The LTC®1142/LTC1142L/LTC1142HV are dual synchronous step-down switching regulator controllers featuring
automatic Burst ModeTM operation to maintain high efficiencies at low output currents. The devices are composed of two
separate regulator blocks, each driving a pair of external
complementary power MOSFETs, at switching frequencies
up to 250kHz, using a constant off-time current mode architecture providing constant ripple current in the inductor.
Dual Outputs: 3.3V and 5V or User Programmable
Ultrahigh Efficiency: Over 95% Possible
Current Mode Operation for Excellent Line and Load
Transient Response
High Efficiency Maintained over 3 Decades of
Output Current
Low Standby Current at Light Loads: 160µA/Output
Independent Micropower Shutdown: IQ < 40µA
Wide VIN Range: 3.5V to 20V
Very Low Dropout Operation: 100% Duty Cycle
Synchronous FET Switching for High Efficiency
Available in Standard 28-Pin SSOP
The operating current level for both regulators is user programmable via an external current sense resistor. Wide input
supply range allows operation from 3.5V* to 18V (20V
maximum). Constant off-time architecture provides low dropout regulation limited only by the RDS(ON) of the external
MOSFET and resistance of the inductor and current sense
resistor.
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APPLICATIO S
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Notebook and Palmtop Computers
Battery-Operated Digital Devices
Portable Instruments
DC Power Distribution Systems
The LTC1142 series is ideal for applications requiring dual
output voltages with high conversion efficiencies over a wide
load current range in a small amount of board space.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a trademark of Linear Technology Corporation.
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TYPICAL APPLICATIO
VIN
5.2V TO 18V
+
VOUT3
3.3V/2A
CIN3
22µF
25V
×2
+
0.22µF
P-CH
Si9430DY
23
L1
50µH
RSENSE3
0.05Ω
1
2
24
VIN3
28
+
COUT3
220µF
10V
×2
6
N-CH
Si9410DY
16
SHDN3
10
SENSE + 5
LTC1142HV
SENSE – 5
NDRIVE 3
NDRIVE 5
PGND3 SGND3 CT3
RSENSE3, RSENSE5 : DALE WSL-2010-.05
L1, L2: COILTRONICS CTX50-2-MP
PINS 5, 7, 8, 19, 21, 22: NC
3
25
ITH3
27
RC3
1k
ITH5
13
RC5
1k
L2
50µH
RSENSE5
0.05Ω
VOUT5
5V/2A
15
1000pF
SENSE – 3
4
9
PDRIVE 5
SENSE + 3
CIN5
22µF
25V
×2
P-CH
Si9430DY
VIN5
SHDN5
PDRIVE 3
1000pF
D1
MBRS130L
0.22µF
0V = NORMAL
>1.5V = SHDN
CT5
14
SGND5 PGND5
11
17
18
D2
MBRS130L
20
N-CH
Si9410DY
+
COUT5
220µF
10V
×2
CT3
CT5
CC3
CC5
560pF 3300pF 3300pF 390pF
NOTE: COMPONENTS OPTIMIZED FOR HIGHEST EFFICIENCY, NOT MINIMUM BOARD SPACE.
1142 F01
Figure 1. High Efficiency Dual 3.3V, 5V Supply
1
LTC1142/LTC1142L/LTC1142HV
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ABSOLUTE
AXI U RATI GS
(Note 1)
Input Supply Voltage (Pins 10, 24)
LTC1142, LTC1142L-ADJ ..................... 16V to – 0.3V
LTC1142HV, LTC1142HV-ADJ ............. 20V to – 0.3V
Continuous Output Current (Pins 6, 9, 20, 23) .... 50mA
Sense Voltages (Pins 1, 14, 15, 28)
VIN > 13V .............................................. 13V to – 0.3V
VIN < 13V .................................. (VIN + 0.3V) to – 0.3V
Operating Ambient Temperature Range ...... 0°C to 70°C
Extended Commercial
Temperature Range ........................... – 40°C to 85°C
Junction Temperature (Note 2) ............................ 125°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
1
28 SENSE – 1
VFB1
2
27 ITH1
SHDN1
3
26 INTVCC1
SGND1
4
25 CT1
PGND1
5
24 VIN1
NDRIVE 1
6
23 PDRIVE 1
22 NC
NC
7
22 NC
21 NC
NC
8
21 NC
PDRIVE 2
9
20 NDRIVE 2
1
28 SENSE – 3
SHDN3
2
27 ITH3
SGND3
3
26 INTVCC3
PGND3
4
25 CT3
NC
5
24 VIN3
NDRIVE 3
6
23 PDRIVE 3
NC
7
NC
8
PDRIVE 5
9
20 NDRIVE 5
VIN5 10
ORDER PART
NUMBER
SENSE + 1
SENSE +3
LTC1142CG
LTC1142HVCG
19 NC
VIN2 10
19 PGND2
CT5 11
18 PGND5
CT2 11
18 SGND2
INTVCC5 12
17 SGND5
INTVCC2 12
17 SHDN2
ITH5 13
16 SHDN5
ITH2 13
SENSE – 5 14
15 SENSE + 5
SENSE – 2 14
ORDER PART
NUMBER
LTC1142HVCG-ADJ
LTC1142LCG-ADJ
16 VFB2
15 SENSE + 2
G PACKAGE
28-LEAD PLASTIC SSOP
G PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/W
TJMAX = 125°C, θJA = 95°C/W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V10 = V24 = 10V, VSHDN = 0V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
V2, V16
Feedback Voltage
LTC1142HV-ADJ, LTC1142L-ADJ : V10, V24 = 9V
●
I2, I16
Feedback Current
LTC1142HV-ADJ, LTC1142L-ADJ
●
VOUT
Regulated Output Voltage
3.3V Output
5V Output
LTC1142, LTC1142HV
ILOAD = 700mA, V24 = 9V
ILOAD = 700mA, V10 = 9V
●
●
∆VOUT
I10, I24
2
MIN
TYP
MAX
UNITS
1.21
1.25
1.29
V
0.2
1
µA
3.23
4.90
3.33
5.05
3.43
5.20
V
V
– 40
0
40
mV
40
60
65
100
mV
mV
Output Voltage Line Regulation
V10, V24 = 7V to 12V, ILOAD = 50mA
Output Voltage Load Regulation
3.3V Output
5V Output
Figure 1 Circuit
5mA < ILOAD < 2A
5mA < ILOAD < 2A
Output Ripple (Burst Mode)
ILOAD = 0A
50
Input DC Supply Current (Note 3)
Normal Mode
Sleep Mode
Shutdown
LTC1142
4V < V10, V24 < 12V
4V < V24 < 12V, 6V < V10 < 12V
VSD1 = VSD2 = 2.1V, 4V < V10, V24 < 12V
1.6
160
10
●
●
mVP-P
2.1
230
20
mA
µA
µA
LTC1142/LTC1142L/LTC1142HV
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V10 = V24 = 10V, VSHDN = 0V unless otherwise noted.
SYMBOL
V1 – V28
V15 – V14
PARAMETER
CONDITIONS
MIN
Input DC Supply Current (Note 3)
Normal Mode
Sleep Mode
Shutdown
LTC1142HV, LTC1142HV-ADJ
4V < V10, V24 < 18V
4V < V24 < 18V, 6V < V10 < 18V
VSD1 = VSD2 = 2.1V, 4V < V10, V24 < 18V
Input DC Supply Current (Note 3)
Normal Mode
Sleep Mode
Shutdown
LTC1142L-ADJ (Note 6)
3.5V < V10, V24 < 12V
3.5V < V10, V24 < 12V
VSD1 = VSD2 = 2.1V, 3.5V < V10, V24 < 12V
Current Sense Threshold Voltage
LTC1142HV-ADJ, LTC1142L-ADJ
V14 = V28 = VOUT + 100mV, V2 = V16 = VREF + 25mV
V14 = V28 = VOUT – 100mV, V2 = V16 = VREF – 25mV
●
LTC1142, LTC1142HV
V28 = VOUT + 100mV (Forced)
V28 = VOUT – 100mV (Forced)
LTC1142, LTC1142HV
V14 = VOUT + 100mV (Forced)
V14 = VOUT – 100mV (Forced)
TYP
1.6
160
10
MAX
2.3
250
22
UNITS
mA
µA
µA
1.6
160
10
2.1
230
20
mA
µA
µA
130
25
150
170
mV
mV
●
130
25
150
170
mV
mV
●
130
25
150
170
mV
mV
0.5
0.8
2
V
1.2
5
µA
VSHDN
Shutdown Pin Threshold
ISHDN
Shutdown Pin Input Current
0V < VSHDN < 8V, V10, V24 = 16V
I11, I24
CT Pin Discharge Current
VOUT in Regulation, VSENSE – = VOUT
VOUT = 0V
50
70
2
90
10
µA
µA
tOFF
Off-Time (Note 4)
CT = 390pF, ILOAD = 700mA
4
5
6
µs
tr, t f
Driver Output Transition Times
CL = 3000pF (Pins 6, 9, 20, 23), V10, V24 = 6V
100
200
ns
– 40°C ≤ TA ≤ 85°C (Note 5), V10 = V24 = 10V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V2, V16
Feedback Voltage
LTC1142HV-ADJ Only: V10, V24 = 9V
1.21
1.25
1.29
V
I2, I16
Feedback Current
LTC1142HV-ADJ Only
0.2
1
µA
VOUT
Regulated Output Voltage
3.3V Output
5V Output
LTC1142, LTC1142HV
ILOAD = 700mA, V24 = 9V
ILOAD = 700mA, V10 = 9V
3.33
5.05
3.43
5.20
V
V
Input DC Supply Current (Note 3)
Normal Mode
Sleep Mode
Shutdown
LTC1142
4V < V10, V24 < 12V
4V < V24 < 12V, 6V < V10 < 12V
VSHDN = 2.1V, 4V < V10, V24 < 12V
1.6
160
10
2.4
260
22
mA
µA
µA
Input DC Supply Current (Note 3)
Normal Mode
Sleep Mode
Shutdown
LTC1142HV-ADJ, LTC1142HV
4V < V10, V24 < 18V
4V < V24 < 18V, 6V < V10 < 18V
VSHDN = 2.1V, 4V < V10, V24 < 12V
1.6
160
10
2.6
280
24
mA
µA
µA
Input DC Supply Current (Note 3)
Normal Mode
Sleep Mode
Shutdown
LTC1142L-ADJ (Note 6)
3.5V < V10, V24 < 12V
3.5V < V10, V24 < 12V
VSD1 = VSD2 = 2.1V, 3.5V < V10, V24 < 12V
1.6
160
10
2.4
260
22
mA
µA
µA
Current Sense Threshold Voltage
LTC1142HV-ADJ, LTC1142L-ADJ
V14 = V28 = VOUT + 100mV, V2 = V16 = VREF + 25mV
V14 = V28 = VOUT – 100mV, V2 = V16 = VREF – 25mV
125
25
150
175
mV
mV
LTC1142, LTC1142HV
V28 = VOUT + 100mV (Forced)
V28 = VOUT – 100mV (Forced)
125
25
150
175
mV
mV
I10, I24
V1 – V28
V15 – V14
3.17
4.85
3
LTC1142/LTC1142L/LTC1142HV
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
VSHDN
Shutdown Pin Threshold
tOFF
Off-Time (Note 4)
– 40°C ≤ TA ≤ 85°C (Note 5), V10 = V24 = 10V, unless otherwise noted.
CONDITIONS
MIN
TYP
MAX
UNITS
LTC1142, LTC1142HV
V14 = VOUT + 100mV (Forced)
V14 = VOUT – 100mV (Forced)
125
25
150
175
mV
mV
0.55
0.8
2
V
3.8
5
6
µs
CT = 390pF, ILOAD = 700mA
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
LTC1142CG: TJ = TA + (PD × 95°C/ W)
Note 3: This current is for one regulator block. Total supply current is the
sum of Pins 10 and 24 currents. Dynamic supply current is higher due to
the gate charge being delivered at the switching frequency. See the
Applications Information section.
Note 4: In applications where RSENSE is placed at ground potential, the offtime increases approximately 40%.
Note 5: The LTC1142/LTC1142L/LTC1142HV are guaranteed to meet
specified performance from 0°C to 70°C and are designed, characterized
and expected to meet these extended temperature limits, but are not tested
at – 40°C and 85°C. Guaranteed I-grade parts are available, consult the
factory.
Note 6: The LTC1142L-ADJ allows operation down to VIN = 3.5V.
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TYPICAL PERFOR A CE CHARACTERISTICS
5V Output Efficiency
3.3V Output Efficiency
100
5V Efficiency vs Input Voltage
100
100
96
VIN = 5V
VIN = 10V
90
95
EFFICIENCY (%)
95
EFFICIENCY (%)
EFFICIENCY (%)
FIGURE 1 CIRCUIT
VOUT = 5V
98
VIN = 6V
VIN = 10V
90
ILOAD = 1A
94
92
90
ILOAD = 100mA
88
86
84
82
85
0.01
0.1
LOAD CURRENT (A)
2
1
80
85
0.01
0.1
LOAD CURRENT (A)
1
1142 G01
20
VIN = 6V
–20
10
∆VOUT (mV)
∆VOUT (mV)
ILOAD = 100mA
88
0
– 10
VIN = 12V
– 40
VIN = 6V
– 60
86
– 20
84
80
– 40
0
4
12
8
INPUT VOLTAGE (V)
16
20
1142 G04
VIN = 12V
– 80
– 30
82
4
FIGURE 1 CIRCUIT
RSENSE = 0.05Ω
0
94
90
20
20
FIGURE 1 CIRCUIT
ILOAD = 1A
30
96
92
16
Load Regulation
40
FIGURE 1 CIRCUIT
VOUT = 3.3V
ILOAD = 1A
12
8
INPUT VOLTAGE (V)
1142 G03
Line Regulation
100
98
4
1142 G02
3.3V Efficiency vs Input Voltage
EFFICIENCY (%)
0
2
0
4
12
8
INPUT VOLTAGE (V)
16
20
1142 G05
VOUT = 5V
VOUT = 3.3V
– 100
0
0.5
1.5
2.0
1.0
LOAD CURRENT (A)
2.5
1142 G06
LTC1142/LTC1142L/LTC1142HV
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TYPICAL PERFOR A CE CHARACTERISTICS
1.6
20
1.8
16
1.2
SUPPLY CURRENT (µA)
ACTIVE MODE
1.5
PER REGULATOR BLOCK
NOT INCLUDING
GATE CHARGE CURRENT
PINS 10, 24
0.9
0.6
VOUT = 5V
PER REGULATOR BLOCK
PINS 10, 24
VSHUTDOWN = 2V
18
1.4
NORMALIZED FREQUENCY
2.1
SUPPLY CURRENT (mA)
Operating Frequency vs
VIN – VOUT
Supply Current in Shutdown
DC Supply Current
14
12
10
8
6
0°C
1.2
70°C
1.0
0.8
25°C
0.6
0.4
4
0.3
SLEEP MODE
0.2
2
0
0
0
0
2
6
8 10 12 14
INPUT VOLTAGE (V)
4
16
0
18
2
4
6
8 10 12 14
INPUT VOLTAGE (V)
1142 G07
24
70
8
150
40
30
10
0
0
12
10
MAXIMUM
THRESHOLD
VSENSE = VOUT
50
4
80
200
260
140
OPERATING FREQUENCY (kHz)
8
Current Sense Threshold Voltage
20
QN + QP = 50nC
6
1142 G09
SENSE VOLTAGE (mV)
12
4
175
60
QN + QP = 100nC
OFF-TIME (µs)
GATE CHARGE CURRENT (mA)
80
16
2
VIN – VOUT VOLTAGE (V)
Off-Time vs Output Voltage
Gate Charge Supply Current
20
0
18
1142 G08
28
20
16
VOUT = 3.3V
1
75
50
MINIMUM
THRESHOLD
0
3
4
2
OUTPUT VOLTAGE (V)
1142 G10
100
25
VOUT = 5V
0
125
5
0
1142 G11
20
60
40
TEMPERATURE (°C)
80
100
1142 G12
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PI FU CTIO S
LTC1142/LTC1142HV
SENSE + 3 (Pin 1): The (+) Input to the 3.3V Section
Current Comparator. A built-in offset between Pins 1 and
28 in conjunction with RSENSE3 sets the current trip
threshold for the 3.3V section.
SHDN3 (Pin 2): When grounded, the 3.3V section operates normally. Pulling Pin 2 high holds both MOSFETs off
and puts the 3.3V section in micropower shutdown mode.
Requires CMOS logic-level signal with tr, t f < 1µs. Do not
“float” Pin 2.
SGND3 (Pin 3): The 3.3V section small-signal ground
must be routed separately from other grounds to the (–)
terminal of the 3.3V section output capacitor.
PGND3 (Pin 4): The 3.3V section driver power ground
connects to source of N-channel MOSFET and the (–)
terminal of the 3.3V section input capacitor.
NC (Pin 5): No Connection.
NDRIVE 3 (Pin 6): High Current Drive for Bottom N-Channel
MOSFET, 3.3V Section. Voltage swing at Pin 6 is from
ground to VIN3.
5
LTC1142/LTC1142L/LTC1142HV
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PI FU CTIO S
NC (Pins 7, 8): No Connection.
NC (Pins 21, 22): No Connection.
PDRIVE 5 (Pin 9): High Current Drive for Top P-Channel
MOSFET, 5V Section. Voltage swing at this pin is from VIN5
to ground.
PDRIVE 3 (Pin 23): High Current Drive for Top P-Channel
MOSFET, 3.3V Section. Voltage swing at this pin is from
VIN3 to ground.
VIN5 (Pin 10): Supply pin, 5V section, must be closely
decoupled to 5V power ground Pin 18.
VIN3 (Pin 24): Supply pin, 3.3V section, must be closely
decoupled to 3.3V power ground, Pin 4.
CT5 (Pin 11): External capacitor CT5 from Pin 11 to ground
sets the operating frequency for the 5V section. (The actual
frequency is also dependent upon the input voltage.)
CT3 (Pin 25): External capacitor CT3 from Pin 25 to ground
sets the operating frequency for the 3.3V section. (The
actual frequency is also dependent upon the input voltage.)
INTVCC5 (Pin 12) : Internal supply voltage for the 5V
section, nominally 3.3V, can be decoupled to signal ground,
Pin 17. Do not externally load this pin.
INTVCC3 (Pin 26): Internal supply voltage for the 3.3V
section, nominally 3.3V, can be decoupled to signal ground,
Pin 3. Do not externally load this pin.
ITH5 (Pin 13): Gain Amplifier Decoupling Point, 5V Section. The 5V section current comparator threshold increases with the Pin 13 voltage.
ITH3 (Pin 27): Gain Amplifier Decoupling Point, 3.3V
Section. The 3.3V section current comparator threshold
increases with the Pin 27 voltage.
SENSE – 5 (Pin 14): Connects to internal resistive divider
which sets the output voltage for the 5V section. Pin 14 is
also the (–) input for the current comparator on the
5V section.
SENSE – 3 (Pin 28): Connects to internal resistive divider
which sets the output voltage for the 3.3V section. Pin 28
is also the (–) input for the current comparator on the
3.3V section.
SENSE + 5 (Pin 15): The (+) Input to the 5V Section Current
Comparator. A built-in offset between Pins 15 and 14 in
conjunction with RSENSE5 sets the current trip threshold
for the 5V section.
SHDN5 (Pin 16): When grounded, the 5V section operates
normally. Pulling Pin 16 high holds both MOSFETs off and
puts the 5V section in micropower shutdown mode.
Requires CMOS logic signal with tr, t f < 1µs. Do not “float”
Pin 16.
SGND5 (Pin 17): The 5V section small-signal ground must
be routed separately from other grounds to the (–) terminal of the 5V section output capacitor.
PGND5 (Pin 18): The 5V section driver power ground
connects to source of N-channel MOSFET and the (–)
terminal of the 5V section input capacitor.
NC (Pin 19): No Connection.
NDRIVE 5 (Pin 20): High Current Drive for Bottom
N-Channel MOSFET, 5V Section. Voltage swing at Pin 20
is from ground to VIN5.
6
LTC1142HV-ADJ/LTC1142L-ADJ
SENSE + 1 (Pin 1): The (+) Input to the Section 1 Current
Comparator. A built-in offset between Pins 1 and 28 in
conjunction with RSENSE1 sets the current trip threshold
for this section.
VFB1 (Pin 2): This pin serves as the feedback pin from an
external resistive divider used to set the output voltage for
section 1.
SHDN1 (Pin 3): When grounded, the section 1 regulator
operates normally. Pulling Pin 3 high holds both MOSFETs
off and puts this section in micropower shutdown mode.
Requires CMOS logic signal with tr, t f < 1µs. Do not “float”
Pin 3.
SGND1 (Pin 4): The section 1 small-signal ground must
be routed separately from other grounds to the (–) terminal of the section 1 output capacitor.
PGND1 (Pin 5): The section 1 driver power ground connects to source of N-channel MOSFET and the (–) terminal
of the section 1 input capacitor.
LTC1142/LTC1142L/LTC1142HV
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PI FU CTIO S
NDRIVE 1 (Pin 6): High Current Drive for Bottom N-Channel
MOSFET, Section 1. Voltage swing at Pin 6 is from ground
to VIN1.
SGND2 (Pin 18): The section 2 small-signal ground must
be routed separately from other grounds to the (–) terminal of the section 2 output capacitor.
NC (Pins 7, 8): No Connection.
PGND2 (Pin 19): The section 2 driver power ground
connects to source of the N-channel MOSFET and the (–)
terminal of the section 2 input capacitor.
PDRIVE 2 (Pin 9): High Current Drive for Top P-Channel
MOSFET, Section 2. Voltage swing at this pin is from VIN2
to ground.
VIN2 (Pin 10): Supply pin, section 2, must be closely
decoupled to section 2 power ground, Pin 19.
CT2 (Pin 11): External capacitor CT2 from Pin 11 to ground
sets the operating frequency for the section 2. (The actual
frequency is also dependent upon the input voltage.)
NDRIVE 2 (Pin 20): High Current Drive for Bottom
N-Channel MOSFET, Section 2. Voltage swing at Pin 20 is
from ground to VIN2.
NC (Pins 21, 22): No Connection.
PDRIVE 1 (Pin 23): High Current Drive for Top P-Channel
MOSFET, Section 1. Voltage swing at this pin is from VIN1
to ground.
INTVCC2 (Pin 12) : Internal supply voltage for section 2,
nominally 3.3V, can be decoupled to signal ground, Pin
18. Do not externally load this pin.
VIN1 (Pin 24): Supply Pin, Section 1. Must be closely
decoupled to section 1 power ground Pin 5.
ITH2 (Pin 13): Gain Amplifier Decoupling Point, Section 2.
The section 2 current comparator threshold increases
with the Pin 13 voltage.
CT1 (Pin 25): External capacitor CT1 from Pin 25 to ground
sets the operating frequency for section 1. (The actual
frequency is also dependent upon the input voltage.)
SENSE – 2 (Pin 14): Connects (–) input for the current
comparator on section 2.
INTVCC1 (Pin 26): Internal supply voltage for section 1,
nominally 3.3V, can be decoupled to signal ground, Pin 4.
Do not externally load this pin.
SENSE + 2 (Pin 15): The (+) Input to the Section 2 Current
Comparator. A built-in offset between Pins 15 and 14 in
conjunction with RSENSE2 sets the current trip threshold
for this section.
VFB2 (Pin 16): This pin serves as the feedback pin from an
external resistive divider used to set the output voltage for
section 2.
ITH1 (Pin 27): Gain Amplifier Decoupling Point, Section 1.
The section 1 current comparator threshold increases
with the Pin 27 voltage.
SENSE – 1 (Pin 28): Connects to the (–) input for the
current comparator on section 1.
SHDN2 (Pin 17): When grounded, the section 2 regulator
operates normally. Pulling Pin 17 high holds both MOSFETs
off and puts section 2 in micropower shutdown mode.
Requires CMOS logic signal with tr, tf < 1µs. Do not “float”
Pin 17.
7
LTC1142/LTC1142L/LTC1142HV
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Only one regulator block shown. Pin numbers are for 3.3V (5V) sections for LTC1142/LTC1142HV,
and VOUT1 (VOUT2) for LTC1142L-ADJ/LTC1142HV-ADJ.
PIN NUMBERS FOR
LTC1142, LTC1142HV
2(16)
LTC1142-ADJ
3(17)
SGND
24(10) VIN
PIN NUMBERS
FOR LTC1142L-ADJ
LTC1142HV-ADJ
23(9)
LTC1142L-ADJ
LTC1142HV-ADJ
4(18)
3(17)
PDRIVE
SENSE –
1(15)
28(14)
LTC1142L-ADJ
LTC1142HV-ADJ
2(16)
NDRIVE
6(20)
SENSE +
NC/ADJ
4(18) PGND
–
LTC1142L-ADJ, LTC1142HV-ADJ: 5(19)
V
SLEEP
–
R
C
Q
+
VTH1
VTH2
25(11)
CT
ITH
–
+
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OPERATIO
27(13)
T
OFF-TIME
CONTROL
VIN
SENSE –
+
5pF
–
13k
G
+
1.25V
2(16)
LTC1142L-ADJ
LTC1142HV-ADJ
3(17)
100k
INTVCC
SHDN
REFERENCE
26(12)
1142 BD
Refer to Functional Diagram
The LTC1142 series consists of two individual regulator
blocks, each using current mode, constant off-time architectures to synchronously switch an external pair of
complementary power MOSFETs. The two regulators are
internally set to provide output voltages of 3.3V and 5V for
the LTC1142. The LTC1142HV-ADJ/LTC1142L-ADJ are
configured to provide two user selectable output voltages,
each set by external resistor dividers. Operating frequency is individually set on each section by the external
capacitors at CT, Pins 11 and 25.
The output voltage is sensed by an internal voltage divider
connected to Sense –, Pin 28 (14) (LTC1142) or external
divider returned to VFB, Pin 2 (16) (LTC1142-ADJ). A
voltage comparator V and a gain block G compare the
divided output voltage with a reference voltage of 1.25V.
To optimize efficiency, the LTC1142 series automatically
switches between two modes of operation, Burst Mode
and continuous mode. The voltage comparator is the
primary control element when the device is in Burst Mode
operation, while the gain block controls the output voltage
in continuous mode.
8
–
VOS
S
–
25mV TO 150mV
+
S
+
During the switch “ON” cycle in continuous mode, current
comparator C monitors the voltage between Pins 1 (15)
and 28 (14) connected across an external shunt in series
with the inductor. When the voltage across the shunt
reaches its threshold value, the PDrive output is switched
to VIN, turning off the P-channel MOSFET. The timing
capacitor connected to Pin 25 (11) is now allowed to
discharge at a rate determined by the off-time controller.
The discharge current is made proportional to the output
voltage [measured by Pin 28 (14)] to model the inductor
current, which decays at a rate that is also proportional to
the output voltage. While the timing capacitor is discharging, the NDrive output goes to VIN, turning on the N-channel
MOSFET.
When the voltage on the timing capacitor has discharged
past VTH1, comparator T trips, setting the flip-flop. This
causes the NDrive output to go low (turning off the
N-channel MOSFET) and the PDrive output to also go low
(turning the P-channel MOSFET back on). The cycle then
repeats.
LTC1142/LTC1142L/LTC1142HV
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Refer to Functional Diagram
As the load current increases, the output voltage decreases slightly. This causes the output of the gain stage
[Pin 27(13)] to increase the current comparator threshold, thus tracking the load current.
The sequence of events for Burst Mode operation is very
similar to continuous operation with the cycle interrupted
by the voltage comparator. When the output voltage is at
or above the desired regulated value, the P-channel
MOSFET is held off by comparator V and the timing
capacitor continues to discharge below VTH1. When the
timing capacitor discharges past VTH2, voltage comparator S trips, causing the internal sleep line to go low and the
N-channel MOSFET to turn off.
The circuit now enters sleep mode with both power
MOSFETs turned off. In sleep mode a majority of the
circuitry is turned off, dropping the quiescent current
from 1.6mA to 160µA (for one regulator block). The load
current is now being supplied from the output capacitor.
When the output voltage has dropped by the amount of
hysteresis in comparator V, the P-channel MOSFET is
again turned on and this process repeats.
To avoid the operation of the current loop interfering with
Burst Mode operation, a built-in offset VOS is incorporated
in the gain stage. This prevents the current comparator
threshold from increasing until the output voltage has
dropped below a minimum threshold.
To prevent both the external MOSFETs from ever being
turned on at the same time, feedback is incorporated to
sense the state of the driver output pins. Before the NDrive
output can go high, the PDrive output must also be high.
Likewise, the PDrive output is prevented from going low
while the NDrive output is high.
Using constant off-time architecture, the operating frequency is a function of the input voltage. To minimize the
frequency variation as dropout is approached, the off-time
controller increases the discharge current as VIN drops
below VOUT + 1.5V. In dropout the P-channel MOSFET is
turned on continuously (100% duty cycle) providing low
dropout operation with VOUT ~ VIN.
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The basic LTC1142 application circuit is shown in
Figure␣ 1. External component selection is driven by the
load requirement and begins with the selection of RSENSE.
Once RSENSE is known, CT and L can be chosen. Next, the
power MOSFETs and D1 are selected. Finally, CIN and
COUT are selected and the loop is compensated. Since the
3.3V and 5V sections in the LTC1142 are identical and
similarly section 1 and section 2 in the LTC1142HV-ADJ/
LTC1142L-ADJ are identical, the process of component
selection is the same for both sections. The circuit shown
in Figure 1 can be configured for operation up to an input
voltage of 20V.
RSENSE Selection for Output Current
RSENSE is chosen based on the required output current.
The LTC1142 current comparators have a threshold range
which extends from a minimum of 25mV/RSENSE to a
maximum of 150mV/RSENSE. The current comparator
threshold sets the peak of the inductor ripple current,
yielding a maximum output current IMAX equal to the peak
value less half the peak-to-peak ripple current. For proper
Burst Mode operation, IRIPPLE(P-P) must be less than or
equal to the minimum current comparator threshold.
Since efficiency generally increases with ripple current,
the maximum allowable ripple current is assumed, i.e.,
IRIPPLE(P-P) = 25mV/RSENSE (see CT and L Selection for
Operating Frequency section). Solving for RSENSE and
allowing a margin for variations in the LTC1142 and
external component values yields:
RSENSE =
100mV
IMAX
A graph for Selecting RSENSE vs Maximum Output Current
is given in Figure 2.
The load current below which Burst Mode operation commences, IBURST, and the peak short-circuit current ISC(PK),
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both track IMAX. Once RSENSE has been chosen, IBURST and
ISC(PK) can be predicted from the following:
IBURST ≈
15mV
RSENSE
ISC(PK) =
150mV
RSENSE
As the operating frequency is increased the gate charge
losses will be higher, reducing efficiency (see Efficiency
Considerations section). The complete expression for
operating frequency of the circuit in Figure 1 is given by:
The LTC1142 automatically extends tOFF during a short
circuit to allow sufficient time for the inductor current to
decay between switch cycles. The resulting ripple current
causes the average short-circuit current ISC(AVG) to be
reduced to approximately IMAX.
0.20
f=
1 VOUT
1−
tOFF
VIN
where:
V
tOFF = 1.3 • 104 • CT • REG
VOUT
VREG is the desired output voltage (i.e., 5V, 3.3V). VOUT
is the measured output voltage. Thus VREG / VOUT = 1 in
regulation.
0.15
RSENSE (Ω)
A graph for selecting CT versus frequency including the
effects of input voltage is given in Figure 3.
Note that as VIN decreases, the frequency decreases.
When the input-to-output voltage differential drops below
1.5V for a particular section, the LTC1142 reduces tOFF in
that section by increasing the discharge current in CT. This
prevents audible operation prior to dropout.
0.10
0.05
0
0
1
3
4
2
MAXIMUM OUTPUT CURRENT (A)
5
1000
VSENSE = VOUT = 5V
1142 F02
800
L and CT Selection for Operating Frequency
Each regulator section of the LTC1142 uses a constant offtime architecture with tOFF determined by an external
timing capacitor CT. Each time the P-channel MOSFET
switch turns on, the voltage on CT is reset to approximately
3.3V. During the off-time, CT is discharged by a current
which is proportional to VOUT. The voltage on CT is
analogous to the current in inductor L, which likewise
decays at a rate proportional to VOUT. Thus the inductor
value must track the timing capacitor value.
The value of CT is calculated from the desired continuous
mode operating frequency:
CT =
1
2.6 • 104 • f
Assumes VIN = 2VOUT, Figure 1 circuit.
10
CAPACITANCE (pF)
Figure 2. Selecting RSENSE
600
VIN = 12V
400
VIN = 7V
200
0
VIN = 10V
0
50
150
200
100
FREQUENCY (kHz)
250
300
1142 F03
Figure 3. Timing Capacitor Value
Once the frequency has been set by CT, the inductor L must
be chosen to provide no more than 25mV/RSENSE of peakto-peak inductor ripple current. This results in a minimum
required inductor value of:
LMIN = 5.1 • 105 • RSENSE • CT • VREG
As the inductor value is increased from the minimum
value, the ESR requirements for the output capacitor are
LTC1142/LTC1142L/LTC1142HV
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eased at the expense of efficiency. If too small an inductor
is used, the inductor current will decrease past zero and
change polarity. A consequence of this is that the LTC1142
may not enter Burst Mode operation and efficiency will be
severely degraded at low currents.
Inductor Core Selection
Once the minimum value for L is known, the type of
inductor must be selected. The highest efficiency will be
obtained using ferrite, molypermalloy (MPP), or Kool Mµ®
cores. Lower cost powdered iron cores provide suitable
performance, but cut efficiency by 3% to 7%. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses will increase.
Ferrite designs have very low core loss, so design goals
can concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple which can cause Burst Mode operation to be falsely
triggered. Do not allow the core to saturate!
Kool Mµ (from Magnetics, Inc.) is a very good, low loss
core material for toroids with a “soft” saturation characteristic. Molypermalloy is slightly more efficient at high
(>200kHz) switching frequencies, but it is quite a bit more
expensive. Toroids are very space efficient, especially
when you can use several layers of wire. Because they
generally lack a bobbin, mounting is more difficult. However, new designs for surface mount are available from
Coiltronics and Beckman Industrial Corporation which do
not increase the height significantly.
Power MOSFET and D1, D2 Selection
Two external power MOSFETs must be selected for use with
each section of the LTC1142: a P-channel MOSFET for the
main switch, and an N-channel MOSFET for the synchronous
switch. The main selection criteria for the power MOSFETs
are the threshold voltage VGS(TH) and on- resistance RDS(ON).
The minimum input voltage determines whether standard
threshold or logic-level threshold MOSFETs must be
used. For VIN > 8V, standard threshold MOSFETs
(VGS(TH) < 4V) may be used. If VIN is expected to drop
below 8V, logic-level threshold MOSFETs (VGS(TH) <
2.5V) are strongly recommended. When logic-level
MOSFETs are used, the LTC1142 supply voltage must
be less than the absolute maximum VGS ratings for the
MOSFETs.
The maximum output current IMAX determines the RDS(ON)
requirement for the two MOSFETs. When the LTC1142 is
operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always
conducting the average load current. The duty cycles for
the two MOSFETs are given by:
P-Ch Duty Cycle =
VOUT
VIN
N-Ch Duty Cycle =
VIN − VOUT
VIN
From the duty cycles the required RDS(ON) for each
MOSFET can be derived:
P-Ch RDS(ON) =
N-Ch RDS(ON) =
VIN • PP
2
(
VOUT • IMAX • 1 + δP
)
VIN • PN
(VIN − VOUT) • IMAX2 • (1+ δN )
where PP and PN are the allowable power dissipations and
δP and δN are the temperature dependencies of RDS(ON).
PP and PN will be determined by efficiency and/or thermal
requirements (see Efficiency Considerations). (1 + δ) is
generally given for a MOSFET in the form of a normalized
RDS(ON) vs Temperature curve, but δ = 0.007/°C can be
used as an approximation for low voltage MOSFETs.
The Schottky diodes D1 and D2 shown in Figure 1 only
conduct during the dead-time between the conduction of
the respective power MOSFETs. The sole purpose of D1
and D2 is to prevent the body diode of the N-channel
MOSFET from turning on and storing charge during the
Kool Mµ is a registered trademark of Magnetics, Inc.
11
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CIN and COUT Selection
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle VOUT/ VIN. To
prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
CIN Required IRMS ≈ IMAX
[V (V
OUT
IN − VOUT
)]
1/ 2
VIN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst case conditon is commonly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question. An additional 0.1µF to 1µF ceramic capacitor is
also required on each VIN line (Pins 10 and 24) for high
frequency decoupling.
The selection of COUT is driven by the required Effective
Series Resistance (ESR). The ESR of COUT must be less
than twice the value of RSENSE for proper operation of the
LTC1142:
COUT Required ESR < 2RSENSE
Optimum efficiency is obtained by making the ESR equal
to RSENSE. As the ESR is increased up to 2RSENSE, the
efficiency degrades by less than 1%. If the ESR is greater
than 2RSENSE, the voltage ripple on the output capacitor
will prematurely trigger Burst Mode operation, resulting in
disruption of continuous mode and an efficiency hit which
can be several percent.
Manufacturers such as Nichicon and United Chemicon
should be considered for high performance capacitors.
The OS-CON semiconductor dielectric capacitor available
12
from Sanyo has the lowest ESR/size ratio of any aluminum
electrolytic at a somewhat higher price. Once the ESR
requirement for COUT has been met, the RMS current
rating generally far exceeds the IRIPPLE(P-P) requirement.
In surface mount applications multiple capacitors may
have to be parallel to meet the capacitance, ESR or RMS
current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both
available in surface mount configurations. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice
is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. For
example, if 200µF/10V is called for in an application
requiring 3mm height, two AVX 100µF/10V (P/N TPSD
107K010) could be used. Consult the manufacturer for
other specific recommendations.
At low supply voltages, a minimum capacitance at COUT is
needed to prevent an abnormal low frequency operating
mode (see Figure 4). When COUT is made too small, the
output ripple at low frequencies will be large enough to trip
the voltage comparator. This causes Burst Mode operation to be activated when the LTC1142 would normally be
in continuous operation. The output remains in regulation
at all times.
1000
OUTPUT CAPACITANCE (µF)
dead-time, which could cost as much as 1% in efficiency
(although there are no other harmful effects if D1 and D2
are omitted). Therefore, D1 and D2 should be selected for
a forward voltage of less than 0.6V when conducting IMAX.
L = 50µH
RSENSE = 0.02Ω
800
L = 25µH
RSENSE = 0.02Ω
600
400
L = 50µH
RSENSE = 0.05Ω
200
0
0
1
3
4
2
VIN – VOUT VOLTAGE (V)
5
1142 F04
Figure 4. Minimum Value of COUT
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in DC (resistive) load
LTC1142/LTC1142L/LTC1142HV
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current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD • ESR, where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge
or discharge COUT until the regulator loop adapts to the
current change and returns VOUT to its steady- state
value. During this recovery time VOUT can be monitored
for overshoot or ringing which would indicate a stability
problem. The Pin 27 (13) external components shown in
the Figure 1 circuit will prove adequate compensation for
most applications.
section) less the gate charge current. For VIN = 10V the
LTC1142 DC supply current for each section is 160µA
with no load, and increases proportionally with load up
to a constant 1.6mA after the LTC1142 has entered
continuous mode. Because the DC bias current is
drawn from VIN, the resulting loss increases with input
voltage. For VIN = 10V the DC bias losses are generally
less than 1% for load currents over 30mA. However, at
very low load currents the DC bias current accounts for
nearly all of the loss.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately 25 • CLOAD.
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
2. MOSFET gate charge current results from switching
the gate capacitance of the power MOSFETs. Each time
a MOSFET gate is switched from low to high to low
again, a packet of charge dQ moves from VIN to ground.
The resulting dQ/dt is a current out of VIN which is
typically much larger than the DC supply current. In
continuous mode, IGATE(CHG) = f (QN + QP). The typical
gate charge for a 0.1Ω N-channel power MOSFET is
25nC, and for a P-channel about twice that value. This
results in IGATE(CHG) = 7.5mA in 100kHz continuous
operation, for a 2% to 3% typical mid-current loss with
VIN = 10V.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percentage of input power. (For high efficiency circuits only small
errors are incurred by expressing losses as a percentage
of output power.)
Although all dissipative elements in the circuit produce
losses, three main sources usually account for most of the
losses in LTC1142 circuits:
1. LTC1142 DC bias current
2. MOSFET gate charge current
3. I2R losses
1. The DC supply current is the current which flows into
VIN (pin 24 for the 3.3V section, Pin 10 for the 5V
Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
principal reason why the highest efficiency circuits
operate at moderate frequencies. Furthermore, it argues against using larger MOSFETs than necessary to
control I2R losses, since overkill can cost efficiency as
well as money!
3. I2R losses are easily predicted from the DC resistances
of the MOSFET, inductor, and current shunt. In continuous mode the average output current flows through L
and RSENSE, but is “chopped” between the P-channel
and N-channel MOSFETs. If the two MOSFETs have
approximately the same RDS(ON), then the resistance of
one MOSFET can simply be summed with the resistances of L and RSENSE to obtain I2R losses. For
example, if each RDS(ON) = 0.1Ω, RL = 0.15Ω, and
RSENSE = 0.05Ω, then the total resistance is 0.3Ω. This
results in losses ranging from 3% to 12% as the output
current increases from 0.5A to 2A. I2R losses cause the
efficiency to roll off at high output currents.
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Figure 5 shows how the efficiency losses in one section of
a typical LTC1142 regulator end up being apportioned.
The gate charge loss is responsible for the majority of the
efficiency lost in the mid-current region. If Burst Mode
operation was not employed at low currents, the gate
charge loss alone would cause efficiency to drop to
unacceptable levels. With Burst Mode operation, the DC
supply current represents the lone (and unavoidable) loss
component which continues to become a higher percentage as output current is reduced. As expected, the I2R
losses dominate at high load currents.
Other losses including CIN and COUT ESR dissipative
losses, MOSFET switching losses, Schottky conduction
losses during dead-time and inductor core losses, generally account for less than 2% total additional loss.
100
EFFICIENCY/LOSS (%)
GATE CHARGE
95
1/2 LTC1142 IQ
N - Ch RDS(ON) =
12(0.25)
5(2)2 (1.27)
= 0.12Ω
12(0.25)
5(2)2 (1.27)
= 0.085Ω
The P-channel requirement can be met by a Si9430DY,
while the N-channel requirement is exceeded by a
Si9410DY. Note that the most stringent requirement for
the N-channel MOSFET is with VOUT = 0 (i.e., short circuit).
During a continuous short circuit, the worst case
N-channel dissipation rises to:
PN = ISC(AVG)2 • RDS(ON) • (1 + δN)
CIN will require an RMS current rating of at least 1A at
temperature, and COUT will require an ESR of 0.05Ω for
optimum efficiency.
90
85
0.03
0.3
1
0.1
OUTPUT CURRENT (A)
3
1142 F05
Figure 5. Efficiency Loss
Design Example
As a design example, assume VIN = 12V (nominal), 5V
section, IMAX = 2A and f = 200kHz; RSENSE, CT and L can
immediately be calculated:
RSENSE = 100mV/2 = 0.05Ω
tOFF = (1/200kHz) • [1 – (5/12)] = 2.92µs
CT5 = 2.92µs/(1.3 • 104) = 220pF
L2MIN = 5.1 • 105 • 0.05Ω • 220pF • 5V = 28µH
Assume that the MOSFET dissipations are to be limited to
PN = PP = 250mW.
If TA = 50°C and the thermal resistance of each MOSFET
is 50°C/ W, then the junction temperatures will be 63°C
14
P - Ch RDS(ON) =
With the 0.05Ω sense resistor, ISC(AVG) = 2A will result,
increasing the 0.085Ω N-channel dissipation to 450mW at
a die temperature of 73°C.
I2R
80
0.01
and δP = δN = 0.007(63 – 25) = 0.27. The required RDS(ON)
for each MOSFET can now be calculated:
Now allow VIN to drop to its minimum value. At lower input
voltages the operating frequency will decrease and the
P-channel will be conducting most of the time, causing its
power dissipation to increase. At VIN(MIN) = 7V:
fMIN = (1/2.92µs)[1 – (5V/ 7V)] = 98kHz
PP =
5V(0.12Ω)(2A)2 (1.27)
= 435mV
7V
A similar calculation for the 3.3V section results in the
component values shown in Figure 14.
LTC1142HV-ADJ/LTC1142L-ADJ
Adjustable Applications
When an output voltage other than 3.3V or 5V is required,
the LTC1142 adjustable version is used with an external
resistive divider from VOUT to VFB, Pin 2 (16). The regulated output voltage is determined by:
R2
VOUT = 1.25 1 +
R1
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To prevent stray pickup a 100pF capacitor is suggested
across R1 located close to the LTC1142HV-ADJ/LTC1142LADJ as in Figure 6. The external divider network must be
placed across COUT with the negative plate of COUT returned
to signal ground. Refer to the Board Layout Checklist.
RSENSE
R2
VFB
[PIN 2(16)]
VOUT
+
100pF
R1
COUT
SGND
[PIN 4(18)]
1142 F06
the layout diagram of Figure 7. In general each block
should be self-contained with little cross coupling for best
performance. Check the following in your layout:
1. Are the signal and power grounds segregated? The
LTC1142 signal ground [Pin 3 (17) for the LTC1142, Pin
4 (18) for LTC1142-ADJ] must return to the (–) plate of
COUT. The power ground returns to the source of the
N-channel MOSFET, anode of the Schottky diode,
and (–) plate of CIN, which should have as short lead
lengths as possible.
2. Does the LTC1142 Sense – , Pin 28 (14) connect to a
point close to RSENSE and the (+) plate of COUT?
Figure 6. LTC1142-ADJ External Feedback Network
Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1142. These items are also illustrated graphically in
3. Are the Sense – and Sense + leads routed together with
minimum PC trace spacing? The 1000pF capacitor
between Pins 1 (15) and 28 (14) should be as close as
possible to the LTC1142. Ensure accurate current sensSENSE RESISTOR PCB PATTERN
1000pF
+
RSENSE3
+
1
SHDN (3.3V OUTPUT)
–
2
SENSE +3
SENSE –3
SHDN3
ITH3
3 SGND3
INTVCC3
L1
4
CT3
PGND3
5 NC
6
N-CH
–
D1
8 NC
1µF
CIN3
+
+
10
VIN5
12
3300pF
CT5
13
1k
14
27
CT3
+
26
25
CIN5
24
VIN3
+
P-CH
1µF
VIN5
D2
NC 22
LTC1142
9 PDRIVE 5
11
+
NDRIVE 3
SENSE + SENSE –
1k
3300pF
PDRIVE 3 23
7 NC
P-CH
VIN3
VIN3
28
+
COUT3
VOUT3
–
NC 21
NDRIVE 5
N-CH
20
NC 19
VIN5
CT5
PGND5
INTVCC5
SGND5
ITH5
SHDN5
SENSE – 5
SENSE +5
18
L2
17
–
16
SHDN (5V OUTPUT)
VOUT5
15
COUT5
+
RSENSE5
+
BOLD LINES INDICATE HIGH CURRENT PATHS
1000pF
1142 F07
Figure 7. LTC1142 Layout Diagram (see Board Layout Checklist)
15
LTC1142/LTC1142L/LTC1142HV
U
W
U
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APPLICATIO S I FOR ATIO
ing with Kelvin connections. Be sure to use a PCB
pattern similar to that shown in Figure 7 for the current
sense resistors.
4. Does the (+) plate of CIN connect to the source of the
P-channel MOSFET as closely as possible? This capacitor provides the AC current to the P-channel MOSFET.
5. Is the input decoupling capacitor (1µF/0.22µF) connected closely between Pin 24 (10) and power ground
[Pin 4 (18) for the LTC1142, Pin 5 (19) for the LTC1142ADJ]? This capacitor carries the MOSFET driver peak
currents.
6. Are the shutdown Pins 2 and 16 for the LTC1142 (Pins
3 and 17 for the LTC1142-ADJ) actively pulled to
ground during normal operation? Both Shutdown pins
are high impedance and must not be allowed to float.
Both pins can be driven by the same external signal if
needed.
7. For the LTC1142-ADJ adjustable applications, the resistive divider R1, R2 must be connected between the
(+) plate of COUT and signal ground.
Output Crowbar
An added feature to using an N-channel MOSFET as the
synchronous switch is the ability to crowbar the output
with the same MOSFET. Pulling the CT , Pin 25 (11) above
1.5V when the output voltage is greater than the desired
regulated value will turn “on” the N-channel MOSFET for
that regulator section.
A fault condition which causes the output voltage to go
above a maximum allowable value can be detected by
external circuitry. Turning on the N-channel MOSFET
when this fault is detected will cause large currents to flow
and blow the system fuse.
The N-channel MOSFET needs to be sized so it will safely
handle this overcurrent condition. The typical delay from
pulling the CT pin high and the NDrive Pin 6 (20) going high
is 250ns. Note: Under shutdown conditions, the N-channel is held OFF and pulling the CT pin high will not cause
the N-channel MOSFET to crowbar the output.
A simple N-channel FET can be used as an interface
between the overvoltage detect circuitry and the LTC1142
as shown in Figure 8.
16
PIN 26(12)
FROM CROWBAR
DETECT CIRCUIT
(ACTIVE WHEN VGATE = VIN
OFF WHEN VGATE = GND)
VN2222LL
PIN 25(11)
INT VCC
LTC1142
CT
1142 F08
Figure 8. Output Crowbar Interface
Troubleshooting Hints
Since efficiency is critical to LTC1142 applications, it is
very important to verify that the circuit is functioning
correctly in both continuous and Burst Mode operation.
The waveform to monitor is the voltage on the CT, Pins 25
and 11.
In continuous mode (ILOAD > IBURST) the voltage on the CT
pin should be a sawtooth with a 0.9VP-P swing. This
voltage should never dip below 2V as shown in Figure 9a.
When load currents are low (ILOAD < IBURST) Burst Mode
operation occurs. The voltage on the CT pin now falls to
ground for periods of time as shown in Figure 9b.
3.3V
0V
(a) CONTINUOUS MODE OPERATION
3.3V
0V
(b) Burst Mode OPERATION
1142 F09
Figure 9. CT Waveforms
Inductor current should also be monitored. Look to verify
that the peak-to-peak ripple current in continuous mode
operation is approximately the same as in Burst Mode
operation.
If Pin 25 or Pin 11 is observed falling to ground at high
output currents, it indicates poor decoupling or improper
grounding. Refer to the Board Layout Checklist.
Auxiliary Windings––Suppressing Burst Mode
Operation
The LTC1142 synchronous switch removes the normal
limitation that power must be drawn from the inductor
primary winding in order to extract power from auxiliary
windings. With synchronous switching, auxiliary outputs
LTC1142/LTC1142L/LTC1142HV
U
U
W
U
APPLICATIO S I FOR ATIO
may be loaded without regard to the primary output load,
providing that the loop remains in continuous mode
operation.
Burst Mode operation can be suppressed at low output
currents with a simple external network which cancels the
25mV minimum current comparator threshold. This technique is also useful for eliminating audible noise from
certain types of inductors in high current (IOUT > 5A)
applications when they are lightly loaded.
An external offset is put in series with the Sense – pin to
subtract from the built-in 25mV offset. An example of this
technique is shown in Figure 10. Two 100Ω resistors are
inserted in series with the sense leads from the sense
resistor.
1000pF
SENSE –
[PIN 28(14)]
R1
100Ω
R1
VOFFSET = VOUT •
R1 + R3
If VOFFSET > 25mV, the built-in offset will be cancelled and
Burst Mode operation is prevented from occurring. Since
VOFFSET is constant, the maximum load current is also
decreased by the same offset. Thus, to get back to the
same IMAX, the value of the sense resistor must be lower:
R SENSE ≈
75mV
I MAX
To prevent noise spikes from erroneously tripping the
current comparator, a 1000pF capacitor is needed across
Pins 1 (15) and Pins 28 (14).
R2
100Ω
SENSE +
[PIN 1(15)]
With the addition of R3 a current is generated through R1
causing an offset of:
RSENSE
VOUT
+
R3
COUT
1142 F10
Figure 10. Suppression of Burst Mode Operation
U
TYPICAL APPLICATIO S
(For additional high efficiency circuits, see Application Note 54)
VIN
5.2V TO 18V
+
VOUT1
3.6V/2A
RSENSE1
0.05Ω
CIN1
22µF
35V
×2
+
0.22µF
P-CH
Si9430DY
23
L1
27µH
1
1000pF
28
COUT1
220µF
10V
×2
2
+
R2
100k
1%
R1
52.3k
1%
D1
MBRS130T3
6
N-CH
Si9410DY
0.22µF
0V = NORMAL
>1.5V = SHDN
3
24
VIN1
10
17
SHDN1
VIN2
9
PDRIVE 2
SHDN2
PDRIVE 1
15
SENSE + 2
+
SENSE 1
LTC1142HV-ADJ
SENSE – 1
SENSE – 2
VFB2
VFB1
NDRIVE 1
NDRIVE 2
PGND1 SGND1 CT1
5
100pF
4
25
ITH1
27
RC1
1k
ITH2
13
RC2
1k
CT2
SGND2 PGND2
11
18
19
P-CH
Si9430DY
L2
33µH
CIN2
22µF
35V
×2
RSENSE2
0.05Ω
VOUT2
5V/2A
1000pF
14
16
+
20
N-CH
Si9410DY
CC1
CT2
CT1
CC2
270pF 3300pF 3300pF 270pF
RSENSE1, RSENSE2 : DALE WSL-2010-.05
L1: SUMIDA CDRH125-270
L2: SUMIDA CDRH125-330
D2
MBRS130T3
100pF
R4
150k
1%
COUT2
220µF
10V
×2
R3
49.9k
1%
1142 F11
Figure 11. LTC1142HV-ADJ Dual Regulator with 3.6V/2A and 5V/2A Outputs
17
LTC1142/LTC1142L/LTC1142HV
U
TYPICAL APPLICATIO S
VIN
4.5V TO 18V
+
VOUT1
2.5V/1.5A
0.22µF
23
1
1000pF
28
COUT1
220µF
10V
×2
2
+
6
D1
MBRS130T3
R2
49.9k
1%
R1
49.9k
1%
0.22µF
0V = NORMAL
>1.5V = SHDN
P-CH
Si9430DY
L1
33µH
RSENSE1
0.075Ω
CIN2
22µF
35V
×2
+
CIN1
22µF
35V
×2
N-CH
Si9410DY
3
24
VIN1
VIN2
9
PDRIVE 2
SHDN2
PDRIVE 1
L2
25µH
15
SENSE + 2
+
SENSE 1
LTC1142HV-ADJ
SENSE – 1
SENSE – 2
VFB2
VFB1
NDRIVE 1
NDRIVE 2
PGND1 SGND1 CT1
5
P-CH
Si9430DY
10
17
SHDN1
4
ITH1
25
100pF
CT2
ITH2
27
RC1
1k
13
RC2
1k
18
1000pF
16
+
20
D2
MBRS130T3
N-CH
Si9410DY
19
R4
84.5k
1%
COUT2
220µF
10V
×2
R3
51k
1%
100pF
CC1
CT1
CT2
CC2
330pF 3300pF 3300pF 330pF
RSENSE1: IRC L1206-01-R075-J
RSENSE2: IRC L1206-01-R050-J
VOUT2
3.3V/2A
14
SGND2 PGND2
11
RSENSE2
0.05Ω
L1: COILTRONICS CTX33-4
L2: COILTRONICS CTX25-4
1142 F12
Figure 12. LTC1142HV-ADJ High Efficiency Regulator with 3.3V/2A and 2.5V/1.5A Outputs
VIN
5.2V TO 18V
CIN3
22µF
25V
×2
+
+
0.22µF
RSENSE3
0.033Ω
2
24
VIN3
P-CH
Si9433DY
VOUT3
3.3V/3A
10
PDRIVE 5
SENSE + 3
28
D1
MBRS130T3
6
N-CH
Si9410DY
SENSE + 5
LTC1142HV
SENSE – 5
NDRIVE 3
NDRIVE 5
4
3
25
ITH3
ITH5
27
RC3
510Ω
13
RC5
1k
9
CIN5
22µF
25V
×2
L2
22µH
RSENSE5
0.05Ω
VOUT5
5V/2A
15
1000pF
SENSE – 3
PGND3 SGND3 CT3
P-CH
Si9430DY
VIN5
SHDN5
PDRIVE 3
1000pF
COUT3
100µF
10V
×3
16
SHDN3
23
L1
10µH
1
+
0.22µF
0V = NORMAL
>1.5V = SHDN
CT5
SGND5 PGND5
11
17
18
14
D2
MBRS130T3
20
N-CH
Si9410DY
+
COUT5
220µF
10V
×2
CC3
CT3
CT5
CC5
200pF 3300pF 3300pF 150pF
RSENSE3: IRC L1206-01-R033-J
RSENSE5: IRC L1206-01-R050-J
L1: COILCRAFT D03316P-103
L2: COILCRAFT D03316P-223
Figure 13. LTC1142HV High Efficiency Regulator with 3.3V/3A and 5V/2A Outputs
18
1142 F13
LTC1142/LTC1142L/LTC1142HV
U
TYPICAL APPLICATIO S
VIN
6.5V TO
14V
+
22µF
25V
×2
+
VOUT3
3.3V/2A
23
L1
33µH
RSENSE3
0.05Ω
16
SHDN3
PDRIVE 3
1
PDRIVE 5
SENSE + 3
28
D1
MBRS140T3
+
SENSE + 5
LTC1142
SENSE – 5
NDRIVE 3
NDRIVE 5
N-CH
Si9410DY
ITH3
PGND3 SGND3 CT3
4
3
25
ITH5
27
RC3
510Ω
22µF
25V
×2
P-CH
Si9430DY
T1
9
CT5
17
VOUT5
5V/2A
15
100Ω
R1,100Ω
14
R5
18k
20
D2
MBRS140T3
N-CH
Si9410DY
SGND5 PGND5
13
11
RC5
510Ω
RSENSE5
0.04Ω
30µH
1000pF
SENSE – 3
6
100µF
10V
×2
10
VIN5
SHDN5
0.01µF
+
1µF
2
24
VIN3
P-CH
Si9430DY
+
0V = NORMAL
>1.5V = SHDN
1µF
18
+
220µF
10V
×2
VN2222LL
CT3
CT5
CC3
CC5
390pF 3300pF 3300pF 200pF
12V ENABLE
0V = 12V OFF
>3V = 12V ON
(6V MAX)
12V/150mA
22µF
25V
1
+
R3
649k
1%
2
20pF
VOUT
SHUTDOWN
ADJ
R4
294k
1%
RSENSE3: KRL SL-C1-1/2-0R050J
RSENSE5: KRL SL-C1-1/2-0R040J
L1: COILTRONICS CTX33-4
T1: DALE LPE-6562-A026
PRIMARY: SECONDARY = 1:1.8
D3
MBRS140T3
5
C9
22µF
35V
22Ω
+
1000pF
LT1121
VIN
8
1142 F14
GND
3
Figure 14. LTC1142 Triple Output Regulator with Switched 12V Output
VIN
8V TO 18V
FROM WALL ADAPTER
+
D3
MBRS340T3
RSENSE1
0.1Ω
0V = CHARGE ON
>1.5V = CHARGE OFF
+
CIN1
22µF
35V
×2
0.22µF
0.22µF
P-CH
Si9430DY
23
L1
50µH
1
1000pF
28
COUT1
220µF
10V
2
+
R2
274k
1%
R1
49.9k
1%
0V = OUTPUT ON
>1.5V = 3.3V OUTPUT OFF
D1
MBRS140T3
6
N-CH
Si9410DY
24
VIN1
17
3
SHDN1
PDRIVE 1
SENSE + 1
SENSE + 2
LTC1142HV-ADJ
SENSE – 1
SENSE – 2
VFB2
VFB1
NDRIVE 1
NDRIVE 2
PGND1 SGND1 CT1
5
4
100pF
25
ITH1
27
CT1
200pF
“1” FOR TRICKLE CHARGE
ITH2
13
CT2
SGND2 PGND2
11
18
19
RC1
1k
RC2
1k
CC1
3300pF
CT2
CC2
3300pF 330pF
VN2222LL
RSENSE1: KRL SL-C1-1/2-1R100J
RSENSE2: KRL SL-C1-1/2-1R050J
L1: COILTRONICS CTX50-4
L2: COILTRONICS CTX25-4
10
VIN2
9
PDRIVE 2
SHDN2
RX
51Ω
CIN2
22µF
25V
×2
VBATT
4 CELLS
NiCAD
P-CH
Si9433DY
L2
25µH
RSENSE2
0.05Ω
VOUT2
3.3V/2A
15
1000pF
14
16
+
20
N-CH
Si9410DY
D2
MBRS140T3
100pF
FAST CHARGE = 130mV/RSENSE1 = 1.3A
TRICKLE CHARGE = 130mV/RSENSE1 = 100mA
R4
84.5k
1%
COUT2
220µF
10V
×2
R3
51k
1%
1142 F15
Figure 15. LTC1142HV-ADJ High Efficiency Power Supply Providing 3.3V/2A with Built-In Battery Charger
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC1142/LTC1142L/LTC1142HV
U
TYPICAL APPLICATIO S
1400
OUTPUT CURRENT (mA)
1200
1000
800
600
400
200
0
1
0
2
3
SET RESISTANCE (kΩ)
4
1142 F16
Figure 16. LTC1142HV-ADJ Output Current vs Trickle Charge Set Resistance
(RX) for the Circuit in Figure 15 Using a 0.1Ω Current Sense Resistor RSENSE1
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
10.07 – 10.33*
(0.397 – 0.407)
5.20 – 5.38**
(0.205 – 0.212)
1.73 – 1.99
(0.068 – 0.078)
28 27 26 25 24 23 22 21 20 19 18 17 16 15
0° – 8°
0.13 – 0.22
(0.005 – 0.009)
0.55 – 0.95
(0.022 – 0.037)
0.65
(0.0256)
BSC
NOTE: DIMENSIONS ARE IN MILLIMETERS
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
7.65 – 7.90
(0.301 – 0.311)
0.25 – 0.38
(0.010 – 0.015)
0.05 – 0.21
(0.002 – 0.008)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
G28 SSOP 1098
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No RSENSE is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.
20
Linear Technology Corporation
1142fd LT/TP 0600 2K REV D • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
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