LTC1344IG#PBF

LTC1344 Software-Selectable Cable Terminator U FEATURES ■ ■ DESCRIPTIO The LTC ® 1344 features six software-selectable multiprotocol cable terminators. Each terminator can be configured as an RS422 (V.11) 100Ω minimum differential load, V.35 T-network load or an open circuit for use with RS232 (V.28) or RS423 (V.10) transceivers that provide their own termination. When combined with the LTC1343, the LTC1344 forms a complete software-selectable multiprotocol serial port. A data bus latch feature allows sharing of the select lines between multiple interface ports. Software-Selectable Cable Termination for: RS232 (V.28) RS423 (V.10) RS422 (V.11) RS485 RS449 EIA530 EIA530-A V.35 V.36 X.21 Outputs Won’t Load the Line with Power Off The LTC1344 is available in a 24-lead SSOP. U APPLICATIO S ■ ■ Data Networking CSU and DSU Data Routers U ■ , LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATION CTS DSR DCD DTR RTS RL TM RXD RXC TXC SCTE TXD LL D3 D2 D1 Daisy-Chained Control Outputs LTC1343 LTC1343 D4 R3 R4 R2 D3 D1 D2 D4 R1 R3 R4 R1 R2 LTC1344 13 5 22 6 10 8 23 20 19 4 21 1 7 25 16 3 17 12 15 11 24 14 2 18 LL A (141) TXD A (103) TXD B SCTE A (113) SCTE B TXC A (114) TXC B RXC A (115) RXC B RXD A (104) RXD B TM A (142) SGND (102) SHIELD (101) RL A (140) RTS A (105) RTS B DTR A (108) DTR B DCD A (109) DCD B DSR A (107) CTS A (106) DSR B CTS B DB-25 CONNECTOR 9 1344 TA01 1 LTC1344 U W U U W W W ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER I FOR ATIO (Note 1) Positive Supply Voltage (VCC) ................................... 7V Negative Supply Voltage (VEE) ........................... – 13.2V Input Voltage (Logic Inputs) .... VEE – 0.3V to VCC + 0.3V Input Voltage (Load Inputs) .................................. ±18V Operating Temperature Range LTC1344C ............................................... 0°C to 70°C LTC1344I ........................................... – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C TOP VIEW M0 1 24 M1 VEE 2 23 M2 R1C 3 22 DCE/DTE R1B 4 21 LATCH R1A 5 20 R6B R2A 6 19 R6A R2B 7 18 R5A R2C 8 17 R5B R3A 9 16 R4A R3B 10 15 R4B R3C 11 14 VCC GND 12 13 GND ORDER PART NUMBER LTC1344CG LTC1344IG G PACKAGE 24-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 100°C/W Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°. VCC = 5V ±5%, VEE = –5V ±5%, TA = TMIN to TMAX (Notes 2, 3) unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Current All Digital Pins = GND or VCC ● 200 700 µA All Loads (Figure 1), – 2V ≤ VCM ≤ 2V (Commercial) All Loads (Figure 2), – 2V ≤ VCM ≤ 2V (Commercial) ● ● 90 135 103 153 110 165 Ω Ω All Loads (Figure 1), – 2V ≤ VCM ≤ 2V (Industrial) All Loads (Figure 2), – 2V ≤ VCM ≤ 2V (Industrial) ● ● 90 130 104 153 125 170 Ω Ω All Loads (Figure 1), – 7V ≤ VCM ≤ 7V (Commercial) All Loads (Figure 1), VCM = 0V (Commercial) ● 100 100 104 104 110 Ω Ω All Loads (Figure 1), VCM = 0V (Industrial) ● 95 104 125 Ω All Loads, – 7V ≤ VCM ≤ 7V (Commercial) ● ±1 ±50 µA Supplies ICC Terminator Pins RV.35 RV.11 ILEAK Differential Mode Impedance Common Mode Impedance Differential Mode Impedance High Impedance Leakage Current Logic Inputs VIH Input High Voltage All Logic Input Pins ● VIL Input Low Voltage All Logic Input Pins ● 0.8 V IIN Input Current All Logic Input Pins ● ±10 µA Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are reference to ground unless otherwise specified. 2 2 V Note 3: All typicals are given at VCC = 5V, VEE = – 5V, TA = 25°C. LTC1344 U W TYPICAL PERFORMANCE CHARACTERISTICS V.11 or V.35 Differential Mode Impedance vs Supply Voltage (VCC) V.11 or V.35 Differential Mode Impedance vs Common Mode Voltage V.11 or V.35 Differential Mode Impedance vs Temperature 105 115 VCM = –2V 110 VCM = 0V 105 VCM = 7V 100 –40 –20 0 20 40 60 80 108 106 104 102 100 100 DIFFERENTIAL MODE IMPEDANCE (Ω) VCM = –7V DIFFERENTIAL MODE IMPEDANCE (Ω) –6 TEMPERATURE (°C) – 4 –2 0 2 4 6 COMMON MODE VOLTAGE (V) 1344 G01 COMMON MODE IMPEDANCE (Ω) DIFFERENTIAL MODE IMPEDANCE (Ω) 158 160 VCM = –2V 155 VCM = 0V 150 VCM = 2V 145 – 40 –20 103 – 5.2 – 5.0 – 4.8 VEE VOLTAGE (V) – 4.6 60 40 20 TEMPERATURE (°C) 0 1344 G04 80 156 154 152 150 –2 100 0 –1 1 COMMON MODE VOLTAGE (V) 1344 G05 Supply Current vs Temperature 154 310 290 153 SUPPLY CURRENT (µA) COMMON MODE IMPEDANCE (Ω) 153 2 1344 G06 V.35 Common Mode Inpedance vs Negative Supply Voltage (VEE) V.35 Common Mode Impedance vs Supply Voltage (VCC) 152 5.4 V.35 Common Mode Impedance vs Common Mode Voltage 165 – 5.4 4.8 5.0 5.2 VCC VOLTAGE (V) 1344 G03 V.35 Common Mode Impedance vs Temperature 105 COMMON MODE IMPEDANCE (Ω) 4.6 8 1344 G02 V.11 or V.35 Differential Mode Impedance vs Negative Supply Voltage (VEE) 104 104 103 –8 COMMON MODE IMPEDANCE (Ω) DIFFERENTIAL MODE IMPEDANCE (Ω) 120 152 151 270 250 230 210 190 170 151 4.6 4.8 5.0 5.2 VCC VOLTAGE (V) 5.4 1344 G07 150 – 5.4 – 5.2 – 4.8 – 5.0 VEE VOLTAGE (V) – 4.6 1344 G08 150 –50 –20 10 40 TEMPERATURE (°C) 70 100 1344 G09 3 LTC1344 U U U PIN FUNCTIONS M0 (Pin 1): TTL Level Mode Select Input. The data on M0 is latched when LATCH is high. R4B (Pin 15): Load 4 Node B. VEE (Pin 2): Negative Supply Voltage Input. Can connect directly to the LTC1343 VEE pin. R5B (Pin 17): Load 5 Node B. R1C (Pin 3): Load 1 Center Tap. R4A (Pin 16): Load 4 Node A. R5A (Pin 18): Load 5 Node A. R6A (Pin 19): Load 6 Node A. R1B (Pin 4): Load 1 Node B. R6B (Pin 20): Load 6 Node B. R1A (Pin 5): Load 1 Node A. LATCH (Pin 21): TTL Level Logic Signal Latch Input. When it is low the input buffers on M0, M1, M2 and DCE/DTE are transparent. When it is high the logic pins are latched into their respective input buffers. The data latch allows the select lines to be shared between multiple I/O ports. R2A (Pin 6): Load 2 Node A. R2B (Pin 7): Load 2 Node B. R2C (Pin 8): Load 2 Center Tap. R3A (Pin 9): Load 3 Node A. DCE/DTE (Pin 22): TTL Level Mode Select Input. The DCE mode is selected when it is high and DTE mode when low. The data on DCE/DTE is latched when LATCH is high. R2B (Pin 10): Load 2 Node B. R3C (Pin 11): Load 3 Center Tap. GND (Pin 12): Ground Connection for Load 1 to Load 3. GND (Pin 13): Ground Connection for Load 4 to Load 6. VCC (Pin 14): Positive Supply Input. 4.75V ≤ VCC ≤ 5.25V. M2 (Pin 23): TTL Level Mode Select Input 1. The data on M2 is latched when LATCH is high. M1 (Pin 24): TTL Level Mode Select Input 2. The data on M1 is latched when LATCH is high. TEST CIRCUITS A R1 51.5Ω S1 ON Ω S2 OFF R1 51.5Ω C S1 ON R3 124Ω S2 ON C R3 124Ω A, B R2 51.5Ω B V ±7V OR ±2V V 1344 F01 Figure 1. Differential V.11 or V.35 Impedance Measurement 4 R2 51.5Ω Ω ±2V 1344 F02 Figure 2. V.35 Common Mode Impedance Measurement LTC1344 W U ODE SELECTIO LTC1344 MODE NAME DCE/DTE M2 M1 M0 R1 R2 R3 R4 R5 R6 V.10/RS423 X 0 0 0 Z Z Z Z Z Z RS530A 0 1 0 0 0 0 1 1 Z Z Z Z Z Z V.11 Z V.11 V.11 V.11 V.11 Reserved 0 1 0 0 1 1 0 0 Z V.11 Z V.11 Z V.11 V.11 Z V.11 Z V.11 Z X.21 0 1 0 0 1 1 1 1 Z Z Z Z Z Z V.11 Z V.11 V.11 V.11 V.11 V.35 0 1 1 1 0 0 0 0 V.35 V.35 V.35 V.35 Z V.35 V.35 Z V.35 V.35 V.35 V.35 RS530/RS449/V.36 0 1 1 1 0 0 1 1 Z Z Z Z Z Z V.11 Z V.11 V.11 V.11 V.11 V.28/RS232 X 1 1 0 Z Z Z Z Z Z No Cable X 1 1 1 V.11 V.11 V.11 V.11 V.11 V.11 X = don’t care, 0 = logic low, 1 = logic high A A R1 51.5Ω S1 ON A R1 51.5Ω C S2 OFF S1 ON R3 124Ω R2 51.5Ω B R1 51.5Ω C S2 ON R2 51.5Ω B V.11 Mode S1 OFF R3 124Ω C S2 OFF R2 51.5Ω B V.35 Mode R3 124Ω 1344 F03 Hi-Z Mode Figure 3. LTC1344 Modes 5 LTC1344 U W U U APPLICATIONS INFORMATION Multiprotocol Cable Termination GENERATOR One of the most difficult problems facing the designer of a multiprotocol serial interface is how to allow the transmitters and receivers for different electrical standards to share connector pins. In some cases the transmitters and receivers for each interface standard can be simply tied together and the appropriate circuitry enabled. But the biggest problem still remains: how to switch the various cable terminations required by the different standards. V.10 (RS423) Termination A typical V.10 unbalanced interface is shown in Figure 4. A V.10 single-ended generator output A with ground C is connected to a differential receiver with inputs A' connected to A and input B' connected to the signal return ground C. The receiver’s ground C' is separate from the signal return. Usually no cable termination is required for V.10 interfaces but the receiver inputs must be compliant with the impedance curve shown in Figure 5. In V.10 mode, both switches S1 and S2 are turned off so the only cable termination is the input impedance of the V.10 receiver. 6 LOAD CABLE TERMINATION RECEIVER A' A C B' C' 1344 F04 Figure 4. Typical V.10 Interface A Traditional implementations have included switching resistors with expensive relays or requiring the user to change termination modules every time the interface standard has changed. Custom cables have been used with the termination in the cable head or separate terminations are built on the board, and a custom cable routes the signals to the appropriate termination. Switching the terminations using FETs is difficult because the FETs must remain off even though the signal voltage is beyond the supply voltage for the FET drivers or the power is off. The LTC1344 solves the cable termination switching problem via software control. The LTC1344 provides termination for the V.10 (RS423), V.11 (RS422), V.28 (RS232) and V.35 electrical protocols. BALANCED INTERCONNECTING CABLE 51.5Ω S1 OFF S2 OFF V.10 RECEIVER LTC1344 Z 124Ω Z 51.5Ω B C IZ 3.25mA –10V –3V Z 3V – 3.25mA VZ 10V 1344 F05 Figure 5. V.10 Interface Using the LTC1344 V.11 (RS422) Termination A typical V.11 balanced interface is shown in Figure 6. A V.11 differential generator with outputs A and B with ground C is connected to a differential receiver with ground C', inputs A' connected to A, B' connected to B. The V.11 interface requires a different termination at the receiver end that has a minimum value of 100Ω. The receiver inputs must also be compliant with the impedance curve shown in Figure 7. In V.11 mode, switch S1 is turned on and S2 is turned off so the cable is terminated with a 103Ω impedance. LTC1344 U U W U APPLICATIONS INFORMATION BALANCED INTERCONNECTING CABLE GENERATOR LOAD GENERATOR BALANCED INTERCONNECTING CABLE CABLE TERMINATION RECEIVER A A' B B' C C' LOAD CABLE TERMINATION RECEIVER 100Ω MIN A A' C C' 1344 F08 1344 F06 Figure 8. Typical V.28 Interface Figure 6. Typical V.11 Interface A A 51.5Ω S1 ON S2 OFF V.11 RECEIVER LTC1344 51.5Ω S1 OFF Z 124Ω S2 OFF V.28 RECEIVER LTC1344 124Ω 5k Z 51.5Ω 51.5Ω B B C C IZ 3.25mA –10V 1344 F09 Figure 9. V.28 Interface Using the LTC1344 –3V Z 3V – 3.25mA VZ 10V 1344 F07 Figure 7. V.11 Interface Using the LTC1344 V.28 (RS232) Termination A typical V.28 unbalanced interface is shown in Figure 8. A V.28 single-ended generator output A with ground C is connected to a single-ended receiver with inputs A' connected to A, ground C' connected via the signal return ground to C. The V.28 standard requires a 5k terminating resistor to ground which is included in almost all compliant receivers as shown in Figure 9. Because the termination is included in the receiver, both switches S1 and S2 in the LTC1344 are turned off. V.35 Termination A typical V.35 balanced interface is shown in Figure 10. A V.35 differential generator with outputs A and B with ground C is connected to a differential receiver with ground C', inputs A' connected to A, B' connected to B. The V.35 interface requires a T-network termination at the receiver end and the generator end. In V.35 mode both switches S1 and S2 in the LTC1344 are turned on as shown in Figure 11. The differential impedance measured at the connector must be 100Ω ±10Ω and the impedance between shorted terminals A' and B' to ground C' must be 150Ω ±15Ω. The input impedance of the V.35 receiver is connected in parallel with the T-network inside the LTC1344, which can cause the overall impedance to fail the specification on the 7 LTC1344 U U W U APPLICATIONS INFORMATION A BALANCED INTERCONNECTING CABLE GENERATOR LOAD V.35 DRIVER CABLE TERMINATION RECEIVER 50Ω 124Ω A' A 125Ω 125Ω 50Ω B B' C C' 50Ω S2 ON S2 ON S1 ON B 50Ω C1 100pF 1344 F10 C 1344 F12 Figure 12. V.35 Driver Using the LTC1344 A S1 ON 51.5Ω 51.5Ω Figure 10. Typical V.35 Interface 51.5Ω LTC1344 Z and B to ground C must be 150Ω ±15Ω. For the generator termination, switches S1 and S2 are both on and the top side of the center resistor is brought out to a pin so it can be bypassed with an external capacitor to reduce common mode noise as shown in Figure 12. 3V Any mismatch in the driver rise and fall times or skew in the driver propagation delays will force current through the center termination resistor to ground causing a high frequency common mode spike on the A and B terminals. The common mode spike can cause EMI problems that are reduced by capacitor C1 which shunts much of the common mode energy to ground rather than down the cable. V.35 RECEIVER LTC1344 Z 124Ω 51.5Ω B C IZ 1mA –7V –3V Z –0.8mA VZ 12V 1344 F11 Figure 11. V.35 Receiver Using the LTC1344 low side. However, all of Linear Technology’s V.35 receivers meet the RS485 input impedance specification as shown in Figure 11, which insures compliance with the V.35 specification when used with the LTC1344. The generator differential impedance must be 50Ω to 150Ω and the impedance between shorted terminals A 8 The LATCH Pin The LATCH pin (21) allows the select lines (M0, M1, M2 and DCE/DTE) to be shared with multiple LTC1344s, each with its own LATCH signal. When the LATCH pin is held low the select line input buffers are transparent. When the LATCH pin is pulled high, the select line input buffers latch the state of the Select pins so that changes on the select lines are ignored until LATCH is pulled low again. If the latch feature is not used, the LATCH pin should be tied to ground. LTC1344 U TYPICAL APPLICATIONS N Figure 13 shows a typical application for the LTC1344 using the LTC1343 mixed mode transceiver chip to generate the clock and data signals for a serial interface. The LTC1344 VEE supply is generated from the LTC1343 charge pump and the select lines M0, M1, M2, DCE and LATCH are shared by both chips. Each driver output and receiver input is connected to one of the LTC1344 termination ports. Each electrical protocol can then be chosen using the digital select lines. 100pF 100pF 100pF 8 3 M1 M2 DCE/DTE LATCH 24 23 22 21 11 12 13 9 10 16 15 18 M0 M1 M2 LTC1344 DCE/DTE LATCH VCC VEE 14 5V C1 1µF 17 18 19 21 22 3 5 2 8 LTC1343 M0 M1 M2 DCE/DTE LATCH + M0 1 42 4 6 7 17 19 20 C2 3.3µF 38 DTE TXD+ DCE RXD+ 37 TXD– RXD– SCTE + TXC+ 6 36 7 35 34 SCTE – TXC – NC RXC + NC RXC – 9 33 32 13 31 30 RXC + NC – RXC TXC + NC SCTE+ 29 28 TXC – RXD+ SCTE – TXD+ 27 RXD– TXD– 14 15 1344 F13 Figure 13. Typical Application Using the LTC1344 9 LTC1344 U TYPICAL APPLICATIONS N Controller Selectable Multiprotocol DTE Port with DB-25 Connector C6 100pF C7 100pF 3 C8 100pF 8 11 12 13 LTC1344 VCC 5V 14 1 2 4 3 C5 1µF 41 8 D2 7 DTE_SCT/DEC_RXC D3 9 D4 10 12 13 DTE_TXC/DCE_TXC R1 14 DTE_RXC/DCE_SCTE R2 15 DTE_RXD/DCE_TXD DTE_TM/DCE_LL R1 100k 3 VCC C12 1µF 6 DTE_RTS/DCE_CTS 7 DTE_DTR/DCE_DSR 9 10 12 13 DTE_DCD/DCE_DCD 38 37 36 D2 D3 35 34 33 D4 R2 R3 28 27 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 21 DCE 19 M2 18 M1 17 M0 15 DTE_CTS/DCE_RTS 39 D1 32 31 30 29 14 DTE_DSR/DCE_DTR R1 16 VCC LATCH R2 100k LB DCE/DTE M2 M1 M0 10 16 15 18 17 19 20 22 23 24 1 DTE LL A TXC A TXC B RXC A RXC B RXD A RXD B 25 TM A VCC C10 1µF 7 1 DCE TM A RXD A RXD B RXC A RXC B TXC A TXC B SCTE A SCTE B TXD A TXD B LL A SGND SHIELD C13 3.3µF LTC1343 5 DTE_RL/DCE_RL 24 41 8 10 15 12 17 9 3 16 43 42 CHARGE PUMP 9 32 31 30 29 28 44 4 7 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B 27 2 C9 1µF 6 38 37 36 35 34 33 26 21 DCE 19 M2 18 M1 17 M0 1 C11 1µF 4 18 R3 EC DB-25 CONNECTOR 39 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 40 GND 23 LB 21 DCE/ DTE M2 M1 M0 5 D1 6 DTE_TXD/DCE_RXD 2 VEE C4 3.3µF LTC1343 5 DTE_LL/DCE_TM 43 42 CHARGE PUMP + C1 1µF LATCH C2 1µF + C3 1µF VCC 44 40 GND 23 LB 21 RL A 4 RTS A 19 RTS B 20 DTR A 23 DTR B 8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B RL A CTS A CTS B DSR A DSR B DCD A DCD B DTR A DTR B RTS A RTS B 26 EC 24 1344 TA02 LTC1344 U TYPICAL APPLICATIONS N Cable Selectable Multiprotocol DTE Port with DB-25 Connector C6 100pF C7 100pF 3 C8 100pF 8 12 13 11 LTC1344 VCC 5V 14 1 2 4 3 C5 1µF 41 8 D4 10 12 13 DTE_TXC/DCE_TXC R3 32 31 30 29 28 27 16 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 26 21 DCE 19 M2 18 M1 17 M0 R1 14 DTE_RXC/DCE_SCTE R2 15 DTE_RXD/DCE_TXD R1 100k 40 GND 23 LB C11 1µF C9 1µF C12 1µF 44 43 42 CHARGE PUMP 41 8 6 7 DTE_DTR/DCE_DSR 9 10 12 13 DTE_DCD/DCE_DCD R2 100k LB D3 10 16 15 18 17 19 20 22 D4 28 27 R4 20 CTRL 22 LATCH 11 INVERT 25 423 SET 26 21 DCE 19 M2 18 M1 17 M0 40 GND 23 LB 23 24 1 VCC DTE 2 TXD A 14 TXD B 24 SCTE A 11 SCTE B 15 12 17 9 3 16 TXC A TXC B RXC A RXC B RXD A RXD B 7 DCE RXD A RXD B RXC A RXC B TXC A TXC B SCTE A SCTE B TXD A TXD B SGND VCC 1 SHIELD VCC C10 1µF VCC R3 10k VCC R4 10k VCC R5 10k 25 C13 3.3µF 21 18 DCE/DTE M1 M0 4 RTS A 19 RTS B 20 DTR A 23 DTR B 35 34 33 R3 16 VCC 9 38 37 36 D2 R2 15 DTE_CTS/ DCE_RTS 7 39 D1 32 31 30 29 14 DTE_DSR/DCE_DTR 6 LTC1343 5 DTE_RTS/DCE_CTS 24 1 3 VCC EC 2 4 4 38 37 36 35 34 33 D3 9 DB-25 CONNECTOR DCE/ DTE M2 M1 M0 5 D2 7 21 39 D1 6 DTE_SCTE/DEC_RXC 2 VEE C4 3.3µF LTC1343 5 DTE_TXD/DCE_RXD 43 42 CHARGE PUMP + C1 1µF LATCH C2 1µF + C3 1µF VCC 44 R1 24 EC 8 DCD A 10 DCD B 6 DSR A 22 DSR B 5 CTS A 13 CTS B CTS A CTS B DSR A DSR B DCD A DCD B DTR A DTR B RTS A RTS B 1344 TA03 VCC CABLE WIRING FOR MODE SELECTION MODE PIN 18 PIN 21 V.35 PIN 7 PIN 7 EIA-530, RS449, NC PIN 7 V.36, X.21 RS232 PIN 7 NC CABLE WIRING FOR DTE/DCE SELECTION MODE PIN 25 DTE PIN 7 DCE NC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 LTC1344 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. G Package 24-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 8.07 – 8.33* (0.318 – 0.328) 24 23 22 21 20 19 18 17 16 15 14 13 7.65 – 7.90 (0.301 – 0.311) 1 2 3 4 5 6 7 8 9 10 11 12 5.20 – 5.38** (0.205 – 0.212) 1.73 – 1.99 (0.068 – 0.078) 0° – 8° 0.13 – 0.22 (0.005 – 0.009) 0.55 – 0.95 (0.022 – 0.037) NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE 0.65 (0.0256) BSC 0.05 – 0.21 (0.002 – 0.008) 0.25 – 0.38 (0.010 – 0.015) G24 SSOP 1098 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1334 Single Supply RS232/RS485 Transceiver 2 RS485 Dr/Rx or 4 RS232 Dr/Rx Pairs LTC1343 Multiprotocol Serial Transceiver Software Selectable Mulitprotocol Interface LTC1345 Single Supply V.35 Transceiver 3 Dr/3 Rx for Data and CLK Signals LTC1346A Dual Supply V.35 Transceiver 3 Dr/3 Rx for Data and CLK Signals LTC1344A Multiprotocol Cable Terminator, Pin Compatible to LTC1344 Allows Separate RS449 Mode LTC1543 Multiprotocol Serial Transceiver 3 Dr/3 Rx for Data and CLK Signals LTC1544 Multiprotocol Serial Transceiver 4 Dr/4 Rx for Control Signals and LL LTC1545 Multiprotocol Serial Transceiver 5 Dr/5 Rx for Control Signals, LL, RL amd TM 12 Linear Technology Corporation 1344fa LT/TP 0300 2K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com  LINEAR TECHNOLOGY CORPORATION 1996