LTC1608ACG#TRPBF

LTC1608 High Speed, 16-Bit, 500ksps Sampling A/D Converter with Shutdown U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO A Complete, 500ksps 16-Bit ADC 90dB S/(N+D) and –100dB THD (Typ) Power Dissipation: 270mW (Typ) No Pipeline Delay No Missing Codes Over Temperature Nap (7mW) and Sleep (10µW) Shutdown Modes Operates with Internal 15ppm/°C Reference or External Reference True Differential Inputs Reject Common Mode Noise 5MHz Full Power Bandwidth ±2.5V Bipolar Input Range 36-Pin SSOP Package Pin Compatible with the LTC1604 The LTC®1608 is a 500ksps, 16-bit sampling A/D converter that draws only 270mW from ±5V supplies. This high performance device includes a high dynamic range sample-and-hold, a precision reference and a high speed parallel output. Two digitally selectable power shutdown modes provide power savings for low power systems. Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems The ADC has µP compatible,16-bit parallel output port. There is no pipeline delay in conversion results. A separate convert start input and a data ready signal (BUSY) ease connections to FlFOs, DSPs and microprocessors. The LTC1608’s full-scale input range is ± 2.5V. Outstanding AC performance includes 90dB S/(N+D) and – 100dB THD at a sample rate of 500ksps. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 15MHz bandwidth. The 68dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. U APPLICATIO S ■ ■ ■ ■ ■ ■ , LTC and LT are registered trademarks of Linear Technology Corporation. Circuitry in the LTC1608 is covered under US Patent #5,764,175 U TYPICAL APPLICATIO 10µF 2.2µF 10Ω + 3 VREF 5V 10µF + 36 AVDD 5V 35 9 AVDD 10µF + 10 DVDD LTC1608 4096 Point FFT DGND SHDN 33 4 REFCOMP 7.5k 1.75X + CONTROL LOGIC AND TIMING 2.5V REF 0 CONVST 31 RD 30 OVDD 29 + + 1 AIN DIFFERENTIAL ANALOG INPUT ± 2.5V – 2 AIN + – OGND 28 16-BIT SAMPLING ADC AGND 5 AGND 6 OUTPUT BUFFERS B15 TO B0 AGND 7 8 16-BIT PARALLEL BUS 1608 TA01 34 + 10µF 5V OR 3V 10µF –40 –60 –80 –100 D15 TO D0 11 TO 26 AGND VSS –20 µP CONTROL LINES BUSY 27 22µF fSAMPLE = 500kHz fIN = 98.754kHz SINAD = 86.7dB THD = –92.6dB CS 32 AMPLITUDE (dB) LTC1608 –120 –140 0 50 100 150 FREQUENCY (kHz) 200 250 1608 TA02 –5V 1 LTC1608 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO AVDD = DVDD = OVDD = VDD (Notes 1, 2) ORDER PART NUMBER TOP VIEW Supply Voltage (VDD) ................................................ 6V Negative Supply Voltage (VSS) ............................... – 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V) VREF Voltage (Note 4) ................. – 0.3V to (VDD + 0.3V) REFCOMP Voltage (Note 4) ......... – 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) ....................– 0.3V to 10V Digital Output Voltage .................. – 0.3V to (VDD + 0.3V) Power Dissipation ............................................. 500mW Operating Temperature Range LTC1608C .............................................. 0°C to 70°C LTC1608I ............................................ – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C AIN+ 1 AIN– 2 36 AVDD 35 AVDD VREF 3 34 VSS REFCOMP 4 33 SHDN AGND 5 32 CS AGND 6 31 CONV AGND 7 30 RD AGND 8 29 OVDD DVDD 9 28 OGND DGND 10 27 BUSY D15 (MSB) 11 26 D0 D14 12 25 D1 D13 13 24 D2 D12 14 23 D3 D11 15 22 D4 D10 16 21 D5 D9 17 20 D6 D8 18 LTC1608CG LTC1608ACG LTC1608IG LTC1608AIG 19 D7 G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 95°C/W Consult factory for parts specified with wider operating temperature ranges. U CO VERTER CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6), unless otherwise noted. PARAMETER CONDITIONS MIN Resolution (No Missing Codes) Integral Linearity Error 15 ● (Note 7) (Note 8) Offset Error (Note 9) Offset Tempco (Note 9) Full-Scale Error Internal Reference External Reference Full-Scale Tempco IOUT(Reference) = 0, Internal Reference U U A ALOG I PUT MIN 16 ±1 ● Transition Noise LTC1608 TYP MAX 16 ±4 16 ±0.5 0.7 ±2 0.5 ± 0.125 ± 0.25 ±0.25 % FSR ppm/°C ±0.125 ±0.25 ±0.25 ±15 LSB LSBRMS ±0.05 ±0.125 0.5 UNITS Bits 0.7 ± 0.05 ± 0.125 ● LTC1608A TYP MAX ±15 % % ppm/°C The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS VIN Analog Input Range (Note 2) 4.75 ≤ VDD ≤ 5.25V, – 5.25 ≤ VSS ≤ – 4.75V, VSS ≤ (AIN–, AIN+) ≤ AVDD IIN Analog Input Leakage Current CS = High CIN Analog Input Capacitance Between Conversions During Conversions tACQ tAP tjitter Sample-and-Hold Acquisition Delay Time Jitter CMRR 2 MIN TYP MAX ±2.5 V ±1 ● UNITS µA 43 5 pF pF Sample-and-Hold Acquisition Time 380 ns Sample-and-Hold Acquisition Delay Time – 1.5 ns Analog Input Common Mode Rejection Ratio – 2.5V < (AIN– = AIN +) < 2.5V 5 psRMS 68 dB LTC1608 W U DY A IC ACCURACY TA = 25°C (Note 5) SYMBOL PARAMETER CONDITIONS MIN S/N Signal-to-Noise Ratio 5kHz Input Signal 100kHz Input Signal 90 88 dB dB S/(N + D) Signal-to-(Noise + Distortion) Ratio 5kHz Input Signal 100kHz Input Signal (Note 10) 90 84 dB dB THD Total Harmonic Distortion Up to 5th Harmonic 5kHz Input Signal 100kHz Input Signal – 100 – 91 dB dB SFDR Spurious Free Dynamic Range 100kHz Input Signal 94 dB IMD Intermodulation Distortion fIN1 = 29.37kHz, fIN2 = 32.446kHz – 88 Full Power Bandwidth Full Linear Bandwidth (S/(N + D) ≥ 84dB) U U U I TER AL REFERE CE CHARACTERISTICS PARAMETER TYP MAX UNITS dB 5 MHz 350 kHz TA = 25°C (Note 5) CONDITIONS MIN TYP MAX UNITS VREF Output Voltage IOUT = 0 2.475 2.500 2.515 VREF Output Tempco IOUT = 0 ±15 ppm/°C VREF Line Regulation 4.75 ≤ VDD ≤ 5.25V – 5.25V ≤ VSS ≤ – 4.75V 0.01 0.01 LSB/V LSB/V VREF Output Resistance 0 ≤ IOUT ≤ 1mA 7.5 kΩ REFCOMP Output Voltage IOUT = 0 V 4.375 V U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER VIH High Level Input Voltage VDD = 5.25V ● VIL Low Level Input Voltage VDD = 4.75V ● 0.8 V IIN Digital Input Current VIN = 0V to VDD ● ±1 0 µA CIN Digital Input Capacitance VOH High Level Output Voltage VOL Low Level Output Voltage CONDITIONS MIN VDD = 4.75V, IOUT = – 10µA VDD = 4.75V, IOUT = – 400µA ● VDD = 4.75V, IOUT = 160µA VDD = 4.75V, IOUT = 1.6mA ● VOUT = 0V to VDD, CS High ● ● TYP MAX 2.4 UNITS V 5 pF 4.5 V V 4.0 0.05 0.10 0.4 V V ±10 µA IOZ Hi-Z Output Leakage D15 to D0 COZ Hi-Z Output Capacitance D15 to D0 CS High (Note 11) ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = VDD 10 mA 15 pF 3 LTC1608 U W POWER REQUIRE E TS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS VDD Positive Supply Voltage (Notes 12, 13) VSS Negative Supply Voltage (Note 12) IDD Positive Supply Current Nap Mode Sleep Mode CS = RD = 0V CS = 0V, SHDN = 0V CS = 5V, SHDN = 0V ● 22 1.5 1 35 2.4 100 mA mA µA ISS Negative Supply Current Nap Mode Sleep Mode CS = RD = 0V CS = 0V, SHDN = 0V CS = 5V, SHDN = 0V ● 32 1 1 49 100 100 mA µA µA PD Power Dissipation Nap Mode Sleep Mode CS = RD = 0V CS = 0V, SHDN = 0V CS = 5V, SHDN = 0V ● 270 7.5 0.01 420 12 1 mW mW mW WU TI I G CHARACTERISTICS MIN TYP MAX UNITS 4.75 5.25 V – 4.75 – 5.25 V The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN fSMPL(MAX) Maximum Sampling Frequency ● 500 600 tCONV Conversion Time ● 1.0 1.45 tACQ Acquisition Time (Notes 11, 14) TYP ● tACQ+CONV(MIN) Throughput Time (Acquisition + Conversion) 1.67 ● MAX UNITS kHz 1.8 µs 400 ns 2 µs t1 CS to RD Setup Time (Notes 11, 12, 15) ● 0 ns t2 CS↓ to CONVST↓ Setup Time (Notes 11, 12) ● 10 ns t3 SHDN↓ to CS↑ Setup Time (Notes 11, 12) ● 10 t4 SHDN↑ to CONVST↓ Wake-Up Time CS = Low (Note 12) t5 CONVST Low Time (Note 12) t6 CONVST to BUSY Delay CL = 25pF ns 400 ● 40 ns 36 80 ● t7 ns Data Ready Before BUSY↑ 60 ns ns ● 32 ns ns t8 Delay Between Conversions (Note 12) ● 200 ns t9 Wait Time RD↓ After BUSY↑ (Note 12) ● –5 ns t10 Data Access Time After RD↓ CL = 25pF 25 40 50 ns ns 45 60 75 ns ns 30 50 60 ns ns ● CL = 100pF (Note 11) ● t11 Bus Relinquish Time ● t12 RD Low Time (Note 12) ● t10 t13 CONVST High Time (Note 12) ● 40 t14 Aperture Delay of Sample-and-Hold Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, OGND and AGND wired together unless otherwise noted. 4 ns ns 2 ns Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. LTC1608 ELECTRICAL CHARACTERISTICS Note 4: When these pin voltages are taken below VSS, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = – 5V, fSMPL = 500kHz, and t r = t f = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specification apply for a singleended AIN+ input with AIN– grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Typical RMS noise at the code transitions. Note 9: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion is measured at 100kHz. These results are used to calculate Signal-to-Nosie Plus Distortion (SINAD). Note 11: Guaranteed by design, not subject to test. Note 12: Recommended operating conditions. Note 13: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best performance ensure that CONVST returns high either within 250ns after conversion start or after BUSY rises. Note 14: The acquisition time would go up to 400ns and the conversion time would go up to 1.8µs. However, the throughput time (acquisition + conversion) is guaranteed by test to be 2µs max. Note 15: If RD↓ precedes CS↓, the output enable will be gated by CS↓. U W TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity vs Output Code Differential Nonlinearity vs Output Code 1.5 0.5 DNL (LSB) 0 –0.5 –1.0 –1.5 –2.0 –32768 –16384 0 CODE 16384 100 90 0.6 80 0.4 70 0.2 0 –0.2 20 –0.8 10 0 CODE 16384 Signal-to-Noise Ratio vs Input Frequency AMPLITUDE (dB BELOW THE FUNDAMENTAL) SIGNAL-TO-NOISE RATIO (dB) 80 70 60 50 40 30 20 10 10k 100k FREQUENCY (Hz) 1M 1608 G04 10k 100k FREQUENCY (Hz) Spurious-Free Dynamic Range vs Input Frequency 0 0 –10 –20 –30 –40 –50 –60 –70 –80 THD 3RD 2ND –90 –100 –110 1k 1M 1608 G03 Distortion vs Input Frequency 90 0 1k 0 1k 32767 1608 G02 1608 G01 100 VIN = –40dB 40 30 –16384 VIN = –20dB 50 –0.6 –1.0 –32768 32767 VIN = 0dB 60 –0.4 10k 100k INPUT FREQUENCY (Hz) 1M 1608 G05 SPURIOUS-FREE DYNAMIC RANGE (dB) INL (LSB) 1.0 1.0 0.8 SINAD (dB) 2.0 S/(N + D) vs Input Frequency and Amplitude –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1608 G06 5 LTC1608 U W TYPICAL PERFOR A CE CHARACTERISTICS Power Supply Feedthrough vs Ripple Frequency fSAMPLE = 500kHz fIN1 = 96.56kHz fIN2 = 99.98kHz AMPLITUDE (dB) –20 –40 –60 –80 AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB) 0 0 –20 Input Common Mode Rejection vs Input Frequency 80 fSAMPLE = 500kHz VRIPPLE = 10mV COMMON MODE REJECTION (dB) Intermodulation Distortion –40 –60 –80 –100 –100 AVDD –120 –120 V SS –140 –140 0 50 100 150 200 250 FREQUENCY (kHz) 1k 10k 100k INPUT FREQUENCY (Hz) 1608 G07 1M 70 60 50 40 30 20 10 0 1k 10k 100k INPUT FREQUENCY (Hz) 1608 G08 1M 1608 G14a U U U PI FU CTIO S AIN+ (Pin 1): Positive Analog Input. The ADC converts the difference voltage between AIN+ and AIN– with a differential range of ±2.5V. AIN+ has a ±2.5V input range when AIN– is grounded. AIN– (Pin 2): Negative Analog Input. Can be grounded, tied to a DC voltage or driven differentially with AIN+ . VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with 2.2µF tantalum in parallel with 0.1µF ceramic. REFCOMP (Pin 4): 4.375V (Nominal) Reference Compensation Pin. Bypass to AGND with 22µF tantalum in parallel with 0.1µF ceramic. This is not recommended for use as an external reference due to part-to-part output voltage variations and glitches that occur during the conversion. AGND (Pins 5 to 8): Analog Grounds. Tie to analog ground plane. DVDD (Pin 9): 5V Digital Power Supply. Bypass to DGND with 10µF tantalum in parallel with 0.1µF ceramic. DGND (Pin 10): Digital Ground for Internal Logic. Tie to analog ground plane. D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15 is the Most Significant Bit. BUSY (Pin 27): The BUSY output shows the converter status. It is low when a conversion is in progress. Data is valid on the rising edge of BUSY. 6 OGND (Pin 28): Digital Ground for Output Drivers. OVDD (Pin 29): Digital Power Supply for Output Drivers. Bypass to OGND with 10µF tantalum in parallel with 0.1µF ceramic. RD (Pin 30): Read Input. A logic low enables the output drivers when CS is low. CONVST (Pin 31): Conversion Start Signal. This active low signal starts a conversion on its falling edge when CS is low. CS (Pin 32): The Chip Select Input. Must be low for the ADC to recognize CONVST and RD inputs. SHDN (Pin 33): Power Shutdown. Drive this pin low with CS low for nap mode. Drive this pin low with CS high for sleep mode. VSS (Pin 34): – 5V Negative Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic. AVDD (Pin 35): 5V Analog Power Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic. AVDD (Pin 36): 5V Analog Power Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic and connect this pin to Pin 35 with a 10Ω resistor. LTC1608 W FU CTIO AL BLOCK DIAGRA U 10µF U 2.2µF 10Ω + 3 VREF 5V 10µF + 36 AVDD 5V 35 9 AVDD 10µF + 10 DVDD DGND SHDN 33 4 REFCOMP + 7.5k 1.75X 4.375V CS 32 CONTROL LOGIC AND TIMING 2.5V REF µP CONTROL LINES CONVST 31 RD 30 BUSY 27 22µF OVDD 29 + 1 AIN+ DIFFERENTIAL ANALOG INPUT ±2.5V 2 AIN– OGND 28 + 16-BIT SAMPLING ADC – AGND AGND 6 5 OUTPUT BUFFERS B15 TO B0 AGND 7 D15 TO D0 16-BIT PARALLEL BUS 11 TO 26 AGND VSS 8 5V OR 3V 10µF 34 1608 BD + 10µF –5V TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay 5V 5V 1k DN 1k DN 1k DN 1k CL CL (A) Hi-Z TO VOH AND VOL TO VOH DN (B) Hi-Z TO VOL AND VOH TO VOL 1608 TC01 (A) VOH TO Hi-Z CL CL (B) VOL TO Hi-Z 1608 TC02 U W U U APPLICATIO S I FOR ATIO CONVERSION DETAILS The LTC1608 uses a successive approximation algorithm and internal sample-and-hold circuit to convert an analog signal to a 16-bit parallel output. The ADC is complete with a sample-and-hold, a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion, the successive approximation register (SAR) resets. Once a conversion cycle has begun, it cannot be restarted. During the conversion, the internal differential 16-bit capacitive DAC output is sequenced by the SAR from the Most Significant Bit (MSB) to the Least Significant Bit (LSB). Referring to Figure 1, the AIN+ and AIN– inputs are acquired during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a duration of 480ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. During the convert phase, the comparator zeroing switches open, putting the comparator into compare mode. The input switches connect the CSMPL capacitors to ground, transferring the differential analog input charge onto the summing junctions. This input charge is successively 7 LTC1608 U W U U APPLICATIO S I FOR ATIO 3V Input/Output Compatible CSMPL AIN+ SAMPLE The LTC1608 operates on ±5V supplies, which makes the device easy to interface to 5V digital systems. This device can also talk to 3V digital systems: the digital input pins (SHDN, CS, CONVST and RD) of the LTC1608 recognize 3V or 5V inputs. The LTC1608 has a dedicated output supply pin (OVDD) that controls the output swings of the digital output pins (D0 to D15, BUSY) and allows the part to talk to either 3V or 5V digital systems. The output is two’s complement binary. HOLD ZEROING SWITCHES CSMPL AIN– HOLD SAMPLE HOLD HOLD +CDAC + –CDAC COMP – +VDAC Power Shutdown –VDAC 16 SAR OUTPUT LATCHES • • • D15 D0 1608 F01 Figure 1. Simplified Block Diagram compared with the binary-weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the AIN+ and AIN– input charges. The SAR contents (a 16-bit data word) which represent the difference of AIN+ and AIN– are loaded into the 16-bit output latches. DIGITAL INTERFACE The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion. The LTC1608 provides two power shutdown modes, Nap and Sleep, to save power during inactive periods. The Nap mode reduces the power by 95% and leaves only the digital logic and reference powered up. The wake-up time from Nap to active is 200ns. In Sleep mode, all bias currents are shut down and only leakage current remains (about 1µA). Wake-up time from Sleep mode is much longer since the reference circuit must power up and settle. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 80ms with the recommended 22µF capacitor. Shutdown is controlled by Pin 33 (SHDN). The ADC is in shutdown when SHDN is low. The shutdown mode is selected with Pin 32 (CS). When SHDN is low, CS low selects nap and CS high selects sleep. SHDN t3 CS 1608 F02a Internal Clock The A/D converter has an internal clock that runs the A/D conversion. The internal clock is factory trimmed to achieve a typical conversion time of 1.45µs and a maximum conversion time of 1.8µs over the full temperature range. No external adjustments are required. The guaranteed maximum acquisition time is 400ns. In addition, a throughput time (acquisition + conversion) of 2µs and a minimum sampling rate of 500ksps are guaranteed. Figure 2a. Nap Mode to Sleep Mode Timing SHDN t4 CONVST 1608 F02b Figure 2b. SHDN to CONVST Wake-Up Timing 8 LTC1608 U W U U APPLICATIO S I FOR ATIO (e.g., CONVST low time >tCONV), accuracy is unaffected. For best results, keep t 5 less than 500ns or greater than tCONV. CS t2 CONVST Figures 5 through 9 show several different modes of operation. In modes 1a and 1b (Figures 5 and 6), CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. t1 RD 1608 F03 Figure 3. CS top CONVST Setup Timing CHANGE IN DNL (LSB) 4 In mode 2 (Figure 7) CS is tied low. The falling edge of CONVST signal starts the conversion. Data outputs are in three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared data bus. 3 2 tCONV tACQ 1 0 0 250 500 750 1000 1250 1500 1750 2000 CONVST LOW TIME, t5 (ns) 1608 F04 Figure 4. Change in DNL vs CONVST Low Time. Be Sure the CONVST Pulse Returns High Early in the Conversion or After the End of Conversion Timing and Control Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A falling edge applied to the CONVST pin will start a conversion after the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. We recommend using a narrow logic low or narrow logic high CONVST pulse to start a conversion as shown in Figures 5 and 6. A narrow low or high CONVST pulse prevents the rising edge of the CONVST pulse from upsetting the critical bit decisions during the conversion time. Figure 4 shows the change of the differential nonlinearity error versus the low time of the CONVST pulse. As shown, if CONVST returns high early in the conversion (e.g., CONVST low time