LTC1608ACG

LTC1608 High Speed, 16-Bit, 500ksps Sampling A/D Converter with Shutdown FEATURES s s s s s s s DESCRIPTIO s s s s s A Complete, 500ksps 16-Bit ADC 90dB S/(N+D) and –100dB THD (Typ) Power Dissipation: 270mW (Typ) No Pipeline Delay No Missing Codes Over Temperature Nap (7mW) and Sleep (10µW) Shutdown Modes Operates with Internal 15ppm/°C Reference or External Reference True Differential Inputs Reject Common Mode Noise 5MHz Full Power Bandwidth ± 2.5V Bipolar Input Range 36-Pin SSOP Package Pin Compatible with the LTC1604 The LTC®1608 is a 500ksps, 16-bit sampling A/D converter that draws only 270mW from ± 5V supplies. This high performance device includes a high dynamic range sample-and-hold, a precision reference and a high speed parallel output. Two digitally selectable power shutdown modes provide power savings for low power systems. The LTC1608’s full-scale input range is ± 2.5V. Outstanding AC performance includes 90dB S/(N+D) and – 100dB THD at a sample rate of 500ksps. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 15MHz bandwidth. The 68dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The ADC has µP compatible,16-bit parallel output port. There is no pipeline delay in conversion results. A separate convert start input and a data ready signal (BUSY) ease connections to FlFOs, DSPs and microprocessors. , LTC and LT are registered trademarks of Linear Technology Corporation. Circuitry in the LTC1608 is covered under US Patent #5,764,175 APPLICATIO S s s s s s s Telecommunications Digital Signal Processing Multiplexed Data Acquisition Systems High Speed Data Acquisition Spectrum Analysis Imaging Systems TYPICAL APPLICATIO 2.2µF 10µF 10Ω 36 3 VREF 5V 10µF 5V 10µF + 35 AVDD + 9 + 10 DGND SHDN 33 AVDD DVDD LTC1608 4 REFCOMP 22µF 7.5k 1.75X 2.5V REF BUSY 27 OVDD 29 5V OR 3V 10µF AMPLITUDE (dB) + CONTROL LOGIC AND TIMING CS 32 CONVST 31 RD 30 µP CONTROL LINES + 1 AIN DIFFERENTIAL ANALOG INPUT ± 2.5V + – OGND 28 16-BIT SAMPLING ADC AGND 5 AGND 6 B15 TO B0 OUTPUT BUFFERS 16-BIT PARALLEL BUS 11 TO 26 1608 TA01 – 2 AIN D15 TO D0 AGND 7 AGND VSS 8 34 10µF + –5V U LTC1608 4096 Point FFT 0 –20 –40 –60 –80 –100 –120 –140 0 50 100 150 FREQUENCY (kHz) 200 250 1608 TA02 + U U fSAMPLE = 500kHz fIN = 98.754kHz SINAD = 86.7dB THD = –92.6dB 1 LTC1608 ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW AIN+ AIN– VREF REFCOMP AGND AGND AGND AGND DVDD 1 2 3 4 5 6 7 8 9 36 AVDD 35 AVDD 34 VSS 33 SHDN 32 CS 31 CONV 30 RD 29 OVDD 28 OGND 27 BUSY 26 D0 25 D1 24 D2 23 D3 22 D4 21 D5 20 D6 19 D7 G PACKAGE 36-LEAD PLASTIC SSOP AVDD = DVDD = OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................ 6V Negative Supply Voltage (VSS) ............................... – 6V Total Supply Voltage (VDD to VSS) .......................... 12V Analog Input Voltage (Note 3) ......................... (VSS – 0.3V) to (VDD + 0.3V) VREF Voltage (Note 4) ................. – 0.3V to (VDD + 0.3V) REFCOMP Voltage (Note 4) ......... – 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) ....................– 0.3V to 10V Digital Output Voltage .................. – 0.3V to (VDD + 0.3V) Power Dissipation ............................................. 500mW Operating Temperature Range .................... 0°C to 70°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER LTC1608CG LTC1608ACG DGND 10 D15 (MSB) 11 D14 12 D13 13 D12 14 D11 15 D10 16 D9 17 D8 18 TJMAX = 125°C, θJA = 95°C/W Consult factory for parts specified with wider operating temperature ranges. CO VERTER CHARACTERISTICS PARAMETER Resolution (No Missing Codes) Integral Linearity Error Transition Noise Offset Error Offset Tempco Full-Scale Error Full-Scale Tempco (Note 7) (Note 8) (Note 9) (Note 9) Internal Reference External Reference CONDITIONS The q denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. With Internal Reference (Notes 5, 6), unless otherwise noted. MIN q q LTC1608 TYP MAX 16 ±1 0.7 ±4 MIN 16 LTC1608A TYP MAX 16 ± 0.5 0.7 ± 0.05 ± 0.125 0.5 ± 0.125 ± 0.25 ± 0.25 ± 15 ±2 UNITS Bits LSB LSBRMS % FSR ppm/°C % % ppm/°C 15 q ± 0.05 ± 0.125 0.5 ± 0.125 ± 0.25 ± 0.25 ± 15 IOUT(Reference) = 0, Internal Reference A ALOG I PUT SYMBOL PARAMETER VIN IIN CIN tACQ tAP tjitter CMRR specifications are at TA = 25°C. The q denotes specifications that apply over the full operating temperature range, otherwise CONDITIONS 4.75 ≤ VDD ≤ 5.25V, – 5.25 ≤ VSS ≤ – 4.75V, VSS ≤ (AIN–, AIN+) ≤ AVDD CS = High Between Conversions During Conversions q MIN TYP ± 2.5 MAX UNITS V Analog Input Range (Note 2) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Time Jitter Analog Input Common Mode Rejection Ratio ±1 43 5 380 – 1.5 5 psRMS dB – 2.5V < (AIN– = AIN +) < 2.5V 68 2 U µA pF pF ns ns W U U WW W U U U LTC1608 DY A IC ACCURACY SYMBOL S/N S/(N + D) THD SFDR IMD PARAMETER Signal-to-Noise Ratio I TER AL REFERE CE CHARACTERISTICS PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance REFCOMP Output Voltage CONDITIONS IOUT = 0 IOUT = 0 4.75 ≤ VDD ≤ 5.25V – 5.25V ≤ VSS ≤ – 4.75V 0 ≤ IOUT ≤ 1mA IOUT = 0 DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage D15 to D0 Hi-Z Output Capacitance D15 to D0 Output Source Current Output Sink Current CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD The q denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) MIN q q q U U U WU U TA = 25°C (Note 5) CONDITIONS 5kHz Input Signal 100kHz Input Signal 5kHz Input Signal 100kHz Input Signal (Note 10) 5kHz Input Signal 100kHz Input Signal 100kHz Input Signal fIN1 = 29.37kHz, fIN2 = 32.446kHz MIN TYP 90 88 90 84 – 100 – 91 94 – 88 5 350 MAX UNITS dB dB dB dB dB dB dB dB MHz kHz Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Up to 5th Harmonic Spurious Free Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth (S/(N + D) ≥ 84dB) U TA = 25°C (Note 5) MIN 2.475 TYP 2.500 ± 15 0.01 0.01 7.5 4.375 MAX 2.515 UNITS V ppm/°C LSB/V LSB/V kΩ V TYP MAX 0.8 ±1 0 UNITS V V µA pF V V 2.4 5 VDD = 4.75V, IOUT = – 10µA VDD = 4.75V, IOUT = – 400µA VDD = 4.75V, IOUT = 160µA VDD = 4.75V, IOUT = 1.6mA VOUT = 0V to VDD, CS High CS High (Note 11) VOUT = 0V VOUT = VDD 4.5 q q q q 4.0 0.05 0.10 0.4 ± 10 15 –10 10 V V µA pF mA mA 3 LTC1608 POWER REQUIRE E TS SYMBOL VDD VSS IDD PARAMETER Positive Supply Voltage Negative Supply Voltage Positive Supply Current Nap Mode Sleep Mode Negative Supply Current Nap Mode Sleep Mode Power Dissipation Nap Mode Sleep Mode The q denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) CONDITIONS (Notes 12, 13) (Note 12) CS = RD = 0V CS = 0V, SHDN = 0V CS = 5V, SHDN = 0V CS = RD = 0V CS = 0V, SHDN = 0V CS = 5V, SHDN = 0V CS = RD = 0V CS = 0V, SHDN = 0V CS = 5V, SHDN = 0V q ISS PD otherwise specifications are at TA = 25°C. (Note 5) SYMBOL fSMPL(MAX) tCONV tACQ t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time CS to RD Setup Time CS↓ to CONVST↓ Setup Time SHDN↓ to CS↑ Setup Time SHDN↑ to CONVST↓ Wake-Up Time CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY↑ TI I G CHARACTERISTICS tACQ+CONV(MIN) Throughput Time (Acquisition + Conversion) (Notes 11, 12, 15) (Notes 11, 12) (Notes 11, 12) CS = Low (Note 12) (Note 12) CL = 25pF Delay Between Conversions Wait Time RD↓ After BUSY↑ Data Access Time After RD↓ t11 t12 t13 t14 Bus Relinquish Time q RD Low Time CONVST High Time Aperture Delay of Sample-and-Hold Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, OGND and AGND wired together unless otherwise noted. 4 UW MIN 4.75 – 4.75 TYP MAX 5.25 – 5.25 UNITS V V mA mA µA mA µA µA mW mW mW 22 1.5 1 32 1 1 270 7.5 0.01 35 2.4 100 49 100 100 420 12 1 q q UW The q denotes specifications that apply over the full operating temperature range, CONDITIONS q q MIN 500 1.0 TYP 600 1.45 1.67 MAX 1.8 400 2 UNITS kHz µs ns µs ns ns ns (Notes 11, 14) q q q q q 0 10 10 400 40 36 80 60 32 200 –5 25 40 50 60 75 50 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns q q q (Note 12) (Note 12) CL = 25pF q q q CL = 100pF (Note 11) q 45 30 (Note 12) (Note 12) q q t10 40 2 ns Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or above VDD without latchup. LTC1608 ELECTRICAL CHARACTERISTICS Note 4: When these pin voltages are taken below VSS, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = – 5V, fSMPL = 500kHz, and t r = t f = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specification apply for a singleended AIN+ input with AIN– grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Typical RMS noise at the code transitions. Note 9: Bipolar offset is the offset voltage measured from – 0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion is measured at 100kHz. These results are used to calculate Signal-to-Nosie Plus Distortion (SINAD). Note 11: Guaranteed by design, not subject to test. Note 12: Recommended operating conditions. Note 13: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best performance ensure that CONVST returns high either within 250ns after conversion start or after BUSY rises. Note 14: The acquisition time would go up to 400ns and the conversion time would go up to 1.8µs. However, the throughput time (acquisition + conversion) is guaranteed by test to be 2µs max. Note 15: If RD↓ precedes CS↓, the output enable will be gated by CS↓. TYPICAL PERFOR A CE CHARACTERISTICS Integral Nonlinearity vs Output Code 2.0 1.5 1.0 DNL (LSB) INL (LSB) 0.2 0 –0.2 –0.4 SINAD (dB) 0.5 0 –0.5 –1.0 –1.5 –2.0 –32768 –16384 0 CODE 16384 32767 1608 G01 Signal-to-Noise Ratio vs Input Frequency AMPLITUDE (dB BELOW THE FUNDAMENTAL) 100 90 SIGNAL-TO-NOISE RATIO (dB) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 SPURIOUS-FREE DYNAMIC RANGE (dB) 80 70 60 50 40 30 20 10 0 1k 10k 100k FREQUENCY (Hz) 1M 1608 G04 UW Differential Nonlinearity vs Output Code 1.0 0.8 0.6 0.4 100 90 80 70 60 50 40 30 20 10 –16384 0 CODE 16384 32767 1608 G02 S/(N + D) vs Input Frequency and Amplitude VIN = 0dB VIN = – 20dB VIN = – 40dB –0.6 –0.8 –1.0 –32768 0 1k 10k 100k FREQUENCY (Hz) 1M 1608 G03 Distortion vs Input Frequency 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 Spurious-Free Dynamic Range vs Input Frequency THD 3RD 2ND –110 1k 100k INPUT FREQUENCY (Hz) 10k 1M 1608 G05 –110 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1608 G06 5 LTC1608 TYPICAL PERFOR A CE CHARACTERISTICS Intermodulation Distortion 0 –20 –40 –60 –80 –100 –120 –140 0 50 100 150 200 250 1608 G07 COMMON MODE REJECTION (dB) 1M 1608 G08 AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB) fSAMPLE = 500kHz fIN1 = 96.56kHz fIN2 = 99.98kHz AMPLITUDE (dB) FREQUENCY (kHz) PI FU CTIO S AIN+ (Pin 1): Positive Analog Input. The ADC converts the difference voltage between AIN+ and AIN– with a differential range of ± 2.5V. AIN+ has a ± 2.5V input range when AIN– is grounded. AIN– (Pin 2): Negative Analog Input. Can be grounded, tied to a DC voltage or driven differentially with AIN+ . VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with 2.2µF tantalum in parallel with 0.1µF ceramic. REFCOMP (Pin 4): 4.375V (Nominal) Reference Compensation Pin. Bypass to AGND with 22µF tantalum in parallel with 0.1µF ceramic. This is not recommended for use as an external reference due to part-to-part output voltage variations and glitches that occur during the conversion. AGND (Pins 5 to 8): Analog Grounds. Tie to analog ground plane. DVDD (Pin 9): 5V Digital Power Supply. Bypass to DGND with 10µF tantalum in parallel with 0.1µF ceramic. DGND (Pin 10): Digital Ground for Internal Logic. Tie to analog ground plane. D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15 is the Most Significant Bit. BUSY (Pin 27): The BUSY output shows the converter status. It is low when a conversion is in progress. Data is valid on the rising edge of BUSY. OGND (Pin 28): Digital Ground for Output Drivers. OVDD (Pin 29): Digital Power Supply for Output Drivers. Bypass to OGND with 10µF tantalum in parallel with 0.1µF ceramic. RD (Pin 30): Read Input. A logic low enables the output drivers when CS is low. CONVST (Pin 31): Conversion Start Signal. This active low signal starts a conversion on its falling edge when CS is low. CS (Pin 32): The Chip Select Input. Must be low for the ADC to recognize CONVST and RD inputs. SHDN (Pin 33): Power Shutdown. Drive this pin low with CS low for nap mode. Drive this pin low with CS high for sleep mode. VSS (Pin 34): – 5V Negative Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic. AVDD (Pin 35): 5V Analog Power Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic. AVDD (Pin 36): 5V Analog Power Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic and connect this pin to Pin 35 with a 10Ω resistor. 6 UW Power Supply Feedthrough vs Ripple Frequency 0 –20 –40 –60 –80 fSAMPLE = 500kHz VRIPPLE = 10mV Input Common Mode Rejection vs Input Frequency 80 70 60 50 40 30 20 10 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1608 G14a –100 AVDD –120 –140 1k 10k 100k INPUT FREQUENCY (Hz) V SS U U U LTC1608 FU CTIO AL BLOCK DIAGRA 2.2µF 10µF 3 VREF + 4 REFCOMP 22µF + 4.375V 1.75X 1 AIN+ DIFFERENTIAL ANALOG INPUT ± 2.5V 2 AIN– + – OGND 28 16-BIT SAMPLING ADC AGND 5 AGND 6 B15 TO B0 OUTPUT BUFFERS 16-BIT PARALLEL BUS 11 TO 26 1608 BD D15 TO D0 AGND 7 AGND VSS 8 34 10µF + –5V TEST CIRCUITS Load Circuits for Access Timing 5V 1k DN 1k CL DN CL DN 1k CL DN CL Load Circuits for Output Float Delay 5V 1k (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL 1608 TC01 (A) VOH TO Hi-Z APPLICATIO S I FOR ATIO CONVERSION DETAILS The LTC1608 uses a successive approximation algorithm and internal sample-and-hold circuit to convert an analog signal to a 16-bit parallel output. The ADC is complete with a sample-and-hold, a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion, the successive approximation register (SAR) resets. Once a conversion cycle has begun, it cannot be restarted. During the conversion, the internal differential 16-bit capacitive DAC output is sequenced by the SAR from the Most Significant Bit (MSB) to the Least Significant Bit (LSB). Referring to Figure 1, the AIN+ and AIN– inputs are acquired during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a duration of 480ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. During the convert phase, the comparator zeroing switches open, putting the comparator into compare mode. The input switches connect the CSMPL capacitors to ground, transferring the differential analog input charge onto the summing junctions. This input charge is successively + W 10Ω 36 5V 10µF 5V 10µF 35 AVDD U W UU U U + 9 + 10 DGND SHDN 33 CS 32 CONVST 31 RD 30 BUSY 27 OVDD 29 5V OR 3V 10µF µP CONTROL LINES AVDD DVDD 7.5k 2.5V REF CONTROL LOGIC AND TIMING (B) VOL TO Hi-Z 1608 TC02 7 LTC1608 APPLICATIO S I FOR ATIO CSMPL AIN+ SAMPLE HOLD CSMPL AIN– SAMPLE HOLD HOLD +CDAC ZEROING SWITCHES HOLD + –CDAC +VDAC COMP – –VDAC SAR 16 OUTPUT LATCHES Figure 1. Simplified Block Diagram compared with the binary-weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the AIN+ and AIN– input charges. The SAR contents (a 16-bit data word) which represent the difference of AIN+ and AIN– are loaded into the 16-bit output latches. DIGITAL INTERFACE The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion. Internal Clock The A/D converter has an internal clock that runs the A/D conversion. The internal clock is factory trimmed to achieve a typical conversion time of 1.45µs and a maximum conversion time of 1.8µs over the full temperature range. No external adjustments are required. The guaranteed maximum acquisition time is 400ns. In addition, a throughput time (acquisition + conversion) of 2µs and a minimum sampling rate of 500ksps are guaranteed. 8 U 3V Input/Output Compatible The LTC1608 operates on ± 5V supplies, which makes the device easy to interface to 5V digital systems. This device can also talk to 3V digital systems: the digital input pins (SHDN, CS, CONVST and RD) of the LTC1608 recognize 3V or 5V inputs. The LTC1608 has a dedicated output supply pin (OVDD) that controls the output swings of the digital output pins (D0 to D15, BUSY) and allows the part to talk to either 3V or 5V digital systems. The output is two’s complement binary. Power Shutdown • • • D15 D0 1608 F01 W UU The LTC1608 provides two power shutdown modes, Nap and Sleep, to save power during inactive periods. The Nap mode reduces the power by 95% and leaves only the digital logic and reference powered up. The wake-up time from Nap to active is 200ns. In Sleep mode, all bias currents are shut down and only leakage current remains (about 1µA). Wake-up time from Sleep mode is much longer since the reference circuit must power up and settle. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 80ms with the recommended 22 µF capacitor. Shutdown is controlled by Pin 33 (SHDN). The ADC is in shutdown when SHDN is low. The shutdown mode is selected with Pin 32 (CS). When SHDN is low, CS low selects nap and CS high selects sleep. SHDN t3 CS 1608 F02a Figure 2a. Nap Mode to Sleep Mode Timing SHDN t4 CONVST 1608 F02b Figure 2b. SHDN to CONVST Wake-Up Timing LTC1608 APPLICATIO S I FOR ATIO CS t2 CONVST t1 RD 1608 F03 Figure 3. CS top CONVST Setup Timing 4 CHANGE IN DNL (LSB) 3 2 tCONV tACQ 1 0 0 250 500 750 1000 1250 1500 CONVST LOW TIME, t5 (ns) 1608 F04 Figure 4. Change in DNL vs CONVST Low Time. Be Sure the CONVST Pulse Returns High Early in the Conversion or After the End of Conversion Timing and Control Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A falling edge applied to the CONVST pin will start a conversion after the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. We recommend using a narrow logic low or narrow logic high CONVST pulse to start a conversion as shown in Figures 5 and 6. A narrow low or high CONVST pulse prevents the rising edge of the CONVST pulse from upsetting the critical bit decisions during the conversion time. Figure 4 shows the change of the differential nonlinearity error versus the low time of the CONVST pulse. As shown, if CONVST returns high early in the conversion (e.g., CONVST low time tCONV), accuracy is unaffected. For best results, keep t 5 less than 500ns or greater than tCONV. Figures 5 through 9 show several different modes of operation. In modes 1a and 1b (Figures 5 and 6), CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. In mode 2 (Figure 7) CS is tied low. The falling edge of CONVST signal starts the conversion. Data outputs are in three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared data bus. In slow memory and ROM modes (Figures 8 and 9), CS is tied low and CONVST and RD are tied together. The MPU starts the conversion and reads the output with the combined CONVST-RD signal. Conversions are started by the MPU or DSP (no external sample clock is needed). In slow memory mode, the processor applies a logic low to RD (= CONVST), starting the conversion. BUSY goes low, forcing the processor into a wait state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results appear on the data outputs; BUSY goes high, releasing the processor and the processor takes RD (= CONVST) back high and reads the new conversion data. In ROM mode, the processor takes RD (= CONVST) low, starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result and initiate another conversion. DIFFERENTIAL ANALOG INPUTS Driving the Analog Inputs The differential analog inputs of the LTC1608 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN – input is grounded). The AIN+ and AIN – inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current 1750 2000 W UU 9 LTC1608 APPLICATIO S I FOR ATIO CS = RD = 0 t5 CONVST t6 BUSY t CONV DATA DATA (N – 1) D15 TO D0 Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) CS = RD = 0 t13 CONVST t6 BUSY tCONV t5 DATA DATA (N – 1) D15 TO D0 Figure 6. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled (CONVST = ) CS = 0 tCONV t5 CONVST t6 BUSY t9 RD t 10 DATA DATA N D15 TO D0 1608 F07 Figure 7. Mode 2. CONVST Starts a Conversion. Data is Read by RD 10 U t8 t7 DATA N D15 TO D0 DATA (N + 1) D15 TO D0 1608 F05 W UU t8 t6 t7 DATA N D15 TO D0 DATA (N + 1) D15 TO D0 1608 F06 t13 t8 t 12 t 11 LTC1608 APPLICATIO S I FOR ATIO CS = 0 RD = CONVST t6 BUSY t 10 DATA DATA (N – 1) D15 TO D0 t CONV Figure 8. Mode 2. Slow Memory Mode Timing CS = 0 RD = CONVST t6 BUSY t 10 DATA t CONV DATA (N – 1) D15 TO D0 spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1608 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 10). For minimum acquisition time with high source impedance, a buffer amplifier should be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 200ns for full throughput rate). Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of +1 and has a unity-gain bandwidth of 50MHz, then ACQUISITION TIME (µs) U t8 t 11 t7 DATA N D15 TO D0 DATA N D15 TO D0 DATA (N + 1) D15 TO D0 1608 F08 W UU t8 t 11 DATA N D15 TO D0 1608 F09 Figure 9. ROM Mode Timing 10 1 0.1 0.01 1 10 100 1k SOURCE RESISTANCE (Ω) 10k 1608 F10 Figure 10. tACQ vs Source Resistance the output impedance at 50MHz should be less than 100Ω. The second requirement is that the closed-loop bandwidth must be greater than 15MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. 11 LTC1608 APPLICATIO S I FOR ATIO The best choice for an op amp to drive the LTC1608 will depend on the application. Generally applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1608. More detailed information is available in the Linear Technology databooks, the LinearViewTM CD-ROM and on our web site at: www.linear-tech. com. LT ® 1007: Low Noise Precision Amplifier. 2.7mA supply current, ± 5V to ± 15V supplies, gain bandwidth product 8MHz, DC applications. LT1097: Low Cost, Low Power Precision Amplifier. 300µA supply current, ± 5V to ± 15V supplies, gain bandwidth product 0.7MHz, DC applications. LT1227: 140MHz Video Current Feedback Amplifier. 10mA supply current, ± 5V to ±15V supplies, low noise and low distortion. LT1360: 37MHz Voltage Feedback Amplifier. 3.8mA supply current, ± 5V to ±15V supplies, good AC/DC specs. LT1363: 50MHz Voltage Feedback Amplifier. 6.3mA supply current, good AC/DC specs. LT1364/LT1365: Dual and Quad 50MHz Voltage Feedback Amplifiers. 6.3mA supply current per amplifier, good AC/DC specs. LT1468: 90MHz, 22V/µs 16-Bit Accurate Operational Amplifier. 3.8mA supply current, excellent DC specs and very low distortion performance to 100kHz. LT1469: Dual 90MHz, 22V/µs 16-Bit Accurate Operational Amplifier. 4.1mA supply current, excellent DC specs and very low distortion performance to 100kHz. Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1608 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 15MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to 12 U minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 11 shows a 3000pF capacitor from AIN+ to ground and a 100Ω source resistor to limit the input bandwidth to 530kHz. The 3000pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. ANALOG INPUT 100Ω 3000pF 1 2 3 4 22µF 5 AGND 1608 F11 W UU AIN+ AIN– LTC1608 VREF REFCOMP Figure 11. RC Input Filter Input Range The ± 2.5V input range of the LTC1608 is optimized for low noise and low distortion. Most op amps also perform well over this same range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. Some applications may require other input ranges. The LTC1608 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference and input circuitry and how they affect the input range. Internal Reference The LTC1608 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500V. It is connected internally to a reference amplifier and is available at VREF (Pin 3) (see Figure 12a). LinearView is a trademark of Linear Technology Corporation. LTC1608 APPLICATIO S I FOR ATIO 2.500V 3 VREF R1 7.5k BANDGAP REFERENCE 4.375V 4 REFCOMP REFERENCE AMP R2 12k R3 16k LTC1608 1608 F12a 22µF 5 AGND Figure 12a. LTC1608 Reference Circuit 5V VIN LT1019A-2.5 VOUT ANALOG INPUT 1 2 3 AIN+ AIN– VREF LTC1608 4 + REFCOMP 22µF 0.1µF 5 AGND 1608 F12b Figure 12b. Using the LT1019-2.5 as an External Reference COMMON MODE REJECTION (dB) A 7.5k resistor is in series with the output so that it can be easily overdriven by an external reference or other circuitry (see Figure 12b). The reference amplifier gains the voltage at the VREF pin by 1.75 to create the required internal reference voltage. This provides buffering between the VREF pin and the high speed capacitive DAC. The reference amplifier compensation pin (REFCOMP, Pin 4) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 22µF or greater. Using a 0.1µF ceramic in parallel is recommended. The VREF pin can be driven with a DAC or other means shown in Figure 13. This is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. The filtering of the internal LTC1608 reference amplifier will limit the bandwidth and settling time of this circuit. A settling time of 20ms should be allowed for after a reference adjustment. U 1 ANALOG INPUT 2V TO 2.7V DIFFERENTIAL AIN+ AIN– LTC1608 LTC1450 2V TO 2.7V 3 VREF 2 4 22µF 5 AGND 1608 F13 W UU REFCOMP Figure 13. Driving VREF with a DAC Differential Inputs The LTC1608 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of AIN+ – AIN– independent of the common mode voltage (see Figure 15a). The common mode rejection holds up to extremely high frequencies (see Figure 14a). The only requirement is that both inputs can not exceed the AVDD or VSS power supply voltages. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar zero error (BZE) will vary. The change in BZE is typically less than 0.1% of the common mode voltage. Dynamic performance is also affected by the common mode voltage. THD will degrade as the inputs approach either power supply rail, from 96dB with a common mode of 0V to 86dB with a common mode of 2.5V or – 2.5V. 80 70 60 50 40 30 20 10 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M 1608 G14a Figure 14a. CMRR vs Input Frequency 13 LTC1608 APPLICATIO S I FOR ATIO OUTPUT CODE Differential inputs allow greater flexibility for accepting different input ranges. Figure 14b shows a circuit that converts a 0V to 5V analog input signal with only an additional buffer that is not in the signal path. ANALOG INPUT 1 2 ± 2.5V 0V TO 5V AIN+ AIN– VREF LTC1608 + – 3 4 22µF 5 REFCOMP AGND 1608 F14b Figure 14b. Selectable 0V to 5V or ± 2.5V Input Range Full-Scale and Offset Adjustment Figure 15a shows the ideal input/output characteristics for the LTC1608. The code transitions occur midway between successive integer LSB values (i.e., – FS + 0.5LSB, – FS + 1.5LSB, – FS + 2.5LSB,... FS – 1.5LSB, FS – 0.5LSB). The output is two’s complement binary with 1LSB = FS – (– FS)/65536 = 5V/65536 = 76.3µV. In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 15b shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset applied to the AIN– input. For zero offset error, apply – 38µV (i.e., – 0.5LSB) at AIN+ and adjust the offset at the AIN– input by varying the output voltage of pin VOUTA from the LTC1662 until the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. For full-scale adjustment, an input voltage of 2.499886V (FS/2 – 1.5LSBs) is applied to AIN+ and the output voltage of pin VOUTB is adjusted until the output code flickers between 0111 1111 1111 1110 and 0111 1111 1111 1111. BOARD LAYOUT AND GROUNDING Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1608, a printed circuit board with 5V 14 U 011...111 011...110 000...001 000...000 111...111 111...110 100...001 100...000 – (FS – 1LSB) FS – 1LSB 1608 F15a W UU INPUT VOLTAGE (AIN+ – AIN– ) Figure 15a. LTC1608 Transfer Characteristics ANALOG INPUT LTC1662 CS/LD VOUTA GND SCK VCC SDI VOUTB REF 0.1µF R1 40.2k R3 1.5M 1 2 R2 100Ω 3 LTC1608 VREF AIN+ AIN– + 80.6k 1% –5V 2.2µF + 4 5 REFCOMP AGND 1608 F15b 22µF OFFSET ADJ RANGE: ± 0.125% FULL-SCALE ADJ RANGE: ± 0.25% Figure 15b. Offset and Full-Scale Adjust Circuit ground plane is required. Layout should ensure that digital and analog signal lines are separated as much as possible. Particular care should be taken not to run any digital track alongside an analog signal track or underneath the ADC.The analog input should be screened by AGND. An analog ground plane separate from the logic system ground should be established under and around the ADC. Pin 5 to Pin 8 (AGNDs), Pin 10 (ADC’s DGND) and all other analog grounds should be connected to this single analog ground point. The REFCOMP bypass capacitor and the DVDD bypass capacitor should also be connected to this analog ground plane. No other digital grounds should be connected to this analog ground plane. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. In LTC1608 APPLICATIO S I FOR ATIO applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1608 has differential inputs to minimize noise coupling. Common mode noise on the AIN+ and AIN– leads will be rejected by the input CMRR. The AIN– input can be used as a ground sense for the AIN+ input; the LTC1608 will hold and convert the difference voltage between AIN+ and AIN– . The leads to AIN+ (Pin 1) and AIN– (Pin 2) should be kept as short as possible. In applications where this is not possible, the AIN+ and AIN– traces should be run side by side to equalize coupling. SUPPLY BYPASSING High quality, low series resistance ceramic, 10µF or 22µF bypass capacitors should be used at the VDD and REFCOMP pins as shown in Figure 16 and in the Typical Application on the first page of this data sheet. Surface mount ceramic capacitors such as Taiyo Yuden’s LMK325BJ106MN and LMK432BJ226MM provide excellent bypassing in a small board space. Alternatively, 10µF tantalum capacitors in parallel with 0.1µF ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. 1 AIN+ AIN– 2 ANALOG INPUT CIRCUITRY VREF REFCOMP AGND 3 2.2µF 4 22µF + – Figure 16. Power Supply Grounding Practice U EXAMPLE LAYOUT Figures 17a, 17b, 17c, 17d and 17e show the schematic and layout of an evaluation board. The layout demonstrates the proper use of decoupling capacitors and ground plane with a 4-layer printed circuit board. DC PERFORMANCE The noise of an ADC can be evaluated in two ways: signalto-noise raio (SNR) in frequency domain and histogram in time domain. The LTC1608 excels in both. Figure 19a demonstrates that the LTC1608 has an SNR of over 90dB in frequency domain. The noise in the time domain histogram is the transition noise associated with a high resolution ADC which can be measured with a fixed DC signal applied to the input of the ADC. The resulting output codes are collected over a large number of conversions. The shape of the distribution of codes will give an indication of the magnitude of the transition noise. In Figure 18, the distribution of output codes is shown for a DC input that has been digitized 4096 times. The distribution is Gaussian and the RMS code transition noise is about 0.66LSB. This corresponds to a noise level of 90.9dB relative to full scale. Adding to that the theoretical 98dB of quantization error for 16-bit ADC, the resultant corresponds to an SNR level of 90.1dB which correlates very well to the frequency domain measurements in Dynamic Performance section. DYNAMIC PERFORMANCE The LTC1608 has excellent high speed sampling capability. Fast fourier transform (FFT) test techniques are used to test the ADC’s frequency response, distortions and LTC1608 VSS 34 10µF AVDD 36 10µF AVDD 35 10µF DVDD 9 10µF DGND OVDD OGND 10 29 10µF 28 DIGITAL SYSTEM 5, 6, 7, 8 1608 F16 W UU 15 LTC1608 APPLICATIO S I FOR ATIO E5 3V E1 5V R6 JP1 10Ω OVDD E2 –5V + C13 22µF + C12 22µF C7 E6 1µF GND 5V R3 C6 10Ω 1µF C5 1µF R5 10k E3 VREF C11 2.2µF AIN+ AIN– 1 2 3 U1 LTC1608 AIN+ AIN– VREF AVDD1 AVDD2 VSS 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 5V C10 22µF 4 5 6 7 C9 5V 1µF E4 GND 8 9 10 11 12 13 14 15 16 17 18 REFCOMP SHDN AGND AGND AGND AGND DVDD DGND D15 D14 D13 D12 D11 D10 D9 D8 CS CONV RD OVDD OGND BUSY D0 D1 D2 D3 D4 D5 D6 D7 C4 1µF 5V C21 0.1µF J3 R7 50Ω R17 10k 3 C14 1000pF 2 C17 10pF C27 100pF AIN+ + – 8 1 C20 0.1µF R11 50Ω R13 50Ω AIN (U1-1) C25 100pF + U4A LT1469 4 –5V R8 402Ω C15 10pF C18 10pF R15 100Ω C16 10pF C24 100pF C26 1000pF 6 R10 50Ω R16 10k – U4B LT1469 R9 402Ω 7 R12 50Ω C22 100pF AIN– J4 5 C19 1000pF + Figure 17a. LTC1608 Suggested Evaluation Circuit Schematic 16 U C28 22µF OVDD U5 TC7SH08FUTE85L J2 CONVERT START C1 0.1µF U2 MC74HC574ADT 20 1 OE VCC 19 2 D0 Q0 18 3 D1 Q1 17 4 D2 Q2 16 5 D3 Q3 15 6 D4 Q4 14 7 D5 Q5 13 8 D6 Q6 12 9 D7 Q7 11 10 GND CLK C3 0.1µF OVDD U3 74HC574 1 2 3 4 5 6 7 8 9 10 OE D0 D1 D2 D3 D4 D5 D6 D7 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 20 19 18 17 16 15 14 13 12 11 JP2 U6 TC7SH04F OVDD OVDD E7 GND J1 CONN20 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 LSB CLK MSB C8 0.1µF + W UU JP3 R4 10k R2 10k R1 51k OVDD GND CLK R14 50Ω C23 100pF AIN– (U1-2) LTC1608 APPLICATIO S I FOR ATIO Figure 17b. Suggested Evaluation Circuit Board. Component Side Silkscreen and Signal Traces ANALOG GROUND PLANE DIGITAL GROUND PLANE Figure 17d. Suggested Evaluation Circuit Board. Inner Layer 1 Showing Separate Analog and Digital Ground Planes 2500 2000 COUNT 1500 1000 500 0 –5 –4 –3 –2 –1 0 1 CODE 2 3 4 5 1608 F18 Figure 18. Histogram for 4096 Conversions U Figure 17c. Suggested Evaluation Circuit Board. Bottom Side Showing Signal Traces ANALOG GROUND PLANE DIGITAL GROUND PLANE W UU Figure 17e. Suggested Evaluation Circuit Board. Inner Layer 2 Showing Separate Analog and Digital Ground Planes noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figures 19a and 19b show typical LTC1608 FFT plots. Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 19a shows a typical spectral content with a 500kHz sampling rate and a 3kHz input. 17 LTC1608 APPLICATIO S I FOR ATIO 0 –20 –40 fSAMPLE = 500kHz fIN = 2.807kHz SINAD = 88.9dB THD = –98dB AMPLITUDE (dB) EFFECTIVE BITS –60 –80 –100 –120 –140 0 50 100 150 200 250 1608 F19a FREQUENCY (kHz) Figure 19a. This FFT of the LTC1608’s Conversion of a Full-Scale 3kHz Sine Wave Shows Outstanding Response with a Very Low Noise Floor When Sampling at 500ksps 0 –20 –40 –60 –80 –100 –120 –140 0 50 100 150 200 250 1608 F19b fSAMPLE = 500kHz fIN = 98.754kHz SINAD = 86.7dB THD = –92.6dB AMPLITUDE (dB) FREQUENCY (kHz) Figure 19b. Even with Inputs at 100kHz, the LTC1608’s Dynamic Linearity Remains Robust The dynamic performance is excellent for input frequencies up to and beyond the Nyquist limit of 250kHz. Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: ENOB = [S/(N + D) – 1.76]/6.02 where ENOB is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 500kHz, the LTC1608 maintains above 14 bits up to the Nyquist input frequency of 250kHz (refer to Figure 20). 18 U 16 15 14 13 12 11 10 9 8 1k 10k 100k FREQUENCY (Hz) 98 92 86 80 74 68 62 56 50 1M 1608 F20 W UU Figure 20. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency SINAD (dB) Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log V22 + V32 + V 42 + ...Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs Input Frequency is shown in Figure 21. The LTC1608 has good distortion performance up to the Nyquist frequency and beyond. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include LTC1608 APPLICATIO S I FOR ATIO AMPLITUDE (dB BELOW THE FUNDAMENTAL) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 1k 100k INPUT FREQUENCY (Hz) 10k 1M 1608 F21 THD 3RD 2ND Figure 21. Distortion vs Input Frequency 0 –20 –40 –60 –80 –100 –120 –140 0 50 100 150 200 250 1608 F22 fSAMPLE = 500kHz fIN1 = 96.56kHz fIN2 = 99.98kHz AMPLITUDE (dB) FREQUENCY (kHz) Figure 22. Intermodulation Distortion Plot PACKAGE DESCRIPTIO G Package 36-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 5.20 – 5.38** (.205 – .212) 12.67 – 12.93* (.499 – .509) 1.73 – 1.99 (.068 – .078) 0° – 8° 7.65 – 7.90 (.301 – .311) .05 – .21 (.002 – .008) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 .13 – .22 (.005 – .009) .55 – .95 (.022 – .037) .65 (.0256) BSC NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE .25 – .38 (.010 – .015) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U (fa ± fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: U W UU IMD fa ± fb = 20Log ( ) Amplitude at (fa ± fb) Amplitude at fa Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 84dB (13.66 effective bits). The LTC1608 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 G36 SSOP 0501 19 LTC1608 TYPICAL APPLICATIO 5V Using the LTC1608 and Two LTC1391s as an 8-Channel Differential 16-Bit ADC System 2.2µF 10µF 10Ω 36 AVDD 5V 10µF 5V 10µF LTC1391 CH0+ 1 2 3 4 5 6 7 CH7 + 8 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 V+ D V 16 15 + 1µF – 14 –5V 1µF DOUT DIN CS CLK GND 12 11 10 9 22µF 5V LTC1391 CH0 – 1 2 3 4 5 6 7 CH7 – CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 V+ D V– DOUT DIN CS CLK GND 16 15 14 12 11 10 9 8 RELATED PARTS SAMPLING ADCs PART NUMBER LTC1410 LTC1415 LTC1418 LTC1419 LTC1604 LTC1605 LTC1606 DESCRIPTION 12-Bit, 1.25Msps, ± 5V ADC 12-Bit, 1.25Msps, Single 5V ADC 14-Bit, 200ksps, Single 5V ADC Low Power 14-Bit, 800ksps ADC 16-Bit, 333ksps, ± 5V ADC 16-Bit, 100ksps, Single 5V ADC 16-Bit, 250ksps, Single 5V ADC COMMENTS 71.5dB SINAD at Nyquist, 150mW Dissipation 55mW Power Dissipation, 72dB SINAD 15mW, Serial/Parallel ± 10V True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation 90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608 ± 10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606 ± 10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605 DACs PART NUMBER LTC1595 LTC1596 LTC1597/LTC1591 LTC1650 DESCRIPTION 16-Bit Serial Multiplying IOUT DAC in SO-8 16-Bit Serial Multiplying IOUT DAC 16-Bit/14-Bit Parallel, Multiplying DACs 16-Bit Serial VOUT DAC COMMENTS ± 1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade ± 1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade ± 1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors Low Power, Low Gritch, 4-Quadrant Multiplication 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com + 13 –5V DIN CS CLK µP CONTROL LINES + + 13 1µF –5V U + 3 VREF + 35 AVDD + 9 DVDD 10 DGND SHDN 33 LTC1608 4 REFCOMP 7.5k 1.75X 2.5V REF + 4.375V CONTROL LOGIC AND TIMING CS 32 CONVST 31 RD 30 BUSY 27 OVDD 29 µP CONTROL LINES + 1 AIN + + – 16-BIT SAMPLING ADC B15 TO B0 OUTPUT BUFFERS D15 TO D0 OGND 28 16-BIT PARALLEL BUS 11 TO 26 5V OR 3V 10µF 3000pF – 2 AIN 3000pF AGND 5 AGND 6 AGND 7 AGND VSS 8 34 10µF 1608 TA03 1608f LT/TP 0601 2K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2000