LTC1736CG#TRPBF

LTC1736 5-Bit Adjustable High Efficiency Synchronous Step-Down Switching Regulator U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®1736 is a synchronous step-down switching regulator controller optimized for CPU power. The output voltage is programmed by a 5-bit digital-to-analog converter (DAC) that adjusts the output voltage from 0.925V to 2.00V according to Intel mobile VID specifications. The 0.8V reference is compatible with future microprocessor generations. Dual N-Channel MOSFET Synchronous Drive Synchronizable/Programmable Fixed Frequency Wide VIN Range: 3.5V to 36V Operation 5-Bit Digital-to-Analog VOUT Selection: 0.925V to 2.00V Range with 50mV/25mV Steps OPTI-LOOPTM Compensation Minimizes COUT ±1% Output Voltage Accuracy Power Good Output Voltage Monitor Active Voltage Positioning Compatible Output Overvoltage Crowbar Protection Internal Current Foldback Latched Short-Circuit Shutdown Timer with Defeat Option Forced Continuous Control Pin Optional Programmable Soft-Start Remote Output Voltage Sense Available in 24-Lead SSOP Package The operating frequency (synchronizable up to 500kHz) is set by an external capacitor allowing maximum flexibility in optimizing efficiency. The output voltage is monitored by a power good window comparator that indicates when the output is within 7.5% of its programmed value. Protection features include: internal foldback current limiting, output overvoltage crowbar and optional short-circuit shutdown. Soft-start is provided by an external capacitor that can be used to properly sequence supplies. The operating current level is user-programmable via an external current sense resistor. Wide input supply range allows operation from 3.5V to 30V (36V maximum). U APPLICATIO S ■ ■ ■ Notebook and Palmtop Computers, PDAs Power Supply for Mobile Pentium® II and Pentium III Processors Low Voltage Power Supplies Pin defeatable Burst ModeTM operation provides high efficiency at low load currents. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. , LTC and LT are registered trademarks of Linear Technology Corporation. OPTI-LOOP and Burst Mode are trademarks of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation. U TYPICAL APPLICATIO VIN 5V TO 24V COSC 47pF RC 33k VIN COSC CSS 0.1µF M1 FDS6680A TG CC1 330pF RUN/SS L1 1.2µH RSENSE 0.004Ω VOUT 1.35V TO 1.60V 12A SW ITH CC2 47pF CIN 22µF/50V ×2 CERAMIC LTC1736 VIDVCC DB CMDSH-3 INTVCC PGOOD VID4 VID3 VID2 VID1 VID0 SGND BOOST + + 4.7µF BG CB 0.22µF M2 FDS6680A ×2 D1 MBRS340T3 PGND VOSENSE SENSE – SENSE + COUT 180µF/4V ×4 COUT: PANASONIC EEFUEOG181R CIN: MARCON THCR70EIH226ZT L1: PANASONIC ETQP6RZIR20HFA RSENSE: IRC LRF2010-01-R004J 1000pF 47pF 1736 F01 Figure 1. High Efficiency Step-Down Converter 1 LTC1736 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) Input Supply Voltage (VIN).........................36V to – 0.3V Topside Driver Supply Voltage (BOOST)....42V to – 0.3V Switch Voltage (SW) ....................................36V to – 5V EXTVCC, VIDVCC, (BOOST – SW) Voltages ..7V to – 0.3V SENSE +, SENSE – .......................... 1.1(INTVCC) to – 0.3V FCB Voltage ............................(INTVCC + 0.3V) to – 0.3V ITH, VOSENSE, VFB Voltage .........................2.7V to – 0.3V RUN/SS, VID0 to VID4, PGOOD Voltages ....7V to – 0.3V Peak Driver Output Current 7.5%) as well as other more serious conditions that may overvoltage the output. In this case, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Foldback current limiting for an output shorted to ground is provided by amplifier A. As VFB drops below 0.6V, the buffered ITH input to the current comparator is gradually pulled down to a 0.86V clamp. This reduces peak inductor current to about 1/4 of its maximum value. Low Current Operation The LTC1736 has three low current modes controlled by the FCB pin. Burst Mode operation is selected when the FCB pin is above 0.8V (typically tied to INTVCC). During Burst Mode operation, if the error amplifier drives the ITH voltage below 0.86V, the buffered ITH input to the current comparator will be clamped at 0.86V. The inductor current peak is then held at approximately 20mV/RSENSE (about 1/ 4 of maximum output current). If ITH then drops below 0.5V, the Burst Mode comparator B will turn off both MOSFETs to maximize efficiency. The load current will be supplied solely by the output capacitor until ITH rises above the 60mV hysteresis of the comparator and switching is resumed. Burst Mode operation is disabled by comparator F when the FCB pin is brought below 0.8V. This forces continuous operation and can assist secondary winding regulation. When the FCB pin is driven by an external oscillator, a low noise cycle-skipping mode is invoked and the internal oscillator is synchronized to the external clock by comparator C. In this mode the 25% minimum inductor current clamp is removed, providing constant frequency discontinuous operation over the widest possible output current range. This constant frequency operation is not quite as efficient as Burst Mode operation, but provides a lower noise, constant frequency spectrum. The FCB pin is tied to ground when forced continuous operation is desired. This operation is the least efficient mode, but is desirable in certain applications. The output can source or sink current in this mode. When sinking current while in forced continuous operation, current will be forced back into the main power supply potentially boosting the input supply to dangerous voltage levels— BEWARE. Foldback Current, Short-Circuit Detection and Short-Circuit Latchoff The RUN/SS capacitor, CSS, is used initially to limit the inrush current of the switching regulator. After the controller has been started and been given adequate time to charge up the output capacitors and provide full load current, CSS is used as a short-circuit time-out circuit. If the output voltage falls to less than 70% of its nominal output voltage, CSS begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. If the condition lasts for a long enough period as determined by the size of the CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latchoff can be overridden by providing a current > 5µA at a compliance of 5V to the RUN/SS pin. This current shortens the soft-start period but also prevents net discharge of CSS during an overcurrent and/or shortcircuit condition. Foldback current limiting is activated when the output voltage falls below 70% of its nominal level whether or not the short-circuit latchoff circuit is enabled. 9 LTC1736 U OPERATIO (Refer to Functional Diagram) INTVCC/EXTVCC Power VID Control Power for the top and bottom MOSFET drivers and most of the internal circuitry of the LTC1736 is derived from the INTVCC pin. When the EXTVCC pin is left open, an internal 5.2V low dropout regulator supplies the INTVCC power from VIN. If EXTVCC is raised above 4.7V, the internal regulator is turned off and an internal switch connects EXTVCC to INTVCC. This allows a high efficiency source, such as the notebook main 5V system supply or a secondary output of the converter itself, to provide the INTVCC power. Voltages up to 7V can be applied to EXTVCC for additional gate drive capability. Bits VID0 to VID4 are logic inputs setting the output voltage using an internal 5-bit DAC as a feedback resistive voltage divider. The output voltage can be set in 50mV or 25mV increments from 0.925V to 2.0V according to Table 1. Pins VID0 to VID4 are internally pulled up to VIDVCC. To provide clean start-up and to protect the MOSFETs, undervoltage lockout is used to keep both MOSFETs off until the input voltage is above 3.5V. PGOOD A window comparator monitors the output voltage and its open-drain output is pulled low when the divided down output voltage is not within ±7.5% of the reference voltage of 0.8V. U W U U APPLICATIO S I FOR ATIO The basic LTC1736 application circuit is shown in Figure 1 on the first page of this data sheet. External component selection is driven by the load requirement and begins with the selection of RSENSE. Once RSENSE is known, COSC and L can be chosen. Next, the power MOSFETs and D1 are selected. The operating frequency and the inductor are chosen based largely on the desired amount of ripple current. Finally, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple and transient specifications. The circuit shown in Figure 1 can be configured for operation up to an input voltage of 28V (limited by the external MOSFETs). RSENSE Selection For Output Current RSENSE is chosen based on the required output current. The LTC1736 current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of SGND to 1.1(INTVCC). The current comparator threshold sets the peak of the inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, ∆IL. Allowing a margin for variations in the LTC1736 and external component values yields: 10 RSENSE = 50mV IMAX COSC Selection for Operating Frequency and Synchronization The choice of operating frequency and inductor value is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss. However, lower frequency operation requires more inductance for a given amount of ripple current. The LTC1736 uses a constant-frequency architecture with the frequency determined by an external oscillator capacitor COSC. Each time the topside MOSFET turns on, the voltage on COSC is reset to ground. During the on-time COSC is charged by a fixed current. When the voltage on the capacitor reaches 1.19V, COSC is reset to ground. The process then repeats. The value of COSC is calculated from the desired operating frequency assuming no external clock input on the FCB pin: LTC1736 U W U U APPLICATIO S I FOR ATIO cycles to recharge the bootstrap capacitor. This minimizes audible noise while maintaining reasonably high efficiency.  1.61(107)   – 11 COSC (pF) =   Frequency  Inductor Value Calculation A graph for selecting COSC versus frequency is given in Figure 2. The maximum recommended switching frequency is 550kHz . The internal oscillator runs at its nominal frequency (fO) when the FCB pin is pulled high to INTVCC or connected to ground. Clocking the FCB pin above and below 0.8V will cause the internal oscillator to lock to an external clock signal with a frequency between 0.9fO and 1.3fO. The clock high level must exceed 1.3V for at least 0.3µs, and the clock low level must be less than 0.3V for at least 0.3µs. The top MOSFET turn-on will synchronize with the rising edge of the external clock. Attempting to synchronize to too high an external frequency (above 1.3fO) can result in inadequate slope compensation and possible loop instability at high duty cycles. If this condition exists simply lower the value of COSC so fEXT = fO according to Figure 2. 100.0 87.5 COSC VALUE (pF) 75.0 62.5 50.0 37.5 25.0 12.5 0 0 100 200 300 400 500 OPERATING FREQUENCY (kHz) 600 1736 F02 Figure 2. Timing Capacitor Value When synchronized to an external clock, Burst Mode operation is disabled but the inductor current is not allowed to reverse. The 25% minimum inductor current clamp present in Burst Mode operation is removed, providing constant frequency discontinuous operation over the widest possible output current range. In this mode the synchronous MOSFET is forced on once every 10 clock The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate-charge losses. In addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL decreases with higher inductance or frequency and increases with higher VIN or VOUT: ∆IL =  V  1 VOUT 1 – OUT  VIN  ( f)(L)  Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆IL = 0.3 to 0.4(IMAX). Remember, the maximum ∆IL occurs at the maximum input voltage. The inductor value also has an effect on low current operation. The transition to low current operation begins when the inductor current reaches zero while the bottom MOSFET is on. Burst Mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by RSENSE. Lower inductor values (higher ∆IL) will cause this to occur at higher load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to decrease. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, 11 LTC1736 U W U U APPLICATIO S I FOR ATIO molypermalloy or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on the inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Molypermalloy (from Magnetics, Inc.) is a very good, low loss core material for toroids, but it is more expensive than ferrite. A reasonable compromise from the same manufacturer is Kool Mµ. Toroids are very space efficient, especially when you can use several layers of wire. Because they generally lack a bobbin, mounting is more difficult. However, designs for surface mount are available that do not increase the height significantly. Power MOSFET and D1 Selection Two external power MOSFETs must be selected for use with the LTC1736: An N-channel MOSFET for the top (main) switch and an N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak gate drive levels are set by the INTVCC voltage. This voltage is typically 5.2V during start-up. (See EXTVCC Pin Connection.) Consequently, logic-level threshold MOSFETs must be used in most LTC1736 applications. The only exception is when low input voltage is expected (VIN < 5V); then, sublogic level threshold MOSFETs (VGS(TH) < 3V) should be used. Pay close attention to the BVDSS specification for the MOSFETs as well; most of the logic level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the “ON” resistance RDS(ON), reverse transfer capacitance CRSS, input voltage and maximum output current. When the LTC1736 is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: 12 Main Switch Duty Cycle = VOUT VIN Synchronous Switch Duty Cycle = VIN – VOUT VIN The MOSFET power dissipations at maximum output current are given by: ( ) (1+ δ)R + k(V ) (I )(C )( f) V –V = (I ) (1+ δ)R V PMAIN = VOUT IMAX VIN 2 DS(ON) 2 IN PSYNC IN MAX OUT RSS 2 MAX DS(ON) IN where δ is the temperature dependency of RDS(ON) and k is a constant inversely related to the gate drive current. Both MOSFETs have I2R losses while the topside N-Channel equation includes an additional term for transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage or during a short circuit when the duty cycle in this switch is nearly 100%. The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs Temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. CRSS is usually specified in the MOSFET characteristics. The constant k = 1.7 can be used to estimate the contributions of the two terms in the main switch dissipation equation. The Schottky diode D1 shown in Figure 1 conducts during the dead-time between the conduction of the two power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on and storing charge during the dead-time, which could cost as much as 1% in efficiency. A 3A Schottky is generally a good size for 10A to 12A regulators due to the relatively small average current. Kool Mµ is a registered trademark of Magnetics, Inc. LTC1736 U W U U APPLICATIO S I FOR ATIO Larger diodes can result in additional transition losses due to their larger junction capacitance. The diode may be omitted if the efficiency loss can be tolerated. CIN Selection In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT/ VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by:  V  V IRMS ≅ IO(MAX ) OUT  IN – 1 VIN  VOUT  1/ 2 This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. COUT Selection The selection of COUT is primarily determined by the effective series resistance (ESR) to minimize voltage ripple. The output ripple (∆VOUT) in continuous mode is determined by:  1  ∆VOUT ≈ ∆IL  ESR +  8 fCOUT   Where f = operating frequency, COUT = output capacitance, and ∆IL = ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. With ∆IL = 0.3IOUT(MAX) the output ripple will be less than 50mV at max VIN assuming: COUT required ESR < 2.2 RSENSE COUT > 1/(8fRSENSE) The first condition relates to the ripple current into the ESR of the output capacitance while the second term guarantees that the output capacitance does not significantly discharge during the operating frequency period due to ripple current. The choice of using smaller output capacitance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low ESR to maintain the ripple voltage at or below 50mV. The ITH pin OPTI-LOOP compensation components can be optimized to provide stable, high performance transient response regardless of the output capacitors selected. The selection of output capacitors for CPU or other applications with large load current transients is primarily determined by the voltage tolerance specifications of the load. The resistive component of the capacitor, ESR, multiplied by the load current change plus any output voltage ripple must be within the voltage tolerance of the load (CPU). The required ESR due to a load current step is: RESR < ∆V/∆I where ∆I is the change in current from full load to zero load (or minimum load) and ∆V is the allowed voltage deviation (not including any droop due to finite capacitance). The amount of capacitance needed is determined by the maximum energy stored in the inductor. The capacitance must be sufficient to absorb the change in inductor current when a high current to low current transition occurs. The opposite load current transition is generally determined by the control loop OPTI-LOOP components, so make sure not to over compensate and slow down the response. The minimum capacitance to assure the inductors’ energy is adequately absorbed is: ( ) COUT > 2( ∆V )VOUT L ∆I 2 where ∆I is the change in load current. 13 LTC1736 U W U U APPLICATIO S I FOR ATIO Manufacturers such as Nichicon, United Chemicon and Sanyo can be considered for high performance throughhole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest (ESR)(size) product of any aluminum electrolytic at a somewhat higher price. An additional ceramic capacitor in parallel with OS-CON capacitors is recommended to reduce the inductance effects. In surface mount applications multiple capacitors may need to be used in parallel to meet the ESR, RMS current handling, and load step requirements of the application. Aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. Special polymer surface mount capacitors offer very low ESR but have much lower capacitive density per unit volume than other capacitor types. These capacitors offer a very cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. Tantalum capacitors offer the highest capacitance density and are often used as output capacitors for switching regulators having controlled soft-start. Several excellent surge-tested choices are the AVX TPS, AVX TPSV or the KEMET T510 series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors can be used in cost-driven applications providing that consideration is given to ripple current ratings, temperature and long-term reliability. A typical application will require several to many aluminum electrolytic capacitors in parallel. A combination of the above mentioned capacitors will often result in maximizing performance and minimizing overall cost. Other capacitor types include Nichicon PL series, NEC Neocap, Panasonic SP and Sprague 595D series. Consult manufacturers for other specific recommendations. Like all components, capacitors are not ideal. Each capacitor has its own benefits and limitations. Combinations of different capacitor types have proven to be a very cost effective solution. Remember also to include high frequency decoupling capacitors. They should be placed as close as possible to the power pins of the load. Any inductance present in the circuit board traces negates their usefulness. 14 INTVCC Regulator An internal P-channel low dropout regulator produces the 5.2V supply that powers the drivers and internal circuitry within the LTC1736. The INTVCC pin can supply a maximum RMS current of 50mA and must be bypassed to ground with a minimum of 4.7µF tantalum, 10µF special polymer or low ESR type electrolytic capacitor. Good bypassing is required to supply the high transient currents required by the MOSFET gate drivers. Higher input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC1736 to be exceeded. The system supply current is normally dominated by the gate charge current. Additional loading of INTVCC also needs to be taken into account for the power dissipation calculations. The total INTVCC current can be supplied by either the 5.2V internal linear regulator or by the EXTVCC input pin. When the voltage applied to the EXTVCC pin is less than 4.7V, all of the INTVCC current is supplied by the internal 5.2V linear regulator. Power dissipation for the IC in this case is highest: (VIN)(IINTVCC), and overall efficiency is lowered. The gate charge is dependent on operating frequency as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equations given in Note 2 of the Electrical Characteristics. For example, the LTC1736G is limited to less than 17mA from a 30V supply when not using the EXTVCC pin as follows: TJ = 70°C + (17mA)(30V)(110°C/W) = 126°C Use of the EXTVCC input pin reduces the junction temperature to: TJ = 70°C + (17mA)(5V)(110°C/W) = 79°C To prevent maximum junction temperature from being exceeded, the input supply current must be checked operating in continuous mode at maximum VIN. EXTVCC Connection The LTC1736 contains an internal P-channel MOSFET switch connected between the EXTVCC and INTVCC pins. Whenever the EXTVCC pin is above 4.7V the internal 5.2V LTC1736 U W U U APPLICATIO S I FOR ATIO regulator shuts off, the switch closes and INTVCC power is supplied via EXTVCC until EXTVCC drops below 4.5V. This allows the MOSFET gate drive and control power to be derived from the output or other external source during normal operation. When the output is out of regulation (start-up, short circuit) power is supplied from the internal regulator. Do not apply greater than 7V to the EXTVCC pin and ensure that EXTVCC < VIN. Significant efficiency gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Efficiency). For 5V regulators this simply means connecting the EXTVCC pin directly to VOUT. However, for VID programmed regulators and other lower voltage regulators, additional circuitry is required to derive INTVCC power from the output. The following list summarizes the three possible connections for EXTVCC: 1. EXTVCC Left Open (or Grounded). This will cause INTVCC to be powered from the internal 5.2V regulator resulting in a low current efficiency penalty of up to 10% at high input voltages. 2. EXTVCC Connected to an External Supply (this option is the most likely used). If an external supply is available in the 5V to 7V range, such as notebook main 5V system power, it may be used to power EXTV CC providing it is compatible with the MOSFET gate drive requirements. This is the typical case as the 5V power is almost always present and is derived by another high efficiency regulator. 3. EXTVCC Connected to an Output-Derived Boost Network. For this low output voltage regulator, efficiency gains can still be realized by connecting EXTVCC to an output-derived voltage that has been boosted to greater than 4.7V. This can be done with either the inductive boost winding or the capacitive charge pump circuits. Refer to the LTC1735 data sheet for details. The charge pump has the advantage of simple magnetics. Output Voltage Programming The output voltage is digitally set to levels between 0.925V and 2.00V using the voltage identification (VID) inputs VID0 to VID4. The internal 5-bit DAC configured as a precision resistive voltage divider sets the output voltage in 50mV or 25mV increments according to Table 1. The VID codes (00000-11110) are engineered to be compatible with Intel Mobile Pentium II and Pentium III processor specifications for output voltages from 0.925V to 2.00V. The LSB (VID0) represents 50mV increments in the upper voltage range (1.30V to 2.00V) and 25mV increments in the lower voltage range (0.925V to 1.275V). The MSB is VID4. When all bits are low, or grounded, the output voltage is 2.00V. Between the VFB pin and ground is a variable resistor, R1, whose value is controlled by the five input pins (VID0 to VID4). Another resistor, R2, between the VOSENSE and the VFB pins completes the resistive divider. The output voltage is thus set by the ratio of (R1 + R2) to R1. The LTC1736 has remote sense capability. The top of the internal resistive divider is connected to VOSENSE, and it is referenced to the SGND pin. This allows a kelvin connection for remotely sensing the output voltage directly across the load, eliminating any PC board trace resistance errors. Each VID digital input is pulled up by a 40k resistor in series with a diode from VIDVCC. Therefore, it must be grounded to get a digital low input, and can be either floated or connected to VIDVCC to get a digital high input. The series diode is used to prevent the digital inputs from being damaged or clamped if they are driven higher than VIDVCC. The digital inputs accept CMOS voltage levels. VIDVCC is the supply voltage for the VID section. It is normally connected to INTVCC but can be driven from other sources such as a 3.3V supply. If it is driven from another source, that source MUST be in the range of 2.7V to 5.5V and MUST be alive prior to enabling the LTC1736. 15 LTC1736 U U W U APPLICATIO S I FOR ATIO Topside MOSFET Driver Supply (CB, DB) Table 1. VID Output Voltage Programming VID4 VID3 VID2 VID1 VID0 VOUT (V) 0 0 0 0 0 2.000V 0 0 0 0 1 1.950V 0 0 0 1 0 1.900V 0 0 0 1 1 1.850V 0 0 1 0 0 1.800V 0 0 1 0 1 1.750V 0 0 1 1 0 1.700V 0 0 1 1 1 1.650V 0 1 0 0 0 1.600V 0 1 0 0 1 1.550V 0 1 0 1 0 1.500V 0 1 0 1 1 1.450V 0 1 1 0 0 1.400V 0 1 1 0 1 1.350V 0 1 1 1 0 1.300V 0 1 1 1 1 * 1 0 0 0 0 1.275V 1 0 0 0 1 1.250V 1 0 0 1 0 1.225V 1 0 0 1 1 1.200V 1 0 1 0 0 1.175V 1 0 1 0 1 1.150V 1 0 1 1 0 1.125V 1 0 1 1 1 1.100V 1 1 0 0 0 1.075V 1 1 0 0 1 1.050V 1 1 0 1 0 1.025V 1 1 0 1 1 1.000V 1 1 1 0 0 0.975V 1 1 1 0 1 0.950V 1 1 1 1 0 0.925V 1 1 1 1 1 ** Note: *, ** represents codes without a defined output voltage as specified in Intel specifications. The LTC1736 interprets these codes as valid inputs and produces output voltages as follows: [01111] = 1.250V, [11111] = 0.900V. 16 An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. Capacitor CB in the Functional Diagram is charged though external diode DB from INTVCC when the SW pin is low. Note that the voltage across CB is about a diode drop below INTVCC. When the topside MOSFET is to be turned on, the driver places the CB voltage across the gate-source of the MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage SW rises to VIN and the BOOST pin rises to VIN + INTVCC. The value of the boost capacitor CB needs to be 100 times greater than the total input capacitance of the topside MOSFET. In most applications 0.1µF to 0.33µF is adequate. The reverse breakdown on DB must be greater than VIN(MAX) . When adjusting the gate drive level, the final arbiter is the total input current for the regulator. If you make a change and the input current decreases, then you improve the efficiency. If there is no change in input current, then there is no change in efficiency. SENSE +/SENSE – Pins The common mode input range of the current comparator is from 0V to 1.1(INTVCC). Continuous linear operation is guaranteed throughout this range allowing output voltages anywhere from 0.8V to 7V (although the VID control pins only program a 0.925V to 2.00V output range). A differential NPN input stage is used and is biased with internal resistors from an internal 2.4V source as shown in the Functional Diagram. This causes current to flow out of both sense pins to the main output. This forces a minimum load current which is sunk by the internal resistive divider resistors R1 and R2. The maximum current flowing out of the sense pins is: ISENSE + + ISENSE – = (2.4V – VOUT)/24k Remember to take this current into account if resistance is placed in series with the sense pins for filtering. LTC1736 U W U U APPLICATIO S I FOR ATIO Soft-Start/Run Function Fault Conditions: Overcurrent Latchoff The RUN/SS pin is a multipurpose pin that provides a softstart function and a means to shut down the LTC1736. Soft-start reduces surge currents from VIN by gradually increasing the controller’s current limit ITH(MAX). This pin can also be used for power supply sequencing. The RUN/SS pin also provides the ability to shut off the controller and latchoff when an overcurrent condition is detected. The RUN/SS capacitor CSS is used initially to turn on and limit the inrush current of the controller. After the controller has been started and given adequate time to charge up the output capacitor and provide full load current, CSS is used as a short-circuit timer. If the output voltage falls to less than 70% of its nominal output voltage after CSS reaches 4.1V, the assumption is made that the output is in a severe overcurrent and/or short-circuit condition and CSS begins discharging. If the condition lasts for a long enough period as determined by the size of CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. Pulling the RUN/SS pin below 1.5V puts the LTC1736 into a low quiescent current shutdown (IQ < 25µA). This pin can be driven directly from logic as shown in Figure 3. Releasing the RUN/SS pin allows an internal 1.2µA current source to charge up the external soft-start capacitor CSS. If RUN/SS has been pulled all the way to ground there is a delay before starting of approximately: t DELAY = ( ) 1.5V CSS = 1.25s / µF CSS 1.2µA When the voltage on RUN/SS reaches 1.5V the LTC1736 begins operating with a current limit at approximately 25mV/RSENSE. As the voltage on RUN/SS increases from 1.5V to 3.0V, the internal current limit is increased from 25mV/RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking an additional 1.25s/µF to reach full current. The output current thus ramps up slowly reducing the starting surge current required from the input power supply. Diode D1 in Figure 3 reduces the start delay while allowing CSS to charge up slowly for the soft-start function. This diode and CSS can be deleted if soft-start is not needed. The RUN/SS pin has an internal 6V zener clamp (See Functional Diagram). 3.3V OR 5V RUN/SS RUN/SS D1 This built-in latchoff can be overridden by providing a current > 5µA at a compliance of 5V to the RUN/SS pin as shown in Figure 4. This current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. When deriving the 5µA current from VIN as in Figure 4a, current latchoff is always defeated. A diode connecting this pull-up resistor to INTVCC , as in Figure 4b, eliminates any extra supply current during controller shutdown while eliminating the INTVCC loading from preventing controller start-up. If the voltage on CSS does not exceed 4.1V, the overcurrent latch is not armed and the function is disabled. INTVCC RSS VIN 3.3V OR 5V RUN/SS D1 D1 CSS CSS CSS CSS 1736 F03 (a) (b) Figure 3. RUN/SS Pin Interfacing RUN/SS RSS (a) (b) 1736 F04 Figure 4. RUN/SS Pin Interfacing with Latchoff Defeated 17 LTC1736 U W U U APPLICATIO S I FOR ATIO Why should you defeat overcurrent latchoff? During the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit to latch off. Defeating this feature will easily allow troubleshooting of the circuit and PC layout. The internal shortcircuit and foldback current limiting still remains active, thereby protecting the power supply system from failure. After the design is complete, a decision can be made whether to enable the latchoff feature. The value of the soft-start capacitor CSS will need to be scaled with output voltage, output capacitance and load current characteristics. The minimum soft-start capacitance is given by: CSS > (COUT )(VOUT)(10 – 4)(RSENSE) The minimum recommended soft-start capacitor of CSS = 0.1µF will be sufficient for most applications. Fault Conditions: Current Limit and Current Foldback The LTC1736 current comparator has a maximum sense voltage of 75mV resulting in a maximum MOSFET current of 75mV/RSENSE. The LTC1736 includes current foldback to help further limit load current when the output is shorted to ground. The foldback circuit is active even when the overload shutdown latch described above is defeated. If the output falls by more than half, then the maximum sense voltage is progressively lowered from 75mV to 30mV. Under short-circuit conditions with very low duty cycle, the LTC1736 will begin cycle skipping in order to limit the short-circuit current. In this situation the bottom MOSFET will be conducting the peak current. The short-circuit ripple current is determined by the minimum on-time tON(MIN) of the LTC1736 (less than 200ns), the input voltage, and inductor value: ∆IL(SC) = tON(MIN) VIN /L. 18 The resulting short circuit current is: ISC = 30mV 1 + ∆IL(SC) RSENSE 2 The current foldback function is always active and is not effected by the current latchoff function. Fault Conditions: Output Overvoltage Protection (Crowbar) The output overvoltage crowbar is designed to blow a system fuse in the input lead when the output of the regulator rises much higher than nominal levels. This condition causes huge currents to flow, much greater than in normal operation. This feature is designed to protect against a shorted top MOSFET; it does not protect against a failure of the controller itself. The comparator (OV in the Functional Diagram) detects overvoltage faults greater than 7.5% above the nominal output voltage. When this condition is sensed, the top MOSFET is turned off and the bottom MOSFET is forced on. The bottom MOSFET remains on continuously for as long as the OV condition persists; if VOUT returns to a safe level, normal operation automatically resumes. Note that VID controlled output voltage decreases may cause the overvoltage protection to be momentarily activated. This will not cause permanent latchoff nor will it disrupt the desired voltage change. With soft-latch overvoltage protection, dynamic VID code changes are allowed and the overvoltage protection tracks the new VID code, always protecting the load (CPU). If dynamic VID code changes are anticipated and the minimum load current is light, it may be necessary to either force continuous operation by pulling FCB low during the transition to maximize current sinking capability or connect PGOOD to FCB to automatically force continuous operation during VID transitions. LTC1736 U W U U APPLICATIO S I FOR ATIO Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest amount of time that the LTC1736 is capable of turning the top MOSFET on and off again. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. Low duty cycle applications may approach this minimum ontime limit and care should be taken to ensure that: tON(MIN) < VOUT VIN( f) If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC1736 will begin to skip cycles. The output voltage will continue to be regulated, but the ripple current and voltage will increase. The minimum on-time for the LTC1736 in a properly configured application is generally less than 200ns. However, as the peak sense voltage decreases, the minimum on-time gradually increases as shown in Figure 5. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. If an application can operate close to the minimum ontime limit, an inductor must be chosen that is low enough in value to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule keep the 250 MINIMUM ON-TIME (ns) FCB Pin Operation When the DC voltage on the FCB pin drops below its 0.8V threshold, continuous mode operation is forced. In this case, the top and bottom MOSFETs continue to be driven synchronously regardless of the load on the main output. Burst Mode operation is disabled and current reversal is allowed in the inductor. In addition to providing a logic input to force continuous synchronous operation and external synchronization, the FCB pin provides a means to regulate a flyback winding output. During continuous mode, current flows continuously in the transformer primary. The secondary winding(s) draw current only when the bottom synchronous switch is on. When primary load currents are low and/or the VIN/VOUT ratio is low, the synchronous switch may not be on for a sufficient amount of time to transfer power from the output capacitor to the secondary load. Forced continuous operation will support secondary windings provided there is sufficient synchronous switch duty factor. Thus, the FCB input pin removes the requirement that power must be drawn from the inductor primary in order to extract power from the auxiliary windings. With the loop in continuous mode, the auxiliary output may nominally be loaded without regard to the primary output load. The secondary output voltage VSEC is normally set as shown in the Functional Diagram by the turns ratio N of the transformer: VSEC ≅ (N + 1) VOUT 200 However, if the controller goes into Burst Mode operation and halts switching due to a light primary load current, then VSEC will droop. An external resistive divider from VSEC to the FCB pin sets a minimum voltage VSEC(MIN): 150 100  R4  VSEC(MIN) ≈ 0.8 V 1 +   R3  50 0 inductor ripple current equal or greater than 30% of IOUT(MAX) at VIN(MAX). 0 10 20 30 40 ∆IL /IOUT(MAX) (%) 1736 F05 Figure 5. Minimum On-Time vs ∆IL If VSEC drops below this level, the FCB voltage forces continuous switching operation until VSEC is again above its minimum. 19 LTC1736 U W U U APPLICATIO S I FOR ATIO In order to prevent erratic operation if no external connections are made to the FCB pin, the FCB pin has a 0.17µA internal current source pulling the pin high. Remember to include this current when choosing resistor values R3 and R4. The internal LTC1736 oscillator can be synchronized to an external oscillator by clocking the FCB pin with a signal above 1.5VP-P. When synchronized to an external frequency, Burst Mode operation is disabled, but cycle skipping is allowed at low load currents since current reversal is inhibited. The bottom gate will come on every 10 clock cycles to assure the boostrap cap, CB, is kept refreshed. The rising edge of an external clock applied to the FCB pin starts a new cycle. The range of synchronization is from 0.9fO to 1.3fO, with fO set by COSC. Attempting to synchronize to a higher frequency than 1.3fO can result in inadequate slope comensation and cause loop instability with high duty cycles. If loop instability is observed while synchronized, additional slope compensation can be obtained by simply decreasing COSC. The following table summarizes the possible states available on the FCB pin: Table 2 FCB Pin Condition DC Voltage: 0V to 0.7V Burst Disabled/Forced Continuous Current Reversal Enabled DC Voltage: > 0.9V Burst Mode Operation, No Current Reversal Feedback Resistors Regulating a Secondary Winding Ext Clock: (0V to VFCBSYNC) Burst Mode Operation Disabled (VFCBSYNC ≥ 1.5V) No Current Reversal Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% - (L1 + L2 + L3 + ...) 20 where L1, L2, etc., are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC1736 circuits: 1) LTC1736 VIN current, 2) INTVCC current, 3) I2R losses, 4) Topside MOSFET transition losses. 1. The VIN current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. VIN current results in a small (< 0.1%) loss that increases with VIN. 2. INTVCC current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the control circuit current. In continuous mode, IGATECHG = f(QT + QB), where QT and QB are the gate charges of the topside and bottom-side MOSFETs. Supplying INTVCC power through the EXTVCC switch input from an output-derived or other high efficiency source will scale the VIN current required for the driver and control circuits by a factor of (Duty Cycle)/(Efficiency). For example, in a 15V to 1.8V application, 10mA of INTVCC current results in approximately 1.2mA of VIN current. This reduces the low current loss from 10% or more (if the driver was powered directly from VIN) to only a few percent. 3. I2R Losses are predicted from the DC resistances of the MOSFETs, inductor and current shunt. In continuous mode the average output current flows through L and RSENSE, but is “chopped” between the topside main MOSFET and the synchronous MOSFET. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and RSENSE to obtain I2R losses. For example, if each RDS(ON) = 0.02Ω, RL = 0.03Ω, and RSENSE = 0.01Ω, then the total resistance is LTC1736 U W U U APPLICATIO S I FOR ATIO 0.06Ω. This results in losses ranging from 3% to 17% as the output current increases from 1A to 5A for a 1.8V output, or 4% to 20% for a 1.5V output. Efficiency varies as the inverse square of VOUT for the same external components and power level. I2R losses cause the efficiency to drop at high output currents. 4. Transition losses apply only to the topside MOSFET(s), and only become significant when operating at high input voltages (typically 12V or greater). Transition losses can be estimated from: Transition Loss = (1.7)(VIN2)(IO(MAX))(CRSS)(f) Other “hidden” losses such as copper trace and internal battery resistances can account for an additional 5% to 10% efficiency degradation in portable systems. It is very important to include these “system” level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. A 25W supply will typically require a minimum of 20µF to 40µF of capacitance having a maximum of 0.01Ω to 0.02Ω of ESR. Other losses including Schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD (ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. OPTILOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC coupled and AC filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full-load current having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second-order overshoot/DC ratio cannot be used determine phase margin. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreasing CC. If RC is increased by the same factor that CC is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Application Note 76. Improve Transient Response and Reduce Output Capacitance with Active Voltage Positioning Fast load transient response, limited board space and low cost are requirements of microprocessor power supplies. Active voltage positioning improves transient response and reduces the output capacitance required to power a microprocessor where a typical load step can be from 0.2A 21 LTC1736 U U W U APPLICATIO S I FOR ATIO to 15A in 100ns or 15A to 0.2A in 100ns. The voltage at the microprocessor must be held to about ±0.1V of nominal in spite of these load current steps. Since the control loop cannot respond this fast, the output capacitors must supply the load current until the control loop can respond. Capacitor ESR and ESL primarily determine the amount of droop or overshoot in the output voltage. Normally, several capacitors in parallel are required to meet microprocessor transient requirements. Active voltage positioning is a form of deregulation. It sets the output voltage high for light loads and low for heavy loads. When load current suddenly increases, the output voltage starts from a level higher than nominal so the output voltage can droop more and stay within the specified voltage range. When load current suddenly decreases the output voltage starts at a level lower than nominal so the output voltage can have more overshoot and stay within the specified voltage range. Less output capacitance is required when voltage positioning is used because more voltage variation is allowed on the output capacitors. Active voltage positioning can be implemented using the OPTI-LOOP architecture of the LTC1736 with two external resistors. An input voltage offset is introduced when the error amplifier has to drive a resistive load. This offset is limited to ±30mV at the input of the error amplifier. The resulting change in output voltage is the product of input offset and the feedback voltage divider ratio. Figure 6 shows a CPU-core-voltage regulator with active voltage positioning. Resistors R1 and R5 force the input voltage offset that sets the output voltage according to the load current level. To select values for R1 and R5, first determine the amount of output deregulation allowed. The actual specification for a typical microprocessor allows the output to vary ±0.112V. The LTC1736 output voltage R3 680k R4 100k POWER GOOD R1 27k C1 39pF R2 100k R5 100k 1 C2 0.1µF 2 C3 100pF C4 100pF 3 4 5 C5 1000pF C6 47pF 6 7 8 9 C7 330pF VID0 VID1 C8 0.1µF 10 11 12 COSC TG RUN/SS BOOST ITH FCB SW LTC1736 SGND VIN INTVCC PGOOD BG SENSE – PGND SENSE + EXTVCC VFB VIDVCC VOSENSE VID4 VID0 VID3 VID1 VID2 24 23 20 L1 1µH D1 CMDSH-3 19 18 17 16 15 + C10 1µF GND M1 FDS6680A C9 0.22µF 22 21 C11 4.7µF 10V M2, M3 FDS6680A ×2 R6 0.003Ω + D2 MBRS340 14 13 VID3 1736 F06 C10, C18: TAIYO YUDEN JMK107BJ105 C11: KEMET T494A475M010AS C12 TO C14: TAIYO YUDEN GMK325F106 C15 TO C17: PANASONIC EEFUE0G181R D1: CENTRAL SEMI CMDSH-3 D2: MOTOROLA MBRS340 L1: PANASONIC ETQP6F1R0SA M1 TO M3: FAIRCHILD FDS6680A R6: IRC LRF2512-01-R003-J U1: LINEAR TECHNOLOGY LTC1736CG Figure 6. CPU-Core-Voltage Regulator with Active Voltage Positioning 22 VOUT 0.9V TO 2V 15A C15 TO C17 180µF/4V ×4 C18 1µF GND 5V (OPTIONAL) VID2 VID4 VID INPUT VIN 7.5V TO 24V C12 TO C14 10µF 35V LTC1736 U W U U APPLICATIO S I FOR ATIO accuracy is ±1%, so the output transient voltage cannot exceed ±0.097V. At VOUT = 1.5V, the maximum output voltage change controlled by the ITH pin would be: Input Offset • VOUT VREF ± 0.03V • 1.5 = = ±56mV 0.8 V ∆VOSENSE = With optimum resistor values at the ITH pin, the output voltage will swing from 1.55V at minimum load to 1.44V at full load. At this output voltage, active voltage positioning provides an additional 56mV to the allowable transient voltage on the output capacitors, a 58% improvement over the 97mV allowed without active voltage positioning. The next step is to calculate the ITH pin voltage, VITH, scale factor. The VITH scale factor reflects the ITH pin voltage required for a given load current. VITH controls the peak sense resistor voltage, which represents the DC output current plus one half of the peak-to-peak inductor current. The no load to full load VITH range is from 0.3V to 2.4V, which controls the sense resistor voltage from 0V to the ∆VSENSE(MAX) voltage of 75mV. The calculated VITH scale factor with a 0.003Ω sense resistor is: VITH Scale Factor = = VITH Range • Sense Re sistor Value ∆VSENSE(MAX) (2.4V – 0.3V) • 0.003 = 0.084V/A 0.075V VITH at any load current is:   ∆I  VITH = IOUT(DC) + L  • VITH Scale Factor  2    + VITH Offset At full load current:    5A VITH(MAX) =  15A + P−P  • 0.084V/A  + 0.3V 2    = 1.77 V At minimum load current:    2A VITH(MIN) =  0.2A + P−P  • 0.084V/A  + 0.3V 2    = 0.40 V In this circuit, VITH changes from 0.40V at light load to 1.77V at full load, a 1.37V change. Notice that ∆IL, the peak-to-peak inductor current, changes from light load to full load. Increasing the DC inductor current decreases the permeability of the inductor core material, which decreases the inductance and increases ∆IL. The amount of inductance change is a function of the inductor design. To create the 30mV input offset, the gain of the error amplifier must be limited. The desired gain is: AV = ∆VITH 1.37 V = = 22.8 Input Offset 2(0.03V) Connecting a resistor to the output of the transconductance error amplifier will limit the voltage gain. The value of this resistor is: RITH = AV 22.8 = = 17.54k Error Amplifier gm 1.3ms To center the output voltage variation, VITH must be centered so that no ITH pin current flows when the output voltage is nominal. VITH(NOM) is the average voltage between VITH at maximum output current and minimum output current: VITH(MAX) – VITH(MIN) + VITH(MIN) 2 1.77 V – 0.40 V = + 0.40 V = 1.085V 2 VITH(NOM) = The Thevenin equivalent of the gain limiting resistance value of 17.54k is made up of a resistor R5 that sources current into the ITH pin and resistor R1 that sinks current to SGND. 23 LTC1736 U W U U APPLICATIO S I FOR ATIO To calculate the resistor values, first determine the ratio between them: VINTVCC – VITH(NOM) 5.2V – 1.085V k= = = 3.79 VITH(NOM) 1.085V VINTVCC is equal to VEXTVCC or 5.2V if EXTVCC is not used. Resistor R1 is: Unfortunately, PCB noise can add to the voltage developed across the sense resistor, R6, causing the ITH pin voltage to be slightly higher than calculated for a given output current. The amount of noise is proportional to the output current level. This PCB noise does not present a serious problem but it does change the effective value of R6 so the calculated values of R1 and R5 may need to be adjusted to achieve the required results. Since PCB noise is a function of the layout, it will be the same on all boards with the same layout. Figures 7 and 8 show the transient response before and after active voltage positioning is implemented. Notice that the output voltage droop and overshoot levels don’t change but the peak-to-peak output voltage reduces considerably with active voltage positioning. Refer to Design Solutions 10 for more information about active voltage positioning. FIGURE 6 CIRCUIT OUTPUT VOLTAGE 15A LOAD CURRENT 10A/DIV 0A 50µs/DIV 1736 F07 Figure 7. Normal Transient Response (Without R1, R5) 24 OUTPUT VOLTAGE 1.418V 15A LOAD CURRENT 50µs/DIV 1736 F08 Figure 8. Transient Response with Active Voltage Positioning (k + 1) • RITH (3.79 + 1) • 17.54k = = 22.17k k 3.79 1.5V 100mV/DIV FIGURE 6 CIRCUIT 0A R4 = (k + 1) • RITH = (3.79 + 1) • 17.54k = 84.0k VIN = 12V VOUT = 1.5V 1.582V 100mV/DIV 1.5V 10A/DIV Resistor R5 is: R1 = VIN = 12V VOUT = 1.5V Automotive Considerations: Plugging into the Cigarette Lighter As battery-powered devices go mobile, there is a natural interest in plugging into the cigarette lighter in order to conserve or even recharge battery packs during operation. But before you connect, be advised: you are plugging into the supply from hell. The main power line in an automobile is the source of a number of nasty potential transients, including load dump, reverse battery, and double battery. Load dump is the result of a loose power cable. When the cable breaks connection, the field collapse in the alternator can cause a positive spike as high as 60V which takes several hundred milliseconds to decay. Reverse battery is just what it says, while double battery is a consequence of tow truck operators finding that a 24V jump start cranks cold engines faster than 12V. The network shown in Figure 9 is the most straight forward approach to protect a DC/DC converter from the ravages of an automotive power line. The series diode prevents current from flowing during reverse battery, while the transient suppressor clamps the input voltage during load dump. Note that the transient suppressor should not conduct during double-battery operation, but must still clamp the input voltage below breakdown of the converter. Although the LTC1736 has a maximum input voltage of 36V, most applications will be limited to 30V by the MOSFET BVDSS. LTC1736 U U W U APPLICATIO S I FOR ATIO in: RDS(ON) = 0.03Ω, CRSS = 80pF. At maximum input voltage with T(estimated) = 50°C: 50A IPK RATING VIN 12V LTC1736 TRANSIENT VOLTAGE SUPPRESSOR GENERAL INSTRUMENT 1.5KA24A PMAIN = 1736 F09 Figure 9. Plugging into the Cigarette Lighter Design Example As a design example, assume VIN = 12V(nominal), VIN = 22V(max), VOUT = 1.6V(nominal), 1.8V to 1.3V range, IMAX = 12A and f = 275kHz. RSENSE and COSC can immediately be calculated: RSENSE = 50mV/12A = 0.0042Ω COSC = 1.61(107)/(275kHz) – 11pF = 47pF Assume a 1.2µH inductor and check the actual value of the ripple current. The following equation is used :  V  V ∆IL = OUT  1 – OUT  ( f)(L)  VIN  The highest value of the ripple current occurs at the maximum input and output voltages:  1.8 V  1.8 V ∆IL =  1–  = 5A 275kHz(1.2µH)  22V  The maximum ripple current is 42% of maximum output current, which is about right. Next, verify the minimum on-time of 200ns is not violated. The minimum on-time occurs at maximum VIN and minimum VOUT. tON(MIN) = VOUT () VIN(MAX) f = 1.3V = 215ns 22V(275kHz) The power dissipation on the topside MOSFET can be easily estimated. Choosing a Fairchild FDS6612A results ( ) [1+ (0.005)(50°C – 25°C)](0.03Ω) 2 +1.7(22V ) (12A )(80pF ) (275kHz) 1.6 V 12 22V 2 = 571mW Because the duty cycle of the bottom MOSFET is much greater than the top, two larger MOSFETs must be paralleled. Choosing Fairchild FDS6680A MOSFETs yields a parallel RDS(ON) of 0.0065Ω. The total power dissipaton for both bottom MOSFETs, again assuming T = 50°C, is: ( ) (1.1)(0.0065Ω) 22V – 1.6 V 12A 22V = 955mW PSYNC = 2 Thanks to current foldback, the bottom MOSFET dissipaton in short circuit will be less than under full-load conditions. CIN is chosen for an RMS current rating of at least 6A at temperature. COUT is chosen with an ESR of 0.01Ω for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR(∆IL) = 0.01Ω(5A) = 50mVP-P PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1736. These items are also illustrated graphically in the layout diagram of Figure 10. Check the following in your layout: 1. Are the signal and power grounds segregated? The LTC1736 PGND pin should tie to the GND plane close to the input capacitor. The SGND pin should then connect to PGND and all components that connect to SGND should make a single point tie to the SGND pin. The low side FET source pins should connect directly to the input capacitor ground. 25 LTC1736 U U W U APPLICATIO S I FOR ATIO 5. Is the INTVCC decoupling capacitor connected closely between INTVCC and the power ground pin? This capacitor carries the MOSFET driver peak currents. An additional 1µF ceramic capacitor placed immediately next to the INTVCC and PGND pins can help improve noise performance. 2. Does the VOSENSE pin connect as close as possible to the load? The optional 50pF to 100pF capacitor from VFB to SGND should be as close as possible to the LTC1736. 3. Are the SENSE – and SENSE + leads routed together with minimum PC trace spacing? The filter capacitor between SENSE + and SENSE – should be as close as possible to the LTC1736. Ensure accurate current sensing with kelvin connections as shown in Figure 11. Series resistance can be added to the SENSE lines to increase noise rejection. 6. Keep the switching node (SW), Top Gate node (TG) and Boost node (BOOST) away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. All of these nodes have very large and fast moving signals and therefore should be kept on the “output side” (Pins 13 to 24) of the LTC1736 and occupy minimum PC trace area. 4. Does the (+) terminal of CIN connect to the drain of the topside MOSFET(s) as closely as possible? This capacitor provides the AC current to the MOSFET(s). + COSC RC 2 CC1 CC2 3 4 5 47pF 1000pF 6 TG COSC RUN/SS BOOST ITH SW FCB LTC1736 SGND VIN INTVCC PGOOD BG 7 SENSE – PGND 8 SENSE + EXTVCC VFB VIDVCC 9 10 11 12 VOSENSE VID4 VID0 VID3 VID1 VID2 24 M1 23 CIN + 1 CSS 22 D1 21 20 M2 + 19 VIN CB DB 4.7µF 18 – 17 EXTERNAL EXTVCC CONNECTION 16 15 14 L1 13 – COUT VOUT RSENSE + + 1736 F10 Figure 10. LTC1736 Layout Diagram HIGH CURRENT PATH 1736 F11 SENSE + SENSE – CURRENT SENSE RESISTOR (RSENSE) Figure 11. Kelvin Sensing RSENSE 26 LTC1736 U PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. G Package 24-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 8.07 – 8.33* (0.318 – 0.328) 24 23 22 21 20 19 18 17 16 15 14 13 7.65 – 7.90 (0.301 – 0.311) 1 2 3 4 5 6 7 8 9 10 11 12 5.20 – 5.38** (0.205 – 0.212) 1.73 – 1.99 (0.068 – 0.078) 0° – 8° 0.13 – 0.22 (0.005 – 0.009) 0.55 – 0.95 (0.022 – 0.037) NOTE: DIMENSIONS ARE IN MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE 0.65 (0.0256) BSC 0.25 – 0.38 (0.010 – 0.015) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 0.05 – 0.21 (0.002 – 0.008) G24 SSOP 1098 27 LTC1736 U TYPICAL APPLICATIO 12A Converter with FCB Tied to PGOOD for CPU Power; Optimized for Output Voltages of 1.3V to 1.6V COSC 47pF 1 CSS 01.µF 2 RC 33k CC1 330pF CC2 47pF 3 4 5 100k 6 INTVCC 7 1000pF 8 47pF VIN 4.75V TO 24V PGOOD 9 10 11 12 TG COSC BOOST RUN/SS SW ITH FCB LTC1736 SGND VIN INTVCC PGOOD BG SENSE – PGND SENSE + EXTVCC VFB VIDVCC VOSENSE VID4 VID0 VID3 VID1 VID2 24 M1 FDS6680A 23 CB 0.22µF 22 20 19 + 17 15 CIN 22µF/30V ×2 OS-CON RSENSE 0.004Ω + 1µF 4.7µF 18 16 L1 1.2µH DB CMDSH-3 21 + M2 FDS6680A ×2 D1 MBRS340T3 OPTIONAL: CONNECT TO 5V VOUT 1.35V TO 1.6V 12A COUT 180µF/4V ×4 SGND 14 13 OUTPUT VOLTAGE PROGRAMMING 10Ω 10Ω 1736 TA02 COUT: 4-180µF/4V PANASONIC EEFUEOG181R (AS SHOWN) 3-470µF/6.3V KEMIT T51CX447M006AS (ALTERNATE) 1-820µF/4V SANYO 4SP820M + 1-180µF/4V PANASONIC EEFUE0G181R (ALTERNATE) CIN: SANYO OS-CON 305C22M L1: PANASONIC ETQP6RZ1RZ0HFA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1147 High Efficiency Step-Down Controller 100% DC, Burst Mode Operation, SO-8 LTC1148HV/LTC1148 High Efficiency Synchronous Step-Down Controllers 100% DC, Burst Mode Operation, VIN < 20V LTC1149 High Efficiency Synchronous Step-Down Controller 100% DC, Std Threshold MOSFETs, VIN < 48V LTC1159 High Efficiency Synchronous Step-Down Controller 100% DC, Logic Level MOSFETs, VIN < 40V LTC1265 1.2A Monolithic High Efficiency Step-Down Switching Regulator 100% DC, Burst Mode Operation, 14-Pin SO LT1375/LT1376 1.5A 500kHz Step-Down Switching Regulators High Efficiency, Constant Frequency, SO-8 LTC1435A High Efficiency Synchronous Step-Down Controller, N-Ch Drive Burst Mode Operation, 16-Pin Narrow SO LTC1436A/LTC1436A-PLL High Efficiency Low Noise Synchronous Step-Down Converters, N-Ch Drive Adaptive PowerTM Mode, 20-Pin/24-Pin SSOP LTC1474/LTC1475 Ultralow Quiescent Current Step-Down Monolithic Switching Regulators IQ = 10µA, 100% DC, 8-Pin MSOP LTC1625/LTC1775 No RSENSETM Current Mode Synchronous Step-Down Controllers Up to 97% Efficiency, Burst Mode Operation, 16-Pin SSOP LTC1628 Dual High Efficiency 2-Phase Step-Down Controller Antiphase Drive, 28-Pin SSOP Package LTC1703 550kHz Dual Output Synchronous Step-Down DC/DC Controller 5-Bit, Mobile VID On Output 1, No RSENSE LTC1735 High Efficiency Synchronous Step-Down Controller, N-Ch Drive Burst Mode Operation, 16-Pin Narrow SSOP LTC1735-1 High Efficiency Step-Down Controller with Power Good Output Fault Protection, 16-Pin SSOP and SO-8 Adaptive Power and No RSENSE are trademarks of Linear Technology Corporaton. 28 Linear Technology Corporation 1736f LT/TP 1299 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com  LINEAR TECHNOLOGY CORPORATION 1999