LTC3882IUJ#TRPBF

LTC3882 Dual Output PolyPhase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management DESCRIPTION FEATURES PMBus/I2C Compliant Serial Interface nn Monitor Voltage, Current, Temperature and Faults nn Digitally Programmable Voltage, Current Limit, Soft-Start/Stop, Sequencing, Margining, AVP and UV/OV Thresholds nn 3V ≤ VINSNS ≤ 38V, 0.5V ≤ V OUT ≤ 5.25V nn ±0.5% Output Voltage Accuracy nn Programmable PWM Frequency or External Clock Synchronization from 250kHz to 1.25MHz nn Accurate PolyPhase® Current Sharing nn Internal EEPROM with Fault Logging and ECC nn IC Supply Range: 3V to 13.2V nn Resistor or Inductor DCR Current Sensing nn Optional Resistor Programming for Key Parameters nn 40-Pin (6mm × 6mm) QFN Package nn AEC-Q100 Qualified for Automotive Applications The LTC®3882 is a dual, PolyPhase DC/DC synchronous step-down switching regulator controller with PMBus compliant serial interface. It uses a constant frequency, leading-edge modulation, voltage mode architecture for excellent transient response and output regulation. Each PWM channel can produce output voltages from 0.5V to 5.25V using a wide range of 3.3V compatible power stages, including power blocks, DrMOS or discrete FET drivers. Up to four LTC3882s can operate in parallel for 2-, 3-, 4-, 6- or 8-phase operation. nn LTC3882 system configuration and monitoring is supported by the LTpowerPlay® software tool. The device’s serial interface can be used to read back input voltage, output voltage and current, temperature and fault status. A wide range of operating parameters can be set via the digital interface or stored in internal EEPROM for use at power up. Switching frequency and phase, output voltage and device address can also be programmed using external configuration resistors. APPLICATIONS High Current Distributed Power Systems Servers, Network and Storage Equipment nn Intelligent Energy Efficient Power Regulation nn Industrial/Telecom/ATE Systems nn All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 5396245, 5859606, 6144194, 6937178, 7420359 and 7000125. nn TYPICAL APPLICATION VIN 7V TO 13.2V Efficiency and Power Loss vs Load Current + VCC VINSNS V SENSE0 LTC3882 TO/FROM EXTERNAL DEVICES TO/FROM OTHER OTHER PHASES PWM SDA COMP0 SCL COMP1 ALERT GND PWM0 RUN0 RUN1 WP GPIO0 GPIO1 92 VOUT 1V 80A SW TSNS0 ISENSE0+ ISENSE0– VSENSE1+ SHARE_CLK SYNC PWM1 IAVG_GND GND 89 88 9 87 7 86 85 84 5 VIN = 12V VOUT = 1V SYNC = 500kHz 82 ISENSE1+ VIN FDMF5820DC IAVG1 11 90 83 ISENSE1– IAVG0 13 91 POWERLOSS (W) TO/FROM MCU FDMF5820DC VIN EFFICIENCY (%) FB0 PWM 81 80 SW GND TSNS1 VSENSE0– 0 10 20 30 40 50 60 LOAD CURRENT (A) 70 3 80 1 3882 TA01b INDUCTORS: COOPER FP1007R1-R22 SOME DETAILS OMITTED FOR CLARITY 3882 TA01a Rev. C For more information www.analog.com 1 LTC3882 TABLE OF CONTENTS Features..............................................................1 Applications.........................................................1 Typical Application .................................................1 Description..........................................................1 Absolute Maximum Ratings.......................................4 Order Information...................................................4 Pin Configuration...................................................4 Electrical Characteristics..........................................5 Block Diagram..................................................... 14 Test Circuit......................................................... 15 Timing Diagram................................................... 15 Operation.......................................................... 15 Overview...................................................................... 15 Main Control Loop........................................................16 Power-Up and Initialization.......................................... 18 Soft-Start..................................................................... 19 Time-Based Output Sequencing................................... 19 Output Ramping Control.............................................. 19 Voltage-Based Output Sequencing............................... 19 Output Disable.............................................................. 19 Minimum Output Disable Times...................................20 Output Short Cycle.......................................................20 Light Load Current Operation.......................................20 Switching Frequency and Phase..................................20 PolyPhase Load Sharing..............................................21 Active Voltage Positioning............................................21 Input Supply Monitoring..............................................21 Output Voltage Sensing and Monitoring......................21 Output Current Sensing and Monitoring......................22 External and Internal Temperature Sense....................22 Resistor Configuration Pins.........................................22 Internal EEPROM with ECC and CRC............................23 Fault Detection.............................................................23 Input Supply Faults......................................................23 Hardwired PWM Response to VOUT Faults...................23 Power Good Indication.................................................24 Hardwired PWM Response to IOUT Faults....................24 Hardwired PWM Response to Temperature Faults.......24 Hardwired PWM Response to Timing Faults................24 External Faults..............................................................25 Fault Handling..............................................................25 Status Registers and ALERT Masking..........................25 Mapping Faults to GPIO Pins........................................27 Other GPIO Uses..........................................................27 Fault Logging................................................................27 Factory Default Operation............................................30 Serial Interface.............................................................31 Serial Bus Addressing..................................................31 Serial Bus Timeout.......................................................35 Serial Communication Errors.......................................35 PMBus Command Summary.................................... 36 PMBus Commands.......................................................36 Data Formats................................................................36 Applications Information........................................ 41 Efficiency Considerations.............................................41 PWM Frequency and Inductor Selection......................41 Power MOSFET Selection.............................................42 MOSFET Driver Selection.............................................43 Using PWM Protocols..................................................43 CIN Selection................................................................44 COUT Selection..............................................................45 Feedback Loop Compensation.....................................45 PCB Layout Considerations..........................................47 Output Current Sensing................................................48 Output Voltage Sensing................................................50 Soft-Start and Stop......................................................50 Time-Based Output Sequencing and Ramping.............51 Voltage-Based Output Sequencing...............................52 Using Output Voltage Servo.........................................53 Using AVP....................................................................53 PWM Frequency Synchronization................................55 PolyPhase Operation and Load Sharing.......................55 External Temperature Sense........................................58 Resistor Configuration Pins.........................................59 Internal Regulator Outputs...........................................60 IC Junction Temperature..............................................61 Derating EEPROM Retention at Temperature...............61 Configuring Open-Drain Pins.......................................61 PMBus Communication and Command Processing.....62 Status and Fault Log Management...............................63 LTpowerPlay – An Interactive Digital Power GUI..........64 Interfacing to the DC1613.............................................64 Design Example............................................................65 PMBus COMMAND DETAILS..................................... 67 Addressing and Write Protect...........................................67 PAGE............................................................................67 PAGE_PLUS_WRITE....................................................67 PAGE_PLUS_READ......................................................68 WRITE_PROTECT........................................................68 MFR_ADDRESS...........................................................69 MFR_RAIL_ADDRESS.................................................69 General Device Configuration...........................................69 PMBUS_REVISION.......................................................69 CAPABILITY.................................................................69 On, Off and Margin Control...............................................70 ON_OFF_CONFIG..........................................................70 MFR_CONFIG_ALL_LTC3882......................................70 OPERATION..................................................................71 MFR_RESET.................................................................71 PWM Configuration..........................................................72 FREQUENCY_SWITCH..................................................72 Rev. C 2 For more information www.analog.com LTC3882 TABLE OF CONTENTS MFR_PWM_CONFIG_LTC3882....................................73 MFR_CHAN_CONFIG_LTC3882................................... 74 MFR_PWM_MODE_LTC3882......................................75 Input Voltage and Limits...................................................76 VIN_ON........................................................................76 VIN_OFF.......................................................................76 VIN_OV_FAULT_LIMIT.................................................76 VIN_UV_WARN_LIMIT.................................................76 Output Voltage and Limits................................................77 VOUT_MODE................................................................77 VOUT_COMMAND........................................................77 MFR_VOUT_MAX.........................................................77 VOUT_MAX..................................................................78 MFR_VOUT_AVP..........................................................78 VOUT_MARGIN_HIGH..................................................78 VOUT_MARGIN_LOW..................................................78 VOUT_OV_FAULT_LIMIT..............................................78 VOUT_OV_WARN_LIMIT..............................................79 VOUT_UV_WARN_LIMIT..............................................79 VOUT_UV_FAULT_LIMIT..............................................79 Output Current and Limits................................................80 IOUT_CAL_GAIN..........................................................80 MFR_IOUT_CAL_GAIN_TC..........................................80 IOUT_OC_FAULT_LIMIT...............................................80 IOUT_OC_WARN_LIMIT...............................................80 Output Timing, Delays, and Ramping...............................81 MFR_RESTART_DELAY...............................................81 TON_DELAY.................................................................81 TON_RISE....................................................................81 TON_MAX_FAULT_LIMIT............................................82 VOUT_TRANSITION_RATE...........................................82 TOFF_DELAY................................................................82 TOFF_FALL...................................................................82 TOFF_MAX_WARN_LIMIT...........................................82 External Temperature and Limits......................................83 MFR_TEMP_1_GAIN.....................................................83 MFR_TEMP_1_OFFSET.................................................83 OT_FAULT_LIMIT.........................................................83 OT_WARN_LIMIT.........................................................83 Status Reporting...............................................................84 STATUS_BYTE.............................................................84 UT_FAULT_LIMIT.........................................................84 STATUS_WORD............................................................85 STATUS_VOUT.............................................................85 STATUS_IOUT..............................................................85 STATUS_INPUT............................................................86 STATUS_TEMPERATURE.............................................86 STATUS_CML...............................................................86 STATUS_MFR_SPECIFIC..............................................87 MFR_PADS_LTC3882..................................................87 MFR_COMMON............................................................88 MFR_INFO....................................................................88 CLEAR_FAULTS...........................................................88 Telemetry..........................................................................89 READ_VIN....................................................................90 MFR_VIN_PEAK...........................................................90 READ_VOUT.................................................................90 MFR_VOUT_PEAK........................................................90 READ_IOUT..................................................................90 MFR_IOUT_PEAK.........................................................90 READ_POUT.................................................................90 READ_TEMPERATURE_1.............................................91 MFR_TEMPERATURE_1_PEAK....................................91 READ_TEMPERATURE_2.............................................91 MFR_TEMPERATURE_2_PEAK...................................91 READ_DUTY_CYCLE....................................................91 READ_FREQUENCY......................................................91 MFR_CLEAR_PEAKS...................................................91 Fault Response and Communication.................................92 VIN_OV_FAULT_RESPONSE........................................92 VOUT_OV_FAULT_RESPONSE.....................................93 VOUT_UV_FAULT_RESPONSE.....................................93 IOUT_OC_FAULT_RESPONSE......................................94 OT_FAULT_RESPONSE.................................................95 UT_FAULT_RESPONSE................................................95 MFR_OT_FAULT_RESPONSE.......................................95 TON_MAX_FAULT_RESPONSE....................................96 MFR_RETRY_DELAY...................................................96 SMBALERT_MASK.......................................................97 MFR_GPIO_PROPAGATE_LTC3882.............................98 MFR_GPIO_RESPONSE...............................................98 MFR_FAULT_LOG........................................................99 Fault Log Operation......................................................99 MFR_FAULT_LOG_CLEAR...........................................99 EEPROM User Access.....................................................100 STORE_USER_ALL....................................................100 RESTORE_USER_ALL................................................100 MFR_COMPARE_USER_ALL.....................................100 MFR_FAULT_LOG_STORE.........................................101 MFR_EE_xxxx............................................................101 USER_DATA_0x.........................................................101 Unit Identification...........................................................101 MFR_ID......................................................................101 MFR_MODEL.............................................................101 MFR_SERIAL.............................................................101 MFR_SPECIAL_ID......................................................101 Typical Applications.............................................102 Package Description............................................104 Revision History.................................................105 Typical Application..............................................106 Related Parts.....................................................106 For more information www.analog.com Rev. C 3 LTC3882 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) IAVG1 ISENSE1+ ISENSE1– VSENSE1+ VSENSE0– VSENSE0+ ISENSE0– ISENSE0+ IAVG0 FB0 40 39 38 37 36 35 34 33 32 31 COMP0 1 30 FB1 TSNS0 2 29 COMP1 TSNS1 3 28 BG1/EN1 VINSNS 4 27 TG1/PWM1 41 GND IAVG_GND 5 BGO/EN0 6 26 VCC –) 25 VDD33 (VSENSE1 TGO/PWM0 7 24 SHARE_CLK SYNC 8 23 WP SCL 9 22 VDD25 SDA 10 21 PHAS_CFG FREQ_CFG VOUT1_CFG ASEL1 ASEL0 RUN1 RUN0 GPIO1 GPIO0 11 12 13 14 15 16 17 18 19 20 VOUT0_CFG *See Derating EEPROM Retention at Temperature in the Applications Information section for junction temperatures in excess of 125°C. TOP VIEW ALERT VCC Supply Voltage..................................... –0.3V to 15V VINSNS Voltage.......................................... –0.3V to 40V VSENSE0 –....................................................... –0.3V to 1V VSENSEn+, ISENSEn+, ISENSEn –......................... –0.3V to 6V VDD33, FBn, COMPn, TSNSn, IAVGn, IAVG_GND.......................................... –0.3V to 3.6V SYNC, GPIOn, WP, PWMn, ENn, SHARE_CLK............................................... –0.3V to 3.6V SCL, SDA, RUNn, ALERT............................ –0.3V to 5.5V VDD25, ASELn, VOUTn_CFG, FREQ_CFG, PHAS_CFG............................................... –0.3V to 2.75V Operating Junction Temperature Range (Notes 2, 3)........................................... –40°C to 125°C* Storage Temperature Range................. –65°C to 150°C* UJ PACKAGE 40-LEAD (6mm × 6mm) PLASTIC QFN TJMAX = 125°C, θJA = 33°C/W , θJC = 2.5°C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3882EUJ#PBF LTC3882EUJ#TRPBF LTC3882UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C LTC3882IUJ#PBF LTC3882IUJ#TRPBF LTC3882UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C LTC3882EUJ#WPBF LTC3882EUJ#WTRPBF LTC3882UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C LTC3882IUJ#WPBF LTC3882IUJ#WTRPBF LTC3882UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C AUTOMOTIVE PRODUCTS** Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. C 4 For more information www.analog.com LTC3882 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0– = VSENSE1– = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IC Supply VCC VCC Voltage Range VDD33 = Internal LDO l 4.5 13.8 V VDD33_EXT VDD33 Voltage Range VCC = VDD33 (Note 6) l 3 3.6 V VUVLO Undervoltage Lockout Threshold VDD33 Rising Hysteresis l IQ IC Operating Current tINIT Controller Initialization Time 42 Delay from RESTORE_USER_ALL, MFR_RESET or VDD33 > VUVLO Until TON_DELAY Can Begin 3 V mV 32 mA 35 ms VDD33 Linear Regulator VDD33 Internal VDD33 Voltage VCC ≥ 4.5V IDD33 VDD33 Current Limit VDD33 = 2.8V VDD33 = 0V l 3.2 3.3 3.4 85 40 V mA mA VDD25 Linear Regulator VDD25 Internal VDD25 Voltage IDD25 VDD25 Current Limit 2.25 2.5 2.75 95 V mA PWM Control Loops VINSNS VIN Sense Voltage Range RVINSNS VINSNS Input Resistance VOUT_R0 Range 0 Maximum VOUT Range 0 Set Point Accuracy (Note 7) Range 0 Resolution Range 0 LSB Step Size VOUT_R1 Range 1 Maximum VOUT Range 1 Set Point Accuracy (Note 7) Range 1 Resolution Range 1 LSB Step Size 3 0.6V ≤ VOUT ≤ 5V 0.6V ≤ VOUT ≤ 5V 0.6V ≤ VOUT ≤ 2.5V 0.6V ≤ VOUT ≤ 2.5V l –0.5 –0.5 VSENSE+ = 5.5V VSENSE– = 0V IVSENSE VSENSE Input Current VLINEREG VCC Line Regulation, No Output Servo 4.5V ≤ VCC ≤ 13.2V (See Test Circuit) AVP AVP Set Accuracy, ∆VOUT AVP = 10%, VOUT_COMMAND = 1.8V, ISENSE Differential Step 3mV (20%) to 12mV (80%) IOUT_OC_WARN_LIMIT at 15mV Resolution LSB Step Size l 38 kΩ 5.25 ±0.2 0.5 V % % Bits mV 0.5 V % % Bits mV 12 1.375 2.65 ±0.2 12 0.6875 235 –335 l V 278 µA µA –0.02 0.02 %/V –118 –96 mV 5 0.5 Bits % AV(OL) Error Amplifier Open-Loop Voltage Gain 87 dB SR Error Amplifier Slew Rate 9.5 V/µs f0dB Error Amplifier Bandwidth 30 MHz ICOMP Error Amplifier Output Current Sourcing Sinking –2.6 34 mA mA RVSFB Resistance Between VSENSE+ and FB Range 0 Range 1 VISENSE ISENSE Differential Input Range l l 52 37 67 49 –1 ±0.1 83 61 ±70 IISENSE ISENSE± Input Current 0V ≤ VPIN ≤ 5.5V IAVG_VOS IAVG Current Sense Offset Referred to ISENSE Inputs l –600 ±175 kΩ kΩ mV 1 µA 650 µV µV Rev. C For more information www.analog.com 5 LTC3882 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0– = VSENSE1– = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified. SYMBOL PARAMETER CONDITIONS VSIOS Slave Current Sharing Offset Referred to ISENSE Inputs fSYNC SYNC Frequency Accuracy 250kHz ≤ fSYNC ≤ 1.25MHz MIN l –800 l –10 TYP ±300 MAX UNITS 700 µV µV 10 % Input Voltage Supervisor NVON Input ON/OFF Resolution LSB Step Size VON_TOL Input ON/OFF Threshold Accuracy 8 143 15V ≤ VIN_ON ≤ 35V l –2 Bits mV 2 % Output Voltage Supervisors NUVOV Resolution VUVOV_R0 Range 0 Maximum Threshold Range 0 Accuracy Range 0 LSB Step Size VUVOV_R1 Range 1 Maximum Threshold Range 1 Accuracy Range 1 LSB Step Size 9 2V ≤ VOUT ≤ 5V (UV and OV) 1V ≤ VOUT ≤ 2.5V (UV and OV) l l –1 –1 5.5 11 2.75 5.5 Bits 1 V % mV 1 V % mV Output Current Supervisors NlLIM Resolution Step Size VILIM_TOL Output Current Limit Accuracy VIREV IREV Threshold Voltage 8 0.4 ISENSE+ – ISENSE– 15mV < ISENSE+ – ISENSE– ≤ 30mV 30mV < ISENSE+ – ISENSE– ≤ 50mV 50mV < ISENSE+ – ISENSE– ≤ 70mV l l l –1.7 –2.5 –5.2 Bits mV 1.7 2.5 5.2 mV mV mV ISENSE+ – ISENSE– 0 mV (Note 9) 10 Bits ADC Readback Telemetry (Note 8) NVIN VINSNS Readback Resolution VIN_TUE VINSNS Total Unadjusted Readback Error 4.5V ≤ VINSNS ≤ 38V 0.5 2 l NDC PWM Duty Cycle Resolution (Note 9) DCTUE PWM Duty Cycle Total Unadjusted Readback Error PWM Duty Cycle = 12.5% NVOUT VOUT Resolution LSB Step Size VOUT_TUE VOUT Total Unadjusted Readback Error 10 –2 Bits 2 16 244 0.6V ≤ VOUT ≤ 5.5V, Constant Load l NISENSE IOUT Readback Resolution LSB Step Size (at ISENSE±) ISENSE_FS IOUT Full Scale Conversion Range ISENSE_TUE IOUT Total Unadjusted Readback Error ISENSE_OS IOUT Zero-Code Offset Voltage NTEMP Temperature Resolution TEXT_TUE External Temperature Total Unadjusted Readback Error TSNS0, TSNS1 ≤ 1.85V (Note 10) MFR_PWM_MODE_LTC3882[6] = 0 MFR_PWM_MODE_LTC3882[6] = 1 l l TINT_TUE Internal Temperature Total Unadjusted Readback Error Internal Diode l tCONVERT Update Rate (Note 11) –0.5 (Note 9) 0mV ≤ |ISENSE+ – ISENSE–| < 16mV 16mV ≤ |ISENSE+ – ISENSE–| < 32mV 32mV ≤ |ISENSE+ – ISENSE–| < 63.9mV 63.9mV ≤ |ISENSE+ – ISENSE–| ≤ 70mV ±0.2 0.5 10 15.625 31.25 62.5 125 l –1 –32 % % Bits µV µV µV µV mV 1 % 32 µV 0.25 –3 –7 % Bits µV ±70 |ISENSE+ – ISENSE–| ≥ 6mV, 0V ≤ VOUT ≤ 5.5V % % °C 3 7 °C °C ±1 °C 90 ms Rev. C 6 For more information www.analog.com LTC3882 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VCC = 5V, VSENSE0+ = VSENSE1+ = 1.8V, VSENSE0– = VSENSE1– = IAVG_GND = GND = 0V, fSYNC = 500kHz (externally driven) unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Internal EEPROM (Notes 4, 6) Endurance Number of Write Operations 0°C ≤ TJ ≤ 85°C During All Write Operations l 10,000 Retention Stored Data Retention TJ ≤ 125°C l 0°C ≤ TJ ≤ 85°C During All Write Operations l Mass Write Time STORE_USER_ALL Execution Duration Cycles 10 Years 0.2 2 s Digital Inputs (SCL, SDA, RUNn, GPIOn, SYNC, SHARE_CLOCK, WP) VIH Input High Voltage SCL, SDA, RUN0, RUN1, GPIO0, GPIO1 SYNC, SHARE_CLK, WP l l VIL Input Low Voltage SCL, SDA, RUN0, RUN1, GPIO0, GPIO1 SYNC, SHARE_CLK, WP l l 1.35 1.8 V V 0.8 0.6 V V VHYST Input Hysteresis SCL, SDA 80 mV IPUWP Input Pull-Up Current WP = 0V 10 µA CIN Input Capacitance SCL, SDA, RUN0, RUN1, GPIO0, GPIO1, SYNC, SHARE_CLK tFILT Input Digital Filter Delay GPIO0, GPIO1 RUN0, RUN1 10 3 10 pF µs µs Digital Outputs (PWMn/TGn, ENn/BGn) VOL Output Low Voltage ISINK = 2mA l VOH Output High Voltage ISOURCE = 2mA l tRO Output Rise Time CLOAD = 30pF, 10% to 90% 5 ns tFO Output Fall Time CLOAD = 30pF, 90% to 10% 4 ns 300 2.7 mV V Open Drain and Three State Outputs (SCL, SDA, RUNn, GPIOn, SYNC, SHARE_CLOCK, ALERT, PWMn, ENn) VOL Output Low Voltage ISINK = 3mA; SDA, SCL, GPIO0, GPIO1, ALERT, SYNC, l RUN0, RUN1, SHARE_CLK 0.2 ITEST PWM Protocol Test Current EN0, EN1 = 3.3V, MFR_PWM_MODE_LTC3882[2:1] =0 10 ILKG Output Leakage Current 0V ≤ PWM0, PWM1 ≤ VDD33 0V ≤ EN0, EN1 ≤ VDD33 0V ≤ GPIO0, GPIO1 ≤ 3.6V 0V ≤ SYNC, SHARE_CLK ≤ 3.6V 0V ≤ RUN0, RUN1 ≤ 5.5V 0V ≤ SCL, SDA, ALERT ≤ 5.5V 0.4 V µA l –1 1 µA l –5 5 µA l –5 5 µA 400 kHz Serial Bus Timing fSMB Serial Bus Operating Frequency l 10 tBUF Bus Free Time Between Stop and Start l 1.3 µs tHD,STA Hold Time After (Repeated) Start Condition. After This Period, the First Clock Is Generated l 0.6 µs tSU,STA Repeated Start Condition Setup Time l 0.6 µs tSU,STO Stop Condition Setup Time l 0.6 µs tHD,DAT Data Hold Time: Receiving Data Transmitting Data l l 0 0.3 tSU,DAT Input Data Setup Time l 100 tTIMEOUT Clock Low Timeout l 25 35 ms tLOW Serial Clock Low Period l 1.3 10000 µs tHIGH Serial Clock High Period l 0.6 0.9 ns µs ns µs Rev. C For more information www.analog.com 7 LTC3882 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3882 is tested under pulsed load conditions such that TJ ≈ TA. The LTC3882E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3882I is guaranteed over the full –40°C to 125°C operating junction temperature range. Junction temperature TJ is calculated in °C from the ambient temperature TA and power dissipation PD according to the formula: TJ = TA + (PD • θJA) where θJA is the package thermal impedance. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Refer to the Applications Information section. Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. Note 4: EEPROM endurance, retention and mass write times are guaranteed by design, characterization and correlation with statistical process controls. Minimum retention applies only for devices cycled less than the minimum endurance specification. EEPROM read commands (e.g. RESTORE_USER_ALL) are valid over the entire specified operating junction temperature range. Note 5: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to GND unless otherwise specified. Note 6: Minimum EEPROM endurance, retention and mass write time specifications apply when writing data with 3.15V ≤ VDD33 ≤ 3.45V. EEPROM read commands are valid over the entire specified VDD33 operating range. Note 7: Specified VOUT accuracy with AVP = 0% requires servo mode to be set with MFR_PWM_MODE_LTC3882 command bit 6. Performance is guaranteed by testing the LTC3882 in a feedback loop that servos VOUT to a specified value. Note 8: ADC tested with PWMs disabled. Comparable capability demonstrated by in-circuit evaluations. Total Unadjusted Error includes all gain and linearity errors, as well as offsets. Note 9: Internal 32-bit calculations using 16-bit ADC results are limited to 10-bit resolution by PMBus Linear 11-bit data format. Note 10: Limits guaranteed by TSNS voltage and current measurements during test, including ADC readback. Note 11: Data conversion is done in round robin fashion. All inputs signals are continuously scanned in sequence resulting in a typical conversion latency of 90ms. Rev. C 8 For more information www.analog.com LTC3882 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Load Current (1-Phase Using D12S1R880A Power Block) 95 Efficiency vs Load Current (3-Phase Using D12S1R845A Power Block) 94 VIN = 12V 0 10 EFFICIENCY (%) EFFICIENCY (%) EFFICIENCY (%) 88 86 84 80 0 10 30 50 20 40 LOAD CURRENT (A) 1500 1500 –400 –300–200–100 0 100 200 300 400 CH1 ISENSE OFFSET TO IDEAL (µV) 0 3882 G25 2000 1500 500 –400 –300–200–100 0 100 200 300 400 CH1 ISENSE OFFSET TO IDEAL (µV) 0 3882 G26 IOUT 20A/DIV VOUT 20mV/DIV VOUT 20mV/DIV 12 IL1, IL2 10A/DIV 10 8 –300 –200–100 0 100 200 300 400 500 CH1 ISENSE OFFSET TO IDEAL (µV) Load Dump Transient Current Sharing (Using FDMF6707B DrMOS) IOUT 20A/DIV 14 3882 G03 2500 Load Step Transient Current Sharing (Using FDMF6707B DrMOS) CHANNEL 1 CHANNEL 2 CHANNEL 3 0 3000 3882 G25 3-Phase DC Output Current Sharing (Using D12S1R845A Power Block 30 1000 500 500 25 11783 UNITS FROM 3 LOTS TJ = 121°C CHO MASTER 3500 1000 1000 15 20 VIN (V) 4000 NUMBER OF ICs NUMBER OF ICs NUMBER OF ICs 2000 10 5 4500 2000 0.5 POWER FET: BSC050N04LS G SYNC FET: BSC010N04LS Typical Distribution of Slave IOUT Offset (Not Including DCR Mismatch) 8593 UNITS FROM 3 LOTS 3000 T = 38°C J CHO MASTER 2500 2500 PHASE CURRENT (A) 1.0 86 80 70 60 3500 9595 UNITS 3500 FROM 3 LOTS TA = –40°C 3000 TJ = –22°C CHO MASTER 16 88 Typical Distribution of Slave IOUT Offset (Not Including DCR Mismatch) 4000 18 1.5 90 3882 G02 Typical Distribution of Slave IOUT Offset (Not Including DCR Mismatch) 20 2.0 92 82 3882 G01 0 94 84 82 40 20 30 LOAD CURRENT (A) 2.5 96 IL1, IL2 10A/DIV 6 4 2 0 0 10 20 30 40 50 60 TOTAL RAIL CURRENT (A) 70 80 VOUT = 1V VIN = 12V SYNC = 500kHz L = 320nH 5µs/DIV 3882 G05 VOUT = 1V VIN = 12V SYNC = 500kHz L = 320nH 5µs/DIV 3882 G06 3882 G04 Rev. C For more information www.analog.com 9 POWERLOSS (W) 3.3V 2.5V 1.8V 1.5V 1.2V 1.0V 80 3.0 VO = 1.8V 98 90 85 75 100 VIN = 12V VOUT = 1.5V 92 90 Efficiency and Power Loss vs Input Voltage (1-Phase Using LTC4449) LTC3882 TYPICAL PERFORMANCE CHARACTERISTICS 3+1 Channel Crosstalk (Using D12S1R845A Power Blocks) Load Step Transient Response Using AVP VOUT0 (1-PHASE) 20mV/DIV Line Step Transient Response (1-phase Using LTC4449) IO 10A/DIV VOUT1 (3-PHASE) 20mV/DIV 25% LOAD STEP IOUT1 10A/DIV 100µs/DIV 1.8V VOUT 50mV/DIV IL1, IL2 10A/DIV IL1, IL2 10A/DIV 3882 G10 1.7995 Soft-Off Ramp RUN 2V/DIV VOUT 1V/DIV VIN = 12V Regulated Output vs Temperature 3882 G11 1ms/DIV VOUT_COMMAND INL VOUT_COMMAND DNL 1.0 0.8 1.0 0.6 0.4 1.7985 0.5 DNL (LSB) INL (LSB) VOUT (V) 1.7990 0 1.7980 0.2 0 –0.2 –0.4 –0.5 1.7975 1.7970 –40 –20 3882 G12 5ms/DIV TOFF_DELAY = 10ms TOFF_FALL = 5ms 1.5 VOUT_COMMAND = 1.8V DIGITAL SERVO OFF 3882 G09 200µs/DIV Start-Up Into a Prebiased Load VOUT 0.5V/DIV 0V 1.8000 3882 G08 200µs/DIV VOUT 0.5V/DIV 1ms/DIV VOUT 10mV/DIV 3882 G07 Soft-Start Ramp VIN = 12V 7V VIN 2V/DIV –0.6 0 20 40 60 80 TEMPERATURE (°C) 100 120 3882 G13 –1.0 0.3 1.1 1.9 2.7 3.5 VOUT (V) 4.3 5.1 5.5 3882 G14 –0.8 0.3 1.1 1.9 2.7 3.5 VOUT (V) 4.3 5.1 5.5 3882 G15 Rev. C 10 For more information www.analog.com LTC3882 TYPICAL PERFORMANCE CHARACTERISTICS Output Overvoltage Threshold Error vs Temperature Output Overcurrent Threshold Error vs Temperature 0.05 0 –0.05 –0.10 VOUT_OV_FAULT_LIMIT = 2V VOUT RANGE = 1 –0.15 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 500.2 1.0 500.1 0.8 0.6 0.4 0.2 0 VIN(SNS) ADC TUE 499.7 –0.4 –40 –20 499.5 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 VOUT ADC TUE –3 –4 –5 –6 –7 5 10 15 20 25 VINSNS (V) 30 35 40 20 40 60 80 TEMPERATURE (°C) 6 0.20 0.10 0 –0.10 –0.20 4 2 0 –2 –4 –6 –0.40 0.5 3882 G19 1 1.5 2 2.5 3 3.5 VOUT (V) 4 4.5 5 –8 5.5 1.0 10 5 15 OUTPUT CURRENT (A) 0 3882 G20 SHARE_CLK Frequency vs Temperature Temperature ADC TUE 100 120 IOUT ADC TUE –0.30 0 0 8 MEASUREMENT ERROR (mA) –2 FREQUENCY_SWITCH = 500kHz 3882 G18 0.30 MEASUREMENT ERROR (mV) MEASUREMENT ERROR (mV) 499.8 499.6 0.40 –8 20 3882 G21 IC Operating Current vs Temperature 31.0 110 0.8 VCC = 14V 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 ICC OPERATING CURRENT (mA) 30.8 SHARE_CLK FREQUENCY (kHz) MEASUREMENT ERROR (°C) 499.9 3882 G17 –1 –9 500.0 –0.2 3882 G16 0 PWM Frequency vs Temperature 1.2 PWM FREQUENCY (kHz) OUTPUT OC THRESHOLD ERROR (%) VOUT OV THRESHOLD ERROR (%) 0.10 105 100 95 30.6 30.4 30.2 30.0 29.8 29.6 –0.8 –1.0 –45 –25 –5 15 35 55 75 95 115 ACTUAL TEMPERATURE (°C) 90 –50 –30 –10 10 30 50 70 TEMPERATURE (°C) 90 3882 G22 110 3882 G23 29.4 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 3882 G24 Rev. C For more information www.analog.com 11 LTC3882 PIN FUNCTIONS COMP0/COMP1 (Pin 1/Pin 29): Error Amplifier Outputs. PWM duty cycle increases with this control voltage. These are true low impedance outputs and cannot be directly connected together when active. For PolyPhase operation, wiring FB to VDD33 will three-state the error amplifier output of that channel, making it a slave. PolyPhase control is then implemented in part by connecting all slave COMP pins together to one master error amplifier output. TSNS0/TSNS1 (Pin 2/Pin 3): External Temperature Sense Inputs. The LTC3882 supports two methods of calculation of external temperature based on forward-biased P/N junctions between these pins and GND. VINSNS (Pin 4): VIN Supply Sense. Connect to the VIN power supply to provide line feedforward compensation. A change in VIN immediately modulates the input to the PWM comparator and inversely changes the pulse width to provide excellent transient line regulation and fixed modulator voltage gain. An external lowpass filter can be added to this pin to prevent noisy signals from affecting the loop gain. IAVG_GND (Pin 5): IAVG Ground Reference. The same IAVG_GND should be shared between all channels of a PolyPhase rail and connected to system ground at a single point. IAVG_GND may be wired directly to GND on ICs that do not share phases with other chips. BG0(EN0)/BG1(EN1) (Pin 6/Pin 28): PWM Multi-Function Control Pins. These pins can be digitally programmed to provide direct bottom FET control (BGn function) or PWM enable control (ENn function), depending on external gate driver requirements. These pins can also function as inputs for three-state PWM protocol selection and should be left open if not used. TG0(PWM0)/TG1(PWM1) (Pin 7/Pin 27): PWM MultiFunction Control Outputs. These pins can be digitally programmed to provide direct top FET control (TGn function) or single-wire PWM switching control (PWMn function), depending on external gate driver requirements. SYNC (Pin 8): External Clock Synchronization Input and Open-Drain Output. If desired, an external clock can be applied to this pin to synchronize the internal PWM channels. If the LTC3882 is configured as a clock master, this pin will also pull to ground at the selected PWM switching frequency with a 125ns pulse width. A pull-up resistor to 3.3V is required in the application if SYNC is driven by any LTC3882. Minimize the capacitance on this line to ensure its time constant is fast enough for the application. SCL (Pin 9): Serial Bus Clock Input. A pull-up resistor to 3.3V is required in the application. SDA (Pin 10): Serial Bus Data Input and Output. A pull-up resistor to 3.3V is required in the application. ALERT (Pin 11): Open-Drain Status Output. This pin may be connected to the system SMBALERT wire-AND interrupt signal and should be left open if not used. If used, a pull-up resistor to 3.3V is required in the application. GPIO0/GPIO1 (Pin 12/Pin 13): Programmable General Purpose Digital Inputs and Open-Drain Outputs. Uses include status indication, external device control, and channel-to-channel fault communication and propagation. These pins should be left open if not used. If used, a pull-up resistor to 3.3V is required in the application. RUN0/RUN1 (Pin 14/Pin 15): Run Control Inputs and Open-Drain Outputs. A voltage above 2V is required on these pins to enable the respective PWM channel. The LTC3882 will drive these pins low under certain reset/restart conditions regardless of any PMBus command settings. A pull-up resistor to 3.3V is required in the application. ASEL0/ASEL1 (Pin 16/Pin 17): Serial Bus Address Select Inputs. Connect optional 1% resistor dividers between VDD25 and GND to these pins to select the serial bus interface address. Refer to the Applications Information section for more detail. VOUT0_CFG/VOUT1_CFG (Pin 18/Pin 19): Output Voltage Configuration Inputs. Connect optional 1% resistor dividers between VDD25 and GND to these pins to select the output voltage for each channel. Refer to the Applications Information section for more detail. Rev. C 12 For more information www.analog.com LTC3882 PIN FUNCTIONS FREQ_CFG (Pin 20): Frequency Configuration Input. Connect an optional 1% resistor divider between VDD25 and GND to this pin to configure PWM switching frequency. Refer to the Applications Information section for more detail. PHAS_CFG (Pin 21): Phase Configuration Input. Connect an optional 1% resistor divider between VDD25 and GND to this pin to configure the phase of each PWM channel relative to SYNC. Refer to the Applications Information section for more detail. VDD25 (Pin 22): Internal 2.5V Regulator Output. Bypass this pin to GND with a low ESR 1µF capacitor. Do not load this pin with external current beyond that required for local LTC3882 configuration pins, if any. WP (Pin 23): Write Protect Input. If WP is above 2V, PMBus writes are restricted and any software WRITE_PROTECT settings are overridden. Refer to PMBus Command Details for more information. This pin has an internal 10µA pull-up to VDD33. SHARE_CLK (Pin 24): Share Clock Input and Open-Drain Output. Share Clock, nominally 100kHz, is used to sequence multiple rails in a power system utilizing more than one LTC PSM controller. A pull-up resistor to 3.3V is required in the application. Minimize the capacitance on this line to ensure the time constant is fast enough for the application. VDD33 (Pin 25): Internal 3.3V Regulator Output. Bypass this pin to GND with a low ESR 2.2µF capacitor. The LTC3882 may also be powered from an external 3.3V rail attached to this pin, if also shorted to VCC. Do not overload this pin with external system current. Local pull-up resistors for the LTC3882 itself may be powered from VDD33. Refer to the Applications Information section for more detail. VCC (Pin 26): 3.3V Regulator Input. Bypass this pin to GND with a capacitor (0.1µF to 1µF ceramic) in close proximity to the IC. VSENSE0– (Pin 35): Channel 0 Negative Output Voltage Sense Input. This pin must still be properly connected on slave channels for accurate output current telemetry. VSENSE0+/VSENSE1+ (Pin 36/Pin 34): Positive Output Voltage Sense Inputs. These pins must still be properly connected on slave channels for accurate output current telemetry. ISENSE0–/ISENSE1– (Pin 37/Pin 33): Current Sense Amplifier Inputs. The (–) inputs to the amplifiers are normally connected to the low side of a DCR sensing network or output current sense resistor for each phase. ISENSE0+/ISENSE1+ (Pin 38/Pin 32): Current Sense Amplifier Inputs. The (+) inputs are normally connected to the high side of an output current sense resistor or the R-C midpoint of a parallel DCR sense circuit. IAVG0/IAVG1 (Pin 39/Pin 31): Average Current Control Pins. A capacitor connected between these pins and IAVG_GND stores a voltage proportional to the average output current of the master channel. PolyPhase control is then implemented in part by connecting all slave IAVG pins together to the master IAVG output. This pin should be left open on channels that control single-phase outputs. FB0/FB1 (Pin 40/Pin 30): Error Amplifier Inverting Inputs. These pins provide an internally scaled version of the output voltage for use in loop compensation. Refer to the Applications Information section for additional details on compensating the output voltage control loop with external components. GND (Exposed Pad Pin 41): Ground and VSENSE1–. All small-signal and compensation components should connect to this pad, which also serves as the negative voltage sense input for channel 1. The exposed pad must be soldered to a suitable PCB copper ground plane for proper electrical operation and to obtain the specified package thermal resistance. Rev. C For more information www.analog.com 13 LTC3882 BLOCK DIAGRAM ROM RAM EEPROM VINSNS R_CONFIG IAVG0 MCU AND CUSTOM LOGIC SHARE_CLK PMBus ± ISENSE0 2.5V REGULATOR WP SYNC 12-BIT DAC PWM0 PWM0/EN0 PLL VOLTAGE REFERENCE VREF IAVG_GND 3.3V REGULATOR VCC PWM1/EN1 VDD33 BIAS AND HOUSEKEEPING PWM1 VSENSE1± IAVG1 INTERNAL DATA BUS VSENSE0± 16-BIT ADC ISENSE0± VSENSE1± 12-BIT DAC ISENSE1± VINSNS PWM0 TSNS0 PWM1 VSENSE0± VINSNS ANALOG MUX INTERNAL TEMPERATURE ISENSE1± TSNS1 3882 BD Rev. C 14 For more information www.analog.com LTC3882 TEST CIRCUIT (Channel 0 Example) LTC3882 1.024V VR 12-BIT D/A DIGITAL + EA – VSENSE0– VSENSE0+ 35 FB0 36 COMP0 40 1 + LTC1055 TARGET = VOUT_COMMAND – 1V TIMING DIAGRAM SDA tf tLOW tr tSU(DAT) tHD(SDA) tf tSP tr tBUF SCL tHD(STA) tHD(DAT) tHIGH tSU(STA) tSU(STO) 3882 TD START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION OPERATION Overview Major features include: The LTC3882 is a dual channel/dual phase, constant frequency analog voltage mode controller for DC/DC step-down applications. It features a PMBus compliant digital interface for monitoring and control of important power system parameters. The chip operates from an IC power supply between 3V and 13.2V and is intended for conversion from VIN between 3V and 38V to output voltages between 0.5V and 5.25V. It is designed to be used in a switching architecture with external FET drivers, including higher level integrations such as non-isolated power blocks. • Digitally Programmable Output Voltage • Digitally Programmable Output Current Limit • Digitally Programmable Input Voltage Supervisor • Digitally Programmable Output Voltage Supervisors • Digitally Programmable Switching Frequency • Digitally Programmable On and Off Delay Times • Digitally Programmable Soft-Start/Stop Rev. C For more information www.analog.com 15 LTC3882 OPERATION • Operating Condition Telemetry Main Control Loop • Phase Locked Loop for Synchronous PolyPhase Operation (2, 3, 4, 6, or 8 phases) The LTC3882 utilizes constant frequency voltage mode control with leading-edge modulation. This provides improved response to a load step increase, especially at larger VIN/ VOUT ratios found in the low voltage, high current solutions demanded by modern digital subsystems. The LTC3882 leading-edge modulation architecture does not have a minimum on-time requirement. Minimum duty cycle will be determined by performance limits of the external power stage. The IC is also capable of active voltage positioning (AVP) to afford the smallest output capacitors possible for a given output voltage accuracy over the anticipated full load range. The LTC3882 error amplifiers have high bandwidth, low offset and low output impedance, allowing the control loop compensation network to be optimized for very high crossover frequencies and excellent transient response. The controller also achieves outstanding line transient response by using input feedforward compensation to instantaneously adjust PWM duty cycle and significantly reduce output under/overshoot during supply voltage changes. This also has the added advantage of making the DC loop gain independent of input voltage. • Fully Differential Load Sense • Non-Volatile Configuration Memory with ECC • Optional External Configuration Resistors for Key Operating Parameters • Optional Time-Base Interconnect for Synchronization Between Multiple Controllers • Fault Event Data Logging • WP Pin to Protect Internal Configuration • Capable of Standalone Operation with Default Factory Configuration • PMBus Revision 1.2 Compliant Interface up to 400kHz The PMBus interface provides access to important power management data during system operation including: • Average Input Voltage • Average Output Voltages • Average Output Currents • Average PWM Duty Cycles • Internal LTC3882 Temperature • External Sensed Temperatures • Warning and Fault Status, Including Input and Output Undervoltage and Overvoltage The LTC3882 supports four serial bus addressing schemes to access the individual PWM channels separately or jointly. Fault reporting and system response behavior are fully configurable. Two status outputs are provided (GPIO0, GPIO1) that can be controlled independently. A separate ALERT pin also provides for a maskable SMBALERT#. Fault responses for each channel may be individually programmed, depending on the fault type. PMBus status commands allow fault reporting over the serial bus to identify a specific fault event. The main PWM control loop used for each channel is illustrated in Figure 1. During normal operation the top MOSFET (power switch) driving choke L1 is commanded off when the clock for that channel resets the RS latch. The power switch is commanded back on when the main PWM comparator VC, sets the RS latch. The error amplifier EA output (COMP) controls the PWM duty cycle to match the FB voltage to the EA positive terminal voltage in steady state. A patented circuit adjusts this output for VINSNS line feedforward. The positive terminal of the EA is connected to the output of a 12-bit DAC with values ranging from 0V to 1.024V. The DAC value is determined by the resistor configuration pins detailed in application Table 8, by values retrieved from internal EEPROM, or by a combination of PMBus commands to synthesize the desired output voltage. Refer to the following PMBus Command Details section of this document for more information. The LTC3882 supports two output ranges. EA can regulate the output voltage to 5.5x the DAC output (Range 0) or 2.75x the DAC output (Range 1). Rev. C 16 For more information www.analog.com LTC3882 OPERATION LTC3882 MODE OSCILLATOR CLOCK TG0 R Q PWM LOGIC S BG0 VIN 7 GATE DRIVER 6 0V VOC0 8-BIT DAC IOUT_OC_FAULT_LIMIT ILIM RAMP VC VREV IREV FEED FORWARD + + + CA – S – SLAVE ENABLE ISENSE0+ ISENSE0– IAVG0 IAVG_GND SLAVE DETECT RS 38 L1 CS VOUT 37 39 COUT 5 MASTER ENABLE VOV0 9-BIT DAC VOUT_OV_FAULT_LIMIT 9-BIT DAC VOUT_UV_FAULT_LIMIT OV UV VUV0 VSENSE0+ 36 9R (RANGE 0) – EA + 4 VINSNS VSP0 FB0 12-BIT DAC VOUT_COMMAND 2R VSENSE0– COMP0 LOOP COMPENSATION NETWORK 40 35 1 3882 F01 Figure 1. LTC3882 PWM Control Loop Diagram Rev. C For more information www.analog.com 17 LTC3882 OPERATION VC discriminates its positive input against an internally generated PWM voltage ramp. The positive input is a composite control based on COMP voltage with line feedforward compensation, and current sharing if the channel controls a slave phase. When the ramp falls below this voltage the comparator trips and sets the PWM latch. If load current increases, VSENSE+ and FB will droop slightly with respect to the 12-bit DAC output. This causes the COMP voltage to increase until the average inductor current matches the new load current and the desired output voltage is restored. Programmable comparators ILIM and IREV monitor peak instantaneous forward and reverse inductor current for pulse-by-pulse protection. The top power MOSFET is immediately commanded off if the programmed positive limit is reached, and the bottom MOSFET is immediately commanded off if the negative limit is reached. Repeated peak overcurrent events cause an overcurrent fault to be set. When the top MOSFET is commanded off, the bottom MOSFET is normally commanded on. In continuous conduction mode (CCM) the bottom MOSFET stays on until comparator VC turns the top MOSFET back on. Otherwise in discontinuous conduction mode (DCM, also known as diode emulation) the bottom MOSFET is commanded off if the IREV comparator detects that the inductor current has decayed to approximately 0A. In any case the next PWM cycle starts when the clock for that channel again clears the RS latch. Power-Up and Initialization The LTC3882 is designed to provide stand-alone supply sequencing with controlled turn-on and turn-off functions. It operates from a single IC input supply of 3V to 13.2V while two on-chip linear regulators generate internal 2.5V and 3.3V. If VCC is below 4.5V, the VCC and VDD33 pins must be shorted together and limited to a maximum operating voltage of 3.6V. Controller configuration is reset by the internal UVLO threshold, where VDD33 must be at or above 3V and the internal 2.5V supply must be within about 20% of its regulated value. At that point the internal microcontroller begins initialization. A PMBus RESTORE_USER_ALL or MFR_RESET command forces this same initialization. The LTC3882 features an internal RAM built-in self-test (BIST) that runs during initialization. Should RAM BIST fail, the following steps are taken. • Device responds only at device address 0x7C and global addresses 0x5A and 0x5B • A persistent Memory Fault Detected is indicated by STATUS_CML • Internal EEPROM is not accessed • RUNn and SHARE_CLK are driven low continuously Normal operation can be restored if the RAM BIST subsequently passes, for instance as the result of another MFR_RESET command issued to address 0x7C. During initialization all PWM outputs are disabled. The RUNn pins and SHARE_CLK are held low and GPIOn pins are high impedance. External configuration resistors are identified and the contents of the onboard EEPROM are read into the controller command memory space. The LTC3882 can determine key operating parameters from external configuration resistors according to application Table 8 through Table 11. See the following Resistor Configuration Pins section for more detail. The resistor configuration pins only determine some of the preset values of the controller. The remaining values, retrieved from internal EEPROM, are programmed at the factory or with PMBus commands. If the configuration resistor pins are all open, the LTC3882 will use only EEPROM contents to determine all operating parameters. If Ignore Resistor Configuration Pins is set (bit 6 of MFR_CONFIG_ALL_LTC3882), the LTC3882 will use only its EEPROM contents to determine all operating parameters except device address. Unless both ASEL pins are completely open, the LTC3882 will always determine some portion of its device address from the resistors on these pins. See Serial Bus Addressing later in this section. The internal microcontroller typically requires 35ms to complete initialization from VDD33 ≥ 3V. At that point, an internal comparator monitors VINSNS, which must exceed the VIN_ON threshold before output power sequencing can begin (SHARE_CLK released, ready for TON_DELAY). Accurate readback telemetry can then require an additional 90ms for initial round-robin A/D conversions. Rev. C 18 For more information www.analog.com LTC3882 OPERATION Soft-Start The RUN pins are released for external control after the part initializes and VINSNS is greater than the VIN_ON threshold. If multiple LTC3882 ICs are used in an application, shared RUN pins are held low until all units initialize and VINSNS exceeds the VIN_ON threshold for all devices. A common SHARE_CLK signal can also ensure all connected devices use the same time reference for initial start-up even if RUN pins cannot be shared due to other design requirements. SHARE_CLK is not released by each IC until the conditions for power sequencing have been fully satisfied. After a channel RUN pin rises above 2V and any specified turn on delay (TON_DELAY) has expired, the LTC3882 performs an initial monotonic soft-start ramp on that channel. This is carried out with a digitally controlled ramp of the regulated output voltage from 0V to the commanded voltage set point over the programmed TON_RISE period, allowing inrush current control. During the soft-start ramp, the LTC3882 does not initiate PWM operation until the commanded output exceeds the actual rail voltage. This allows the regulator to start up into a pre-biased load even when using gate drivers or power blocks that do not support discontinuous operation. The soft-start feature is disabled by setting the value of TON_RISE to any time less than 0.25ms. Time-Based Output Sequencing The LTC3882 supports time-based on and off output sequencing using a shared time reference (SHARE_CLK). Following a valid qualified command to turn on, each output is enabled after waiting its programmed TON_DELAY. This can be used to sequence outputs in a prescribed order that can be preprogrammed as needed without hardware modification. Channel off-sequencing is accomplished in a similar way with the TOFF_DELAY command. Output Ramping Control The LTC3882 supports synchronized output on and off ramping control using a shared time reference (SHARE_ CLK). Power rail on and off relationships similar to those of conventional analog tracking functions can be achieved by using programmed delays and TON_RISE and TOFF_FALL times. However, with LTC3882 digital control, on and off ramping methods need not be the same, and ramping configurations can be reprogrammed as needed without hardware modification. Programmable fault responses and fault sharing can ensure that any desired time-based output sequencing and ramping control is properly accomplished each time the system powers up or down. Refer to the Applications Information section for various LTC3882 hardware and PMBus command configurations needed to fully support synchronization for time-based sequencing and output ramping when using multiple ICs. Voltage-Based Output Sequencing It is also possible to sequence outputs on using cascaded voltage events. To do this, the GPIO pin monitoring one PWM channel can be used to control the RUN pin of a downstream channel. The controlling GPIO pin can be configured to hold low if VOUT is below the VOUT_UV_FAULT_LIMIT or if POWER_GOOD conditions are not being met. This keeps the downstream channel off until acceptable output conditions exist on the controlling channel. The LTC3882 does not readily support voltage-based off-sequencing. Refer to the Applications Information section for more details on voltage-based sequencing. Output Disable Both PWM channels are disabled any time VINSNS is below the VIN_OFF threshold. The power stages are immediately shut off to stop the transfer of energy to the load(s) as quickly as possible. A PWM channel may also be disabled in response to certain internal fault conditions, an external fault propagated through a GPIO pin, or loss of SHARE_CLK. In these cases the power stage is immediately shut off to stop the transfer of energy to the load as quickly as possible. Refer to the following Fault Detection and Handling section for additional details related to fault recovery. Each PWM channel can be disabled with a PMBus OPERATION command at any time if enabled by ON_OFF_CONFIG. This will force a controlled turn-off response with defined delay (TOFF_DELAY) and ramp down rate (TOFF_FALL). The controller will maintain the programmed mode of Rev. C For more information www.analog.com 19 LTC3882 OPERATION operation for TOFF_FALL. In DCM, the controller will not draw current from the load and fall time will be set by output capacitance and load current. Finally, each PWM channel can be commanded off by pulling the associated RUN pin low. Pulling the RUN pin low can force the channel to perform a controlled turn off or immediately disable the power stage, depending on the programming of the ON_OFF_CONFIG command. Minimum Output Disable Times When a PMBus OPERATION command is used to turn off an LTC3882 channel, a minimum output disable time of 120ms is imposed regardless of how quickly the channel is commanded back on. If bit 4 of MFR_CHAN_CONFIG is clear, a PMBus command to turn the channel off also pulses the RUN pin low. Once the RUN pin is pulled low internally or externally, a minimum output disable time (RUN forced low) of TOFF_DELAY + TOFF_FALL + 136ms is enforced. If MFR_RESTART_DELAY is greater than this mandatory minimum, the larger value of MFR_RESTART_DELAY is used. In either case the LTC3882 holds its own RUN pin low during the entire disable period. These minimum off times allow a consistent channel restart with coherent monitor ADC values and make the LTC3882 highly compatible with other LTC PSM digital power system management products. Output Short Cycle An output short cycle condition is created when a master channel is commanded back on while waiting for TOFF_DELAY or TOFF_FALL to expire. Any time this occurs, the LTC3882 asserts the Short Cycle bit in STATUS_MFR_SPECIFIC. Device response at that point is governed by bits in MFR_CHAN_CONFIG_LTC3882 and SMBALERT_MASK. Refer to the detailed descriptions of those commands for additional details. Generally, the LTC3882 should be controlled so that short cycle conditions are not created during normal operation. Light Load Current Operation The LTC3882 has two modes of PWM operation: discontinuous conduction mode (DCM) and forced continuous conduction mode (CCM). Mode selection is made with the MFR_PWM_MODE command. In DCM, the inductor current is not allowed to reverse. The reverse current comparator IREV disables the external bottom MOSFET (synchronous rectifier) when the inductor current reaches approximately 0A, preventing it from going substantially negative. The LTC3882 can be programmed to disable the bottom NFET by putting the PWM output into high impedance, deasserting the EN output, or driving the BG output low. PWM control protocol selection depends on the requirements of the external gate driver or power block, which must have short delays to a high impedance output, relative to the PWM cycle, to support DCM. Efficiency at light loads in CCM is lower than in DCM. Continuous conduction mode exhibits less interference with audio circuitry but may result in reverse inductor current, for instance at light loads or under large transient conditions. Switching Frequency and Phase There is a high degree of flexibility for setting the PWM operating frequency of the LTC3882. The switching frequency of the PWM can be established with an internal oscillator or an external time base. The internal phase-locked loop (PLL) synchronizes PWM control to this timing reference with proper phase relation, whether the clock is provided internally or externally. The device can also be configured to provide the master clock to other ICs through PMBus command, EEPROM setting, or external configuration resistors as outlined in application Table 10. For PMBus or EEPROM configuration, the LTC3882 is designated as a clock master by clearing bit 4 of MFR_CONFIG_ALL_LTC3882. As clock master, the LTC3882 will drive its open-drain SYNC pin at the selected rate with a pulse width of 125ns. An external pull-up resistor between SYNC and VDD33 is required in this case. Only one device connected to SYNC should be designated to drive the pin. If more than one LTC3882 sharing SYNC is programmed as clock master, just one of the devices is automatically elected to provide the clock. The others disable their SYNC outputs and indicate this with bit 10 of MFR_PADS_LTC3882. The LTC3882 will automatically accept an external SYNC input, disabling is own SYNC drive if necessary, as long as the external clock frequency is greater than 1/2 of the programmed internal oscillator. Whether configured to drive SYNC or not, the LTC3882 can continue PWM operation Rev. C 20 For more information www.analog.com LTC3882 OPERATION at the selected frequency (FREQUENCY_SWITCH) using its own internal oscillator, if an external clock signal is subsequently lost. The MFR_PWM_CONFIG_LTC3882 command can be used to configure the phase of each channel. Desired phase can also be set from EEPROM or external configuration resistors as outlined in Table 10. Phase designates the relationship between the falling edge of SYNC and the internal clock edge that resets the PWM latch. That reset turns off the top power switch, producing a TG/PWM falling edge. Additional small propagation delays to the PWM control pins will apply. The phase relationships and frequency are independent of each other, providing numerous application options. Multiple LTC3882 ICs can be synchronized to realize a PolyPhase array. In this case the phases should be separated by 360/n degrees, where n is the number of phases driving the output voltage rail. PolyPhase Load Sharing Multiple LTC3882 ICs can be combined to provide a balanced load-share solution by configuring the necessary pins. The SHARE_CLK and SYNC pins of all load-sharing channels should be bussed together. Connecting the SYNC pins synchronizes the PWM controllers with each other. Bussing the SHARE_CLK pins together allows the phases to start synchronously. Refer to the discussion in the previous Power-Up and Initialization section. The last device to see all start-up conditions satisfied controls the initiation of power sequencing for all phases. Due to the low output impedance of the LTC3882 error amplifiers, PolyPhase applications should use the error amplifier of only one phase as the master. The FB pins of each slave channel must be wired to VDD33, and the COMP pins of each slave phase must be connected to the master error amplifier COMP output. This disables the slave error amplifiers and provides a single point of voltage control and loop stabilization for the PolyPhase output rail. For PolyPhase load sharing the LTC3882 also incorporates an auxiliary current sharing loop. Referring back to Figure 1, the instantaneous current of each slave phase is sensed by current amplifier CA and compared to the IAVG pin. The IAVG and IAVG_GND pins of each phase are wired together, and a small capacitor (50pF to 200pF) between IAVG and IAVG_GND stores a voltage corresponding to the average master phase output current. The difference in this average and the instantaneous phase current is integrated. The output of integrator S of each slave phase is then proportionally summed with the master error amplifier COMP output to adjust the duty cycle and balance the current contribution of that phase. Additional hardware configuration and digital programming requirements apply in PolyPhase systems. Refer to the Applications Information section for complete details on building PolyPhase rails with the LTC3882. Active Voltage Positioning Load slope is programmable in the LTC3882 via the MFR_VOUT_AVP PMBus command. The inductor current measured at the ISENSE pins is converted to a voltage which is then subtracted from the voltage reference at the positive input of the error amplifier. The final load slope is defined by the inductor current sense element and the bits set in the MFR_VOUT_AVP PMBus command. Setting MFR_VOUT_AVP to a value greater than 0.0% automatically disables output servo mode for that channel. Input Supply Monitoring The input supply voltage is sensed by the LTC3882 at the VINSNS pin. Undervoltage, overvoltage, valid on and off levels can be programmed for VIN. Refer to the following PMBus Command Details section for more information on programming the input supply thresholds. In addition, the telemetry ADC monitors the VINSNS voltage relative to GND. Conversion results are returned by the READ_VIN PMBus command. Output Voltage Sensing and Monitoring Both PWM channels allow remote, differential sensing of the load voltage with VSENSE pins. The channel 1 output sense pin VSENSE1– is internally shorted to GND (the exposed pad). The telemetry ADC is fully differential and makes its measurements of the output voltages of channels 0 and 1 at VSENSE0± and VSENSE1±, respectively. Conversion results are returned by the READ_VOUT PMBus command. Rev. C For more information www.analog.com 21 LTC3882 OPERATION Output Current Sensing and Monitoring Resistor Configuration Pins Both channels allow differential sensing of the inductor current using either the inductor DCR or a resistor in series with the inductor across the ISENSE pins. When the ISENSE pins for a channel are multiplexed to the differential inputs of the LTC3882 monitor ADC, they have an input range of approximately ±128mV and a noise floor of 7μVRMS. Peak-peak noise is approximately 46.5μV. The internal ADC anti-aliasing filter and conversion rate produce an average reading of the ISENSE differential voltage. The resulting value is returned by the READ_IOUT PMBus command. Refer to the Applications Information section for details on sensing output current using inductor DCR or discrete resistors. Six input pins can be used to configure key operating parameters with selected 1% resistors arranged between VDD25 and GND as a divider to the pin(s). The pins are ASEL0, ASEL1, VOUT0_CFG, VOUT1_CFG, FREQ_CFG, and PHAS_CFG. If any of these pins are left open the value stored in the corresponding EEPROM command is used. The resistor configuration pins are only measured during power-up and execution of RESTORE_USER_ALL or MFR_RESET commands. If bit 6 of the MFR_CONFIG_ALL_LTC3882 command is set in EEPROM, all resistor inputs except ASELn are ignored. Per the PMBus specification, all pinprogrammed parameters can be overridden at any time by commands from the digital interface. External and Internal Temperature Sense The ASELn pin settings are described in application Table 11. These pins can be used to select the entire LTC3882 device address. ASEL0 always programs the bottom four bits of the device address for the LTC3882 unless left open. ASEL1 can be used to program the three most-significant bits. Either portion of the address can also be retrieved from the MFR_ADDRESS value in EEPROM. If both pins are left open, the full 7-bit MFR_ADDRESS value stored in EEPROM is used to determine the device address. The LTC3882 always responds to 7-bit global addresses 0x5A and 0x5B. MFR_ADDRESS should not be set to either of these values. External temperature can best be measured using a remote, diode-connected PNP transistor such as the MMBT3906. The emitter should be connected to a TSNS pin while the base and collector terminals of the PNP transistor must be shorted together and returned directly to the LTC3882 GND pin. Two different currents are applied to the diode (nominally 2μA and 32μA) and the temperature is calculated from a ΔVBE measurement made with the internal 16-bit monitor ADC. The LTC3882 also supports direct VBE based external temperature measurements. In this case the diode or diode network is trimmed to a specific voltage at a specific current and temperature. In general this method does not yield as accurate a result as the ΔVBE measurement. Refer to MFR_PWM_MODE_LTC3882 in the PMBus Command Details section for additional information on programming the LTC3882 for these two external temperature sense configurations. The calculated temperature is returned by the PMBus READ_TEMPERATURE_1 command. Refer to the Applications Information section for details on proper layout of external temperature sense elements and PMBus commands that can be used to improve the accuracy of calculated temperatures. The READ_TEMPERATURE_2 command returns the internal junction temperature of the LTC3882 using an on-chip diode with a ΔVBE measurement and calculation. 22 The VOUTn_CFG pin settings are described in application Table 8. These pins select the output voltages for the related channel. The following parameters are also set as a percentage of the programmed VOUT if resistor configuration pins are used to determined output voltage: • VOUT_OV_FAULT_LIMIT: +10% • VOUT_OV_WARN_LIMIT: +7.5% • VOUT_MAX: +7.5% • VOUT_MARGIN_HIGH: +5% • VOUT_MARGIN_LOW: –5% • VOUT_UV_WARN_LIMIT: –6.5% • VOUT_UV_FAULT_LIMIT: –7% For more information www.analog.com Rev. C LTC3882 OPERATION The FREQ_CFG pin settings are described in application Table 9. This pin selects the switching frequency of the internal oscillator and enables the SYNC output if not left open, shorted to GND or ignored by EEPROM setting. Fault Detection The PHAS_CFG pin settings are described in Table 10. This pin selects the phase relationships between the two channels and the selected clock source. • Input Under/Overvoltage A variety of fault and warning detection, reporting and handling mechanisms are provided by the LTC3882. Fault or warning detection capabilities include: • Output Under/Overvoltage • Output Overcurrent (Peak and Average) Internal EEPROM with ECC and CRC The LTC3882 contains internal EEPROM with error correction code (ECC) to store user configuration settings and fault log information. EEPROM endurance and retention for user space and fault log pages are specified in the Absolute Maximum Ratings and Electrical Characteristics table. The integrity of the entire onboard EEPROM is checked with a CRC calculation each time its data is to be read, such as after a power-on reset or execution of a RESTORE_USER_ ALL command. If a CRC error occurs, the CML bit is set in the STATUS_BYTE and STATUS_WORD commands, the EEPROM CRC Error bit in the STATUS_MFR_SPECIFIC command is set, and the ALERT and RUN pins pulled low (PWM channels off). At that point the device will only respond at special address 0x7C, which is activated only after an invalid CRC has been detected. The chip will also respond at the global addresses 0x5A and 0x5B, but use of these addresses when attempting to recover from a CRC issue is not recommended. All power supply rails associated with either PWM channel of a device reporting an invalid CRC should remain disabled until the issue is resolved. LTC recommends that the EEPROM not be written when die temperature is greater than 85°C. If internal die temperature exceeds 130°C, all EEPROM operations except RESTORE_USER_ALL and MFR_RESET are disabled. Full EEPROM operation is not re-enabled until die temperature falls below 125°C. Refer to the Applications Information section for equations to predict retention degradation due to elevated operating temperatures. See the Applications Information section or contact the factory for details on efficient in-system EEPROM programming, including bulk EEPROM programming, which the LTC3882 also supports. • Internal and External Overtemperature and External Undertemperature • CML Fault (Communication, Memory, or Logic) • External Fault Detection via Bidirectional GPIO Pins Reporting is covered in following sections on status commands (registers) and ALERT pin function. Fault handling mechanisms include hardwired, low-level PWM safety responses that always occur, and higher-level programmable event management. Both types are covered in the following sections. Input Supply Faults Input undervoltage and overvoltage limits are determined from multiplexed monitor ADC conversions. Therefore the input UV/OV response is naturally deglitched by the 90ms typical conversion cycle of the ADC. There is no hardwired low-level PWM response for any input supply fault. Hardwired PWM Response to VOUT Faults VOUT undervoltage (UV) and overvoltage (OV) faults are detected by supervisor comparators. The OV and UV fault limits can be set in three ways: • As a Percentage of VOUT if Using the Resistor Configuration Pins • From Stored EEPROM Values • By PMBus Command The output overvoltage comparator guards against transient overshoots as well as long term overvoltages at the output. When an output OV fault is detected the top MOSFET for that channel is commanded off and the bottom MOSFET is commanded on until the overvoltage condition is cleared or for most PWM control protocols reverse overcurrent is detected. See IOUT faults below. Rev. C For more information www.analog.com 23 LTC3882 OPERATION UV faults and warnings are masked if the channel has been commanded off or until all of the following criteria are achieved. • TON_DELAY Has Expired • TON_RISE Ramp Has Completed • TON_MAX_FAULT_LIMIT Has Been Reached • IOUT_OC_FAULT_LIMIT Has Not Been Reached • TOFF_FALL Is Not in Progress Output UV warnings are determined from multiplexed monitor ADC conversions. The LTC3882 has no hardwired PWM response for output UV faults or warnings. Power Good Indication An LTC3882 master phase indicates Power Good in STATUS_WORD based on programmed UV and OV fault limits. Power Good is indicated as long as the phase is enabled to run and VOUT is between the UV and OV fault limits. Slave phases indicate Power Good in STATUS_ WORD once enabled, unless a master error amplifier fault is detected, indicating the bussed COMP voltage appears to be too high. Hardwired PWM Response to IOUT Faults The LTC3882 measures average IOUT from the voltage across the ISENSE pins, taking into account the sense resistor or DCR value and its associated temperature coefficient. Both are provided by PMBus command or EEPROM values. An output overcurrent (OC) fault condition is detected by a supervisor comparator for each PWM output when the sensed instantaneous current for that channel reaches its maximum allowed value. Refer to the IOUT_OC_ FAULT_LIMIT PMBus command for details. When an OC fault is detected the controller immediately disables the top FET, and the bottom FET is normally commanded on for the remainder of that PWM cycle. If programmed to operate in CCM, the LTC3882 also uses the negative of IOUT_OC_FAULT_LIMIT to detect a reverse overcurrent (ROC) fault. When an ROC fault occurs the controller immediately disables both top and bottom FETs, unless the EN pin for that channel is tied high with three-state PWM output protocol selected. OC and ROC faults are both handled according to the IOUT_OC_FAULT_RESPONSE for that channel. Either hardware response can result in current-limited operation using pulse truncation or skipping. Because the LTC3882 uses leading edge modulation, this will cause a shift in average phase toward 0° on the faulted channel and an increase in input ripple current Output OC warnings are determined from multiplexed monitor ADC conversions. The LTC3882 has no hardwired PWM response if an output OC warning occurs. Hardwired PWM Response to Temperature Faults An internal temperature sensor measured by the monitor ADC protects against EEPROM and other IC damage. When die temperature rises above 130°C, the LTC3882 will NACK any EEPROM-related command except RESTORE_ USER_ALL and MFR_RESET and issue a CML fault for Invalid/Unsupported Command. Normal EEPROM access is re-enabled when die temperature drops below 125°C. Above 160°C, the part shuts down all PWM outputs until die temperature is below 150°C. Internal temperature fault limits cannot be adjusted. Writing to the EEPROM above a die temperature of 85°C is strongly discouraged. Refer to the Absolute Maximum Ratings for other important temperature limitations on internal EEPROM use. External temperature sensors may also be monitored by the onboard ADC. There is no hardwired PWM response for sensed external temperature faults or warnings. Hardwired PWM Response to Timing Faults There is no hardwired PWM response to any timing faults. TON_MAX_FAULT_LIMIT is the time allowed for VOUT to rise and settle at start-up. The TON_MAX_FAULT_LIMIT timer, which has a resolution of 10µs, is started after TON_DELAY has been reached and a soft-start sequence is started. If the VOUT_UV_FAULT_LIMIT is not reached or an OC remains within the specified time, fault response is determined by the value of TON_MAX_FAULT_RESPONSE. An internal watchdog detects if SHARE_CLK remains low for more than 64µs. The part then actively holds SHARE_CLK low for 120ms, ensuring all devices connected to this shared control observe a minimum RETRY_DELAY Rev. C 24 For more information www.analog.com LTC3882 OPERATION event. The LTC3882 sets the SHARE_CLK_LOW bit in MFR_COMMON to indicate this fault condition. External Faults There are no hardware-level responses to any external faults propagated into the IC through the GPIOn pins. Fault Handling Status Registers and ALERT Masking Figure 2 summarizes the internal LTC3882 status registers accessible by PMBus command. These contain indication of various faults, warnings and other important operating conditions. As shown, the STATUS_BYTE and STATUS_WORD commands also summarize contents of other status registers. Refer to PMBus Command Details for specific information. Higher-level input and output fault event handling (response) can be programmed as described in the following PMBus Command Details section. For most faults, the LTC3882 can manage response in one of three ways: ignore, autonomous recovery (hiccup), or latch off. The device takes no additional action beyond previously discussed hardware-level responses when programmed to ignore a fault. NONE OF THE ABOVE in STATUS_BYTE indicates that one or more of the bits in the most-significant nibble of STATUS_WORD are also set. For autonomous recovery a new soft-start is attempted if the fault condition is not present after the MFR_RETRY_ DELAY interval has elapsed. MFR_RETRY_DELAY can be set from 120ms to 83 seconds in 1ms increments. If the fault persists, the controller will continue to retry with an interval specified by the MFR_RETRY_DELAY command. This avoids damage to external regulator components caused by repetitive, rapid power cycling. • A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_ RESET Command Is Issued No retry is attempted for a latch off fault response. In the latch off state the gate drivers for the external MOSFETs are immediately disabled to stop the transfer of energy to the load as quickly as possible. The output remains disabled until the channel is commanded off and then on, or IC supply power is cycled. Commanding a PWM channel off and on may require software and/or hardware intervention depending on its programmed configuration. The RUN pin must be released by any controlling external application circuits for that channel to restart from the latch off state. As the RUN pin for a given channel rises, associated internal fault indications are cleared automatically. The LTC3882 can also be programmed to clear faults for both outputs based solely on the RUN voltage of just one channel. See the MFR_CONFIG_ALL_LTC3882 command. The CLEAR_FAULTS PMBus command can also be used to clear all fault bits at any time, independent of PWM channel state. Handling of some internally generated faults can be digitally deglitched. See Table 12. External faults propagated into the chip using GPIOn pins are not deglitched. Refer to the following section on GPIO functions. In general, any asserted bit in a STATUS_x register also pulls the ALERT pin low. Once set, ALERT will remain low until one of the following occurs. • The Related Status Bit Is Written to a One • The Faulted Channel Is Properly Commanded Off and Back On • The LTC3882 Successfully Transmits Its Address During a PMBus Alert Response Address (ARA) • IC Supply Power Is Cycled With some exceptions, the SMBALERT_MASK command can be used to prevent the LTC3882 from asserting ALERT for bits in these registers on a bit-by-bit basis. These mask settings are promoted to STATUS_WORD and STATUS_BYTE in the same fashion as the status bits themselves. For example, if ALERT is masked for all bits in Channel 0 STATUS_VOUT, then ALERT is effectively masked for the VOUT bit in STATUS_WORD for PAGE 0. The BUSY bit in STATUS_BYTE also asserts ALERT low and cannot be masked. This bit can be set as a result of interaction between internal operation and PMBus communication. This fault occurs when a command is received that cannot be safely executed with one or both channels enabled. As discussed in Application Information, BUSY faults can be avoided by polling MFR_COMMON before executing some commands. Status information contained in MFR_COMMON and MFR_PADS_LTC3882 can be used to clarify the contents of STATUS_BYTE or STATUS_WORD as shown, For more information www.analog.com Rev. C 25 LTC3882 OPERATION STATUS_WORD STATUS_VOUT* 7 6 5 4 3 2 1 0 VOUT_OV Fault VOUT_OV Warning VOUT_UV Warning VOUT_UV Fault VOUT_MAX Warning TON_MAX Fault TOFF_MAX Warning (reads 0) 15 14 13 12 11 10 9 8 VOUT IOUT INPUT MFR_SPECIFIC POWER_GOOD# (reads 0) (reads 0) (reads 0) 7 6 5 4 3 2 1 0 BUSY OFF VOUT_OV IOUT_OC (reads 0) TEMPERATURE CML NONE OF THE ABOVE STATUS_BYTE (PAGED) STATUS_IOUT 7 6 5 4 3 2 1 0 IOUT_OC Fault (reads 0) IOUT_OC Warning (reads 0) (reads 0) (reads 0) (reads 0) (reads 0) MFR_COMMON 7 6 5 4 3 2 1 0 Chip Not Driving ALERT Low Chip Not Busy Internal Calculations Not Pending Output Not In Transition EEPROM Initialized (reads 0) SHARE_CLK_LOW WP Pin High 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved EEPROM ECC Status Reserved Reserved Reserved Reserved STATUS_TEMPERATURE OT Fault OT Warning (reads 0) UT Fault (reads 0) (reads 0) (reads 0) (reads 0) STATUS_CML 7 6 5 4 3 2 1 0 Invalid/Unsupported Command Invalid/Unsupported Data Packet Error Check Failed Memory Fault Detected Processor Fault Detected (reads 0) Other Communication Fault Other Memory or Logic Fault DESCRIPTION General Fault or Warning Event General Non-Maskable Event Dynamic Status Derived from Other Bits 7 6 5 4 3 2 1 0 Internal Temperature Fault Internal Temperature Warning EEPROM CRC Error Internal PLL Unlocked Fault Log Present (reads 0) VOUT Short Cycled GPIO Low (PAGED) MFR_PADS_LTC3882 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MFR_INFO (PAGED) VIN_OV Fault (reads 0) VIN_UV Warning (reads 0) Unit Off for Insuffcient VIN (reads 0) (reads 0) (reads 0) STATUS_MFR_SPECIFIC (PAGED) (PAGED) 7 6 5 4 3 2 1 0 STATUS_INPUT 7 6 5 4 3 2 1 0 Channel 1 is Slave Channel 0 is Slave (reads 0) (reads 0) Invalid ADC Result(s) SYNC Output Disabled Externally Channel 1 is POWER_GOOD Channel 0 is POWER_GOOD LTC3882 Forcing RUN1 Low LTC3882 Forcing RUN0 Low RUN1 Pin State RUN0 Pin State LTC3882 Forcing GPIO1 Low LTC3882 Forcing GPIO0 Low GPIO1 Pin State GPIO0 Pin State MASKABLE GENERATES ALERT BIT CLEARABLE Yes No No No Yes Yes No Not Directly Yes Yes No No *IF THE CHANNEL IS CONFIGURED AS A SLAVE AS INDICATED BY MFR_PADS_LTC3882[15:14], VOUT_OV FAULT INDICATES A DETECTED MASTER ERROR AMPLIFIER FAULT (COMP VOLTAGE TOO HIGH). NO OTHER BITS IN STATUS_VOUT ARE ACTIVE ON SLAVE CHANNELS 3882 F02 Figure 2. LTC3882 Status Register Summary Rev. C 26 For more information www.analog.com LTC3882 OPERATION but the contents of these registers do not affect the state of the ALERT pin and may not directly influence bits in STATUS_BYTE or STATUS_WORD. Mapping Faults to GPIO Pins The LTC3882 can map various fault indicators to their respective GPIO pin using the MFR_GPIO_PROPAGATE_ LTC3882 command. Channel-to-channel fault dependencies and communication can be created by connecting GPIO pins together. In the event of an internal fault, one or more of the channels is configured to pull the bussed GPIO pins low. All channels are then configured to shut down when the bussed GPIO pins are pulled low (MFR_GPIO_RESPONSE set to 0xc0). If latch off is the programmed response on the faulted channel, the GPIO pin remains low until one of the following occurs: • A CLEAR_FAULTS, RESTORE_USER_ALL or MFR_ RESET Command Is Issued • The Related Status Bit Is Written to a One • The Faulted Channel Is Properly Commanded Off and Back On • IC Supply Power Is Cycled For autonomous group retry, the faulted channel is configured to release the GPIO pin(s) after a retry interval, assuming the original fault has cleared. All the channels in the group then begin a soft-start sequence. Other GPIO Uses A GPIO pin can also find usage as a driver for an external crowbar device, overtemperature alert, overvoltage alert, or as an interrupt to cause a microcontroller to poll the status commands. The GPIO pins may be configured as inputs to detect faults external to the controller that require an immediate response. External faults propagated into the chip using GPIOn pins are not deglitched. The GPIO pins can also serve as power good indicator outputs. On master phases, this designates the controller’s output is within the desired regulation limits. As described in the previous Voltage-Based Output Sequencing section, the GPIO pins also make it possible to control start-up through concatenated events. Refer to the MFR_GPIO_PROPAGATE command for additional details. Fault Logging The LTC3882 features a fault log, providing telemetry recording capability. During normal operation log data is continuously updated in internal RAM. When a fault occurs that disables either PWM controller, recording to internal memory is halted, the fault log information is made available from RAM via the MFR_FAULT_LOG command, and the contents of the RAM log are copied into EEPROM. Refer to the Fault Log Operation section for more detail. EEPROM fault logging is allowed above a die temperature of 85°C, but 10 years of retention is not guaranteed. When die temperature exceeds 130°C EEPROM fault logging is delayed until the temperature drops below 125°C. Faults generating a log should be fully cleared before the log is erased to prevent generation of spurious fault logs. Faults propagated into the IC through GPIOn pins do not trigger a fault logging event. When the LTC3882 powers up it checks the EEPROM for a valid fault log. If one is found the Valid Fault Log bit in the STATUS_MFR_SPECIFIC PMBus command is set. Additional fault logging will be disabled until the LTC3882 receives a CLEAR_FAULTS command. If the Memory Fault Detected bit is also set in STATUS_CML, then the stored fault log is partial. Data in one or more event records may be incomplete or incorrect and MFR_FAULT_LOG_CLEAR should also be commanded after all faults are cleared in order to fully enable additional logging functions. The MFR_FAULT_LOG command uses a block read protocol with a fixed length of 147 bytes. The LTC3882 returns a block byte count of zero if a fault log is not present. Contents of a fault log are shown in Table 1 through Table 4. Refer to Table 6 for an explanation of data formats. Each event record represents one complete conversion cycle through all multiplexed monitor ADC inputs and related status. The six most recent event records are maintained in internal memory in reverse chronological order unless the part is reset. Then the four most recent events are maintained in EEPROM. When a fault log is created the present ADC input cycle is completed and the ADC input being converted at the time of the fault is noted in the log header record. For more information www.analog.com Rev. C 27 LTC3882 OPERATION Table 1. LTC3882 Fault Log Contents STARTING BYTE ENDING BYTE COMMENTS Header Information 0 26 See Table 2. Fault Event Record 27 46 Fault may have occurred anywhere during this event record. See byte 4 of Table 2 and all of Table 3 and Table 4. Event Record N-1 47 66 Last complete cyclical data read before the fault was detected. Event Record N-2 67 86 Older data records… Event Record N-3 87 106 Event Record N-4 107 126 Event Record N-5 127 146 RECORD TYPE Oldest recorded data. Table 2. Fault Log Header Information RECORD BITS FORMAT Fault Log Preface [7:0] ASC [7:0] [15:8] MFR_REAL_TIME MFR_VOUT_PEAK (PAGE 0) Reg Returns LTxx beginning at byte 0 if a partial or complete fault log exists. Word xx is a factory identifier that may vary part to part. 2 3 Reg 4 Refer to Table 3. [7:0] Reg 5 48 bit share-clock counter value when fault occurred (200µs resolution). [15:8] 6 [23:16] 7 [31:24] 8 [39:32] 9 [47:40] 10 [15:8] L16 [15:8] MFR_IOUT_PEAK (PAGE 0) [15:8] MFR_IOUT_PEAK (PAGE 1) [15:8] MFR_VIN_PEAK [15:8] L16 L11 [15:8] L11 Peak READ_IOUT on Channel 0 since last power-on or CLEAR_PEAKS command. 17 Peak READ_IOUT on Channel 1 since last power-on or CLEAR_PEAKS command. 19 Peak READ_VIN since last power-on or CLEAR_PEAKS command. 21 External temperature sensor 0 during last event. 22 L11 [7:0] [7:0] 15 20 [7:0] READ_TEMPERATURE2 Peak READ_VOUT on Channel 1 since last power-on or CLEAR_PEAKS command. 18 L11 [7:0] [15:8] 13 16 L11 [7:0] READ_TEMPERATURE1 (PAGE 1) Peak READ_VOUT on Channel 0 since last power-on or CLEAR_PEAKS command. 14 [7:0] [15:8] 11 12 [7:0] READ_TEMPERATURE1 (PAGE 0) DETAILS [7:0] [7:0] MFR_VOUT_PEAK (PAGE 1) 0 1 [7:0] Fault Source BLOCK BYTE COUNT 23 External temperature sensor 1 during last event. 24 L11 25 Internal temperature sensor during last event. 26 Rev. C 28 For more information www.analog.com LTC3882 OPERATION Table 3. Fault Source Values FAULT SOURCE VALUE CAUSE OF FAULT LOG 0x00 TON_MAX 0x01 VOUT_OV 0x02 VOUT_UV 0x03 IOUT_OC 0x05 Over temperature 0x06 Under temperature CHANNEL 0 0x07 VIN_OV 0x0A Internal temperature 0x10 TON_MAX 0x11 VOUT_OV 0x12 VOUT_UV 0x13 IOUT_OC 0x15 Over temperature 0x16 Under temperature 0x17 VIN_OV 0x1A Internal temperature 0xFF MFR_FAULT_LOG_STORE 1 Table 4. Fault Log Event Record DATA BITS FORMAT RECORD BYTE INDEX READ_VOUT (PAGE 0) [15:8] L16 0 [7:0] READ_VOUT (PAGE 1) [15:8] READ_IOUT (PAGE 0) [15:8] READ_IOUT (PAGE 1) [15:8] 1 L16 2 L11 4 L11 6 [7:0] 3 [7:0] 5 [7:0] READ_VIN [15:8] 7 L11 [7:0] (Not used) [15:8] STATUS_VOUT (PAGE 0) [7:0] 8 9 L11 10 Reg 12 [7:0] 11 STATUS_VOUT (PAGE 1) [7:0] Reg 13 STATUS_WORD (PAGE 0) [15:8] Reg 14 [7:0] STATUS_WORD (PAGE 1) [15:8] 15 Reg [7:0] 16 17 STATUS_MFR_SPECIFIC (PAGE 0) [7:0] Reg 18 STATUS_MFR_SPECIFIC (PAGE 1) [7:0] Reg 19 Rev. C For more information www.analog.com 29 LTC3882 OPERATION Factory Default Operation The LTC3882 ships from the factory with a default configuration stored in its non-volatile memory, unless custom programming has been requested. These command values are loaded into volatile RAM when the chip is initialized. Prior to receiving any PMBus commands, a stock LTC3882 will operate in the factory default mode. If a STORE_USER_ ALL command is executed, the contents of the non-volatile memory are replaced with active command values from internal RAM, and that will permanently overwrite the factory defaults. Table 5 summarizes the default factory operation settings of the LTC3882 if all resistor configuration pins are left open. These defaults allow parameters listed in bold text in the table to be overridden with configuration resistor programming. Warning limits are given in Table 5 because exceeding them will cause the ALERT pin to be asserted even if the PMBus interface is not being utilized. Table 5. Factory Default Operation Summary PARAMETER* DEFAULT SETTING UNITS PMBus Address All writes enabled to Channel 0 at address 0x4F (no PEC). – Operation OPERATION enabled with RUN pin control and soft-off. – Input Voltage OFF Threshold 6.0 V Input Voltage UV Warning Limit 6.3 V Input Voltage ON Threshold 6.5 V Input Voltage OV Fault Limit 15.5 V Input Voltage OV Fault Response Latch off. Soft-Start Time 8 (with no delay). ms – Maximum Start-Up Time (TMAX) 10 ms TMAX Fault Response Retry every 350ms. – Output Voltage UV Fault/Warning Limits 0.900/0.925 V Output Voltage UV Fault Response Retry every 350ms. – Output Voltage 1.000 V Active Voltage Positioning Disabled. – Output Voltage OV Warning/Fault Limits 1.075/1.100 V Output Voltage OV Fault Response Retry every 350ms. – Shut Down 8ms soft-off. – Output Current Sense Element 0.63mΩ with 3930ppm/°C TC. – Output Current OC Warning/Fault Limits 20/29.75 A Output Current OC Fault Response Ignore – PWM Switching Mode Continuous inductor current only. – PWM Control Protocol Three-State PWM. – PWM Switching Frequency 500 Channel 0/1 Phase 0/180 kHz Degrees Internal Overtemperature Warning/Fault Limits 130/160 °C Internal Overtemperature Responses Warning: EEPROM disabled; Fault: PWM disabled. – External Undertemperature Fault Limit –40 °C External Undertemperature Fault Response Retry every 350ms. – External Overtemperature Warning/Fault Limits 85/100 °C External Overtemperature Fault Response Retry every 350ms. – GPIO Asserts low for the following faults: VOUT UV or OV, VIN OV, external or internal OT, external UT, TON_MAX, or output short cycle. – ALERT Masking ALERTs are masked for loss of PLL lock and external GPIO inputs. – *bold entries can be changed with external configuration resistors Rev. C 30 For more information www.analog.com LTC3882 OPERATION Serial Interface • Read Byte The LTC3882 has a PMBus compliant serial interface that can operate at any frequency between 10kHz and 400kHz. The LTC3882 is a bus slave device that communicates bidirectionally with a host (master) using standard PMBus protocols. The Timing Diagram found earlier in this document, along with related Electrical Characteristics table entries, define the timing relationships of the SDA and SCL bus signals. SDA and SCL must be high when the bus is not in use. External pull-up resistors or current sources are required on these lines. • Read Word PMBus, an incremental extension of the SMBus standard, offers more robust operation than a 2-wire I2C interface. In addition to adding a protocol layer to improve interoperability and facilitate reuse, PMBus supports bus timeout recovery for system reliability, optional packet error checking to ensure data integrity, and peripheral hardware alerts for system fault management. In general, a programmable device capable of functioning as an I2C bus master can be configured for PMBus management with little or no change to hardware. However, not all I2C controllers support repeat start (restart) required for PMBus reads. For a description of the minor extensions and exceptions PMBus makes to the SMBus standard, refer to PMBus Specification Part I Revision 1.2 Paragraph 5 on Transport. For a description of the differences between SMBus and I2C, refer to System Management Bus (SMBus) Specification Version 2.0 Appendix B on Differences Between SMBus and I2C. The user is encouraged to reference Part I of the latest PMBus Power System Management Protocol Specification to understand how to interface the LTC3882 to a PMBus system. This specification can be found at http://www. pmbus.org/specs.html. The LTC3882 uses the following standard serial interface protocols defined in the SMBus and PMBus specifications: • Quick Command • Send Byte • Write Byte • Write Word • Block Read • Block Write – Block Read Process Call • Alert Response Address The LTC3882 does not require PEC for Quick Command under any circumstances. The LTC3882 also supports group command protocol (GCP) as required by PMBus specification Part I, section 5.2.3. GCP is used to send commands to more than one PMBus device in one continuous transmission. It should not be used with commands that require the receiving device to respond with data, such as a STATUS_BYTE command. Refer to Part I of the PMBus specification for additional details on using GCP. All LTC3882 message transmission types allow for packet error checking. The later section on Serial Communication Errors provides more detail on packet error checking. Figure 4 to Figure 20 illustrate these protocols. Figure 3 provides a key to the protocol diagrams. Not all protocol elements will be present in every data packet. For instance, not all packets are required to include the packet error code. A number shown above a field in these diagrams indicates the number of bits in that field. All data transfers are initiated by the present bus master regardless of how many times data direction flow may change during the subsequent transmission. The LTC3882 never functions as a bus master. This device includes handshaking features to ensure robust system communication. Please refer to the PMBus Communication and Command Processing section in Applications Information for more details. Serial Bus Addressing The LTC3882 supports four types of serial bus addressing: • Global Bus Addressing • Power Rail Addressing • Individual Device Addressing • Page+ Channel Addressing Rev. C For more information www.analog.com 31 LTC3882 OPERATION Global addressing provides a means for the bus master to communicate with all LTC3882 devices on the bus simultaneously. The LTC3882 global addresses of 0x5A and 0x5B cannot be changed or disabled. Commands sent to address 0x5A are applied to both channels, as if the PAGE command were set to 0xFF. Global address 0x5B is paged, allowing channel-specific control of all LTC3882 devices on the bus. Other LTC device types may respond at one or both of these global addresses. Reading from global addresses is strongly discouraged. that might be required for reliable system control. Reading from rail addresses is also strongly discouraged. Device addressing is the most common means used by a bus master to communicate with an LTC3882. The value of the device address is set by the combination of ASEL pin programming and the MFR_ADDRESS command. Refer to the previous section on Resistor Configuration Pins for details. Individual channel addressing allows the bus master to communicate directly with a specific LTC3882 PWM channel without first using a PAGE command. Refer to the PAGE_PLUS commands for additional details. Rail addressing provides a means for the bus master to simultaneously communicate with all channels connected together to produce a single output voltage (PolyPhase). While similar to global addressing, the rail address can be dynamically assigned with the paged MFR_RAIL_ADDRESS command, allowing for any logical grouping of channels Use of any of the four types of addressing requires careful planning to avoid address-related bus conflicts. Communication to LTC3882 devices at global and rail addresses should be limited to command write operations. S START CONDITION Sr REPEATED START CONDITION Rd READ (BIT VALUE OF 1) Wr WRITE (BIT VALUE OF 0) A NA ACKNOWLEDGE (BIT SHOULD BE 0), OR NOT ACKNOWLEDGE (BIT SHOULD BE 1) P STOP CONDITION PEC PACKET ERROR CODE MASTER TO SLAVE SLAVE TO MASTER ... CONTINUATION OF PROTOCOL 3882 F03 Figure 3. PMBus Packet Protocol Diagram Element Key 1 7 S 1 1 SLAVE ADDRESS Rd/Wr A 1 P 3882 F04 Figure 4. Quick Command Protocol 1 S 1 1 SLAVE ADDRESS Wr A COMMAND CODE A 7 1 1 8 P 3882 F05 Figure 5. Send Byte Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 1 PEC A P 3882 F06 Figure 6. Send Byte Protocol with PEC Rev. C 32 For more information www.analog.com LTC3882 OPERATION 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 DATA BYTE A 1 P 3882 F07 Figure 7. Write Byte Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 1 DATA BYTE A PEC A P 3882 F08 Figure 8. Write Byte Protocol with PEC 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 1 DATA BYTE LOW A DATA BYTE HIGH A P 3882 F09 Figure 9. Write Word Protocol 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 8 1 8 1 8 1 1 DATA BYTE LOW A DATA BYTE HIGH A PEC A P 3882 F10 Figure 10. Write Word Protocol with PEC 1 S 7 1 1 8 1 1 7 1 1 8 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 1 DATA BYTE 1 NA P 3882 F11 Figure 11. Read Byte Protocol 1 S 7 1 1 8 1 1 7 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 8 1 1 DATA BYTE A PEC A P 3882 F12 Figure 12. Read Byte Protocol with PEC 1 S 7 1 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A 1 7 1 1 Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE LOW A 8 1 1 DATA BYTE HIGH NA P 3882 F13 Figure 13. Read Word Protocol 1 S 7 1 1 8 1 1 7 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE LOW A 8 1 DATA BYTE HIGH A 8 1 1 PEC A P 3882 F14 Figure 14. Read Word Protocol with PEC 1 S 7 1 1 8 1 1 7 1 1 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 8 DATA BYTE 1 A DATA BYTE 2 1 … A … 8 DATA BYTE N 8 1 BYTE COUNT = N A 1 … 1 NA P 3882 F15 Figure 15. Block Read Protocol Rev. C For more information www.analog.com 33 LTC3882 OPERATION 1 S 7 1 1 8 1 1 7 1 1 8 SLAVE ADDRESS Wr A COMMAND CODE A Sr SLAVE ADDRESS Rd A 8 1 8 DATA BYTE 1 A DATA BYTE 2 1 … A … 1 BYTE COUNT = N A 8 1 8 DATA BYTE N A PEC 1 … 1 NA P 3882 F16 Figure 16. Block Read Protocol with PEC 1 S 7 1 1 8 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A 8 1 DATA BYTE 2 1 7 1 8 A … 1 Sr SLAVE ADDRESS Rd A 1 8 A … … 1 BYTE COUNT = N A 8 DATA BYTE 2 1 A A … DATA BYTE M 8 8 DATA BYTE 1 8 1 DATA BYTE 1 A 1 DATA BYTE N … 1 NA P 3882 F17 Figure 17. Block Write – Block Read Process Call 1 S 7 1 1 8 1 8 1 SLAVE ADDRESS Wr A COMMAND CODE A BYTE COUNT = M A 8 DATA BYTE 2 1 7 1 1 Sr SLAVE ADDRESS Rd A 8 1 DATA BYTE 2 1 … A … A … 8 1 A … 1 DATA BYTE M 8 8 DATA BYTE 1 A … 1 BYTE COUNT = N A 8 DATA BYTE 1 8 1 8 DATA BYTE N A PEC A 1 … 1 NA P 3882 F18 Figure 18. Block Write – Block Read Process Call with PEC 1 7 1 1 8 1 1 S ALERT RESPONSE Rd A DEVICE ADDRESS NA P ADDRESS 3882 F19 Figure 19. Alert Response Address Protocol 1 7 1 1 8 1 S ALERT RESPONSE Rd A DEVICE ADDRESS A ADDRESS 8 PEC 1 1 NA P 3882 F20 Figure 20. Alert Response Address Protocol with PEC Rev. C 34 For more information www.analog.com LTC3882 OPERATION Serial Bus Timeout Serial Communication Errors The LTC3882 implements a timeout feature to avoid hanging the serial interface. The data packet timer begins running at the first START event before the SLAVE ADDRESS write byte and ends with the STOP bit. Packet transmission must be completed before the timer expires, or the LTC3882 will tri-state the bus and ignore all message data. The data packet includes the SLAVE ADDRESS byte, COMMAND CODE byte, repeated START and SLAVE ADDRESS byte (if a read operation), all ACKNOWLEDGE and flow control bits (R/W) and all data bytes. The LTC3882 supports the optional PMBus packet error checking protocol. This protocol appends a packet error code (PEC) to the end of applicable message transfers to improve communication reliability. The PEC is a CRC-8 error-checking byte calculated by the bus device sending the last data byte. Refer to SMBus specification 1.2 or higher for additional implementation details. All LTC3882 read operations will return a valid PEC if the bus master requests it. If bit 2 in the MFR_CONFIG_ALL_LTC3882 command is set, the IC will not act in response to a bus write operation unless a valid PEC is also received from the host. The packet timer is typically set to 30ms. If bit 3 of MFR_CONFIG_ALL_LTC3882 is set, this period is extended to 255ms. The LTC3882 automatically allows a packet transmission time of 255ms for MFR_FAULT_LOG block reads regardless of the setting of this bit. In no circumstances will the timeout period be less than the tTIMEOUT specification (25ms minimum). The LTC3882 supports the full PMBus frequency range of 10kHz to 400kHz. PEC errors on command writes, attempts to access unsupported commands, or writing invalid data to supported commands all cause the LTC3882 to generate a CML fault. The CML bit is then set in the STATUS_BYTE and STATUS_WORD commands, and the appropriate bit is set in the STATUS_CML command. Rev. C For more information www.analog.com 35 LTC3882 PMBus COMMAND SUMMARY PMBus Commands Table 7 lists supported PMBus commands and manufacturer specific commands. Additional information about these commands can be found in Revision 1.2 of Part II of the PMBus Power System Management Protocol Specification that can be found at http://www.pmbus.org/specs.html. Users are encouraged to reference that manual. Exceptions or manufacturer-specific implementations are detailed in the tables below. All standard PMBus commands from 0x00 through 0xCF not listed in this table are implicitly not supported by the LTC3882. All commands from 0xD0 through 0xFF not listed in this table are implicitly reserved by the manufacturer. The LTC3882 may execute additional commands not listed in this table, and these can change without notice. Reading these unlisted commands is harmless to the operation of the IC. Writes to any unsupported or reserved command should be avoided, as they may result in a CML fault and/or undesired operation of the part. If PMBus commands are received faster than they are being processed, the part may become too busy to handle new commands. In these cases the LTC3882 follows the protocols defined in the PMBus Specification V1.2, Part II, Section 10.8.7, to communicate that it is busy. This device includes handshaking features to eliminate busy responses, simplify error handling software and ensure robust communication and system behavior. Please refer to PMBus Communication and Command Processing in the Applications Information section for further details. LTC has made an effort to establish PMBus command compatibility and functional uniformity among its family of parts. However, differences may occur due to specific product requirements. Compatibility of PMBus commands among any ICs should not be assumed based simply on command name. Always refer to the manufacturer’s data sheet of each device for a complete definition of a command function. Data Formats PMBus supports specific floating point number formats and allows for a wide range of other data formats. Table 6 describes the data formats used by the LTC3882. Abbreviations of these formats appear throughout this document. Table 6. Abbreviations of Supported Data Formats PMBus TERMINOLOGY SPECIFICATION LTC REFERENCE TERMINOLOGY DEFINITION L11 Linear Part II ¶7.1 Linear_5s_11s L16 Linear VOUT_MODE Part II ¶8.2 Linear_16u CF DIRECT Part II ¶7.2 varies Reg register bits Part II ¶10.3 Reg ASC text characters Part II ¶22.2.1 ASCII Floating point 16-bit data: value = Y • 2N, where N = b[15:11] and Y = b[10:0], both two’s compliment binary integers. EXAMPLE b[15:0] = 0x9807 = 10011_000_0000_0111 value = 7 • 2–13 = 854E-6 Floating point 16-bit data: value = Y • 2–12, b[15:0] = 0x4C00 = 0100_1100_0000_0000 where Y = b[15:0], an unsigned integer. value = 19456 • 2–12 = 4.75 16-bit data with a custom format defined in the detailed PMBus command description. Often an unsigned or two’s compliment integer. Per-bit meaning defined in detailed PMBus PMBus STATUS_BYTE command. command description. ISO/IEC 8859-1 [A05] LTC (0x4C5443) Rev. C 36 For more information www.analog.com LTC3882 PMBus COMMAND SUMMARY Table 7. PMBus Command Summary COMMAND NAME CMD CODE DESCRIPTION PAGE 0x00 Channel (page) presently selected for any paged command. R/W Byte N Reg OPERATION 0x01 On, off and margin control. R/W Byte Y Reg ON_OFF_CONFIG 0x02 RUN pin and PMBus on/off command configuration. R/W Byte Y Reg CLEAR_FAULTS 0x03 Clear all set fault bits. Send Byte N 88 PAGE_PLUS_WRITE 0x05 Write a command directly to a specified page. W Block N 67 PAGE_PLUS_READ 0x06 Read a command directly from a specified page. Block R/W Process N 68 WRITE_PROTECT 0x10 Protect the device against unintended PMBus modifications. R/W Byte N STORE_USER_ALL 0x15 Store entire operating memory in EEPROM. Send Byte N 100 RESTORE_USER_ALL 0x16 Restore entire operating memory from EEPROM. Send Byte N 100 CAPABILITY 0x19 Summary of supported optional PMBus features. R Byte N Reg SMBALERT_MASK 0x1B Mask ALERT activity Block R/W Y Reg VOUT_MODE 0x20 Voltage-related format (Linear) and exponent. R Byte Y Reg VOUT_COMMAND 0x21 Nominal VOUT value. R/W Word Y L16 V VOUT_MAX 0x24 Maximum VOUT that can be set by any command, including margin. R/W Word Y L16 VOUT_MARGIN_HIGH 0x25 VOUT at high margin, must be greater than VOUT_COMMAND. R/W Word Y VOUT_MARGIN_LOW 0x26 VOUT at low margin, must be less than VOUT_COMMAND. R/W Word VOUT_TRANSITION_RATE 0x27 VOUT slew rate for programmed output changes. FREQUENCY_SWITCH 0x33 VIN_ON TYPE DATA PAGED FORMAT DEFAULT VALUE SEE PAGE 0x00 67 l 0x80 71 l 0x1E 70 UNITS NVM Reg l 0x00 68 0xB0 69 see CMD details 97 0x14 2–12 77 l 1.0V 0x1000 77 V l 5.5V 0x5800 78 L16 V l 1.05V 0x10CD 78 Y L16 V l 0.95V 0x0F33 78 R/W Word Y L11 V/ms l 0.25 0xAA00 82 PWM frequency control. R/W Word N L11 kHz l 500kHz 0xFBE8 72 0x35 Minimum input voltage to begin power conversion. R/W Word N L11 V l 6.5V 0xCB40 76 VIN_OFF 0x36 Decreasing input voltage at which power R/W Word conversion stops. N L11 V l 6.0V 0xCB00 76 IOUT_CAL_GAIN 0x38 Ratio of ISENSE± voltage to sensed current. R/W Word Y L11 mΩ l 0.63mΩ 0xB285 80 VOUT_OV_FAULT_LIMIT 0x40 VOUT overvoltage fault limit. R/W Word Y L16 V l 1.1V 0x119A 78 VOUT_OV_FAULT_RESPONSE 0x41 VOUT overvoltage fault response. R/W Byte Y Reg VOUT_OV_WARN_LIMIT 0x42 VOUT overvoltage warning limit. R/W Word Y L16 l V l 0xB8 93 l 1.075V 0x1133 79 Rev. C For more information www.analog.com 37 LTC3882 PMBus COMMAND SUMMARY Table 7. PMBus Command Summary COMMAND NAME CMD CODE DESCRIPTION DEFAULT VALUE SEE PAGE VOUT_UV_WARN_LIMIT 0x43 VOUT undervoltage warning limit. R/W Word Y L16 V l 0.925V 0x0ECD 79 VOUT_UV_FAULT_LIMIT 0x44 VOUT undervoltage fault limit. R/W Word Y L16 V l 0.9V 0x0E66 79 VOUT_UV_FAULT_RESPONSE 0x45 VOUT undervoltage fault response. R/W Byte Y Reg l 0xB8 93 IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 l 29.75A 0xDBB8 80 IOUT_OC_FAULT_RESPONSE 0x47 Output overcurrent fault response. R/W Byte Y Reg l 0x00 94 IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A l 20.0A 0xDA80 80 OT_FAULT_LIMIT 0x4F External overtemperature fault limit. R/W Word Y L11 °C l 100.0°C 0xEB20 83 OT_FAULT_RESPONSE 0x50 External overtemperature fault response. R/W Byte Y Reg l 0xB8 95 °C l OT_WARN_LIMIT 0x51 External overtemperature warning limit. R/W Word Y L11 85.0°C 0xEAA8 83 UT_FAULT_LIMIT 0x53 External undertemperature fault limit. R/W Word Y L11 °C l –40.0°C 0xE580 84 UT_FAULT_RESPONSE 0x54 External undertemperature fault response. R/W Byte Y Reg l 0xB8 95 VIN_OV_FAULT_LIMIT 0x55 VIN overvoltage fault limit. R/W Word N L11 l 15.5V 0xD3E0 76 VIN_OV_FAULT_RESPONSE 0x56 VIN overvoltage fault response. R/W Byte Y Reg l 0x80 92 VIN_UV_WARN_LIMIT 0x58 VIN undervoltage warning limit. R/W Word N L11 V l 6.3V 0xCB26 76 TON_DELAY 0x60 Delay from RUN pin or OPERATION ON command to TON_RISE ramp start. R/W Word Y L11 ms l 0.0ms 0x8000 81 TON_RISE 0x61 Time for VOUT to rise from 0.0V to VOUT_COMMAND after TON_DELAY. R/W Word Y L11 ms l 8.0ms 0xD200 81 TON_MAX_FAULT_LIMIT 0x62 Maximum time for VOUT to rise above VOUT_UV_FAULT_LIMIT after TON_DELAY. R/W Word Y L11 ms l 10.0ms 0xD280 82 TON_MAX_FAULT_RESPONSE 0x63 Fault response when TON_MAX_FAULT_ LIMIT is exceeded. R/W Byte Y Reg l 0xB8 96 TOFF_DELAY 0x64 Delay from RUN pin or OPERATION OFF command to TOFF_FALL ramp start. R/W Word Y L11 ms l 0.0ms 0x8000 82 TOFF_FALL 0x65 Time for VOUT to fall to 0.0V from VOUT_COMMAND after TOFF_DELAY. R/W Word Y L11 ms l 8.0ms 0xD200 82 TOFF_MAX_WARN_ LIMIT 0x66 Maximum time for VOUT to decay below 12.5% of VOUT_COMMAND after TOFF_FALL completes. R/W Word Y L11 ms l 150ms 0xF258 82 STATUS_BYTE 0x78 One-byte channel status summary. R/W Byte Y Reg 84 STATUS_WORD 0x79 Two-byte channel status summary. R/W Word Y Reg 85 STATUS_VOUT 0x7A VOUT fault and warning status. R/W Byte Y Reg 85 STATUS_IOUT 0x7B IOUT fault and warning status. R/W Byte Y Reg 85 STATUS_INPUT 0x7C Input supply fault and warning status. R/W Byte N Reg 86 TYPE DATA PAGED FORMAT UNITS NVM A V Rev. C 38 For more information www.analog.com LTC3882 PMBus COMMAND SUMMARY Table 7. PMBus Command Summary COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE SEE PAGE STATUS_TEMPERATURE 0x7D External temperature fault and warning status. R/W Byte Y Reg 86 STATUS_CML 0x7E Communication, memory and logic fault and warning status. R/W Byte N Reg 86 STATUS_MFR_ SPECIFIC 0x80 LTC3882-specific status. R/W Byte Y Reg 87 READ_VIN 0x88 Measured VIN. R Word N L11 READ_VOUT 0x8B Measured VOUT. R Word Y READ_IOUT R Word Y READ_TEMPERATURE_1 0x8C Measured IOUT. 0x8D Measured external temperature. R Word Y READ_TEMPERATURE_2 0x8E Measured internal temperature. R Word N READ_DUTY_CYCLE 0x94 Measured commanded PWM duty cycle. R Word READ_FREQUENCY 0x95 Measured PWM input clock frequency. READ_POUT 0x96 Calculated output power. PMBUS_REVISION 0x98 MFR_ID 0x99 MFR_MODEL MFR_SERIAL V 90 L16 V 90 L11 A 90 L11 °C 91 L11 °C 91 Y L11 % 91 R Word Y L11 kHz 91 R Word Y L11 W 90 Supported PMBus version. R Byte N Reg 0x22 V1.2 69 Manufacturer identification. R String N ASC LTC 101 0x9A LTC model number. R String N ASC LTC3882 101 0x9E R Block N ASC R Word Y L16 Device serial number. 101 LTC3882 Custom Commands MFR_VOUT_MAX 0xA5 Maximum value of any VOUT related command. V 5.6V 0x599A 77 USER_DATA_00 0xB0 EEPROM word reserved for LTpowerPlay. R/W Word N Reg l 101 USER_DATA_01 0xB1 EEPROM word reserved for LTpowerPlay. R/W Word Y Reg l 101 USER_DATA_02 0xB2 EEPROM word reserved for OEM use. R/W Word N Reg l USER_DATA_03 0xB3 EEPROM word available for general data storage. R/W Word Y Reg l 0x0000 101 USER_DATA_04 0xB4 EEPROM word available for general data storage. R/W Word N Reg l 0x0000 101 R Word N Reg 101 MFR_INFO 0xB6 Manufacturer Specific Information MFR_EE_UNLOCK 0xBD (contact the factory) NA 101 MFR_EE_ERASE 0xBE (contact the factory) 101 MFR_EE_DATA 0xBF (contact the factory) MFR_CHAN_CONFIG_LTC3882 0xD0 LTC3882 channel-specific configuration. 88 101 R/W Byte Y Reg l 0x1D 74 MFR_CONFIG_ALL_LTC3882 0xD1 LTC3882 device-level configuration. R/W Byte N Reg l 0x01 70 MFR_GPIO_PROPAGATE_ LTC3882 0xD2 Configure LTC3882 status propagation via GPIOn pins. R/W Word Y Reg l 0x6993 98 MFR_VOUT_AVP 0xD3 Specify VOUT load line. R/W Word Y L11 l 0% 0x8000 78 MFR_PWM_MODE_LTC3882 0xD4 LTC3882 channel-specific PWM mode control. R/W Byte Y Reg l 0x48 75 MFR_GPIO_RESPONSE 0xD5 PWM response when GPIOn pin is low. R/W Byte Y Reg l 0xC0 98 MFR_OT_FAULT_RESPONSE 0xD6 Internal overtemperature fault response. R Byte N Reg 0xC0 95 % Rev. C For more information www.analog.com 39 LTC3882 PMBus COMMAND SUMMARY Table 7. PMBus Command Summary COMMAND NAME CMD CODE DESCRIPTION TYPE DATA PAGED FORMAT UNITS NVM DEFAULT VALUE SEE PAGE MFR_IOUT_PEAK 0xD7 Maximum IOUT measurement since last MFR_CLEAR_PEAKS. R Word Y L11 A 90 MFR_RETRY_DELAY 0xDB Minimum time before retry after a fault. R/W Word Y L11 ms l 350ms 0xFABC 96 MFR_RESTART_DELAY 0xDC Minimum time RUN pin is held low by the LTC3882. R/W Word Y L11 ms l 500ms 0xFBE8 81 MFR_VOUT_PEAK 0xDD Maximum VOUT measurement since last MFR_CLEAR_PEAKS. R Word Y L16 V 90 MFR_VIN_PEAK 0xDE Maximum VIN measurement since last MFR_CLEAR_PEAKS. R Word N L11 V 90 MFR_TEMPERATURE_1_PEAK 0xDF Maximum external temperature measurement since last MFR_CLEAR_ PEAKS. R Word Y L11 °C 91 MFR_CLEAR_PEAKS 0xE3 Clear all peak values. Send Byte N MFR_PADS_LTC3882 0xE5 State of selected LTC3882 pads. R Word N Reg MFR_ADDRESS 0xE6 Specify right-justified 7-bit device address. R/W Byte N Reg MFR_SPECIAL_ID 0xE7 Manufacturer code representing the LTC3882. R Word N Reg MFR_FAULT_LOG_STORE 0xEA Force transfer of fault log from operating Send Byte memory to EEPROM. N MFR_FAULT_LOG_CLEAR 0xEC Clear existing EEPROM fault log. Send Byte N MFR_FAULT_LOG 0xEE Read fault log data. R Block N Reg 99 MFR_COMMON 0xEF LTC-generic device status reporting. R Byte N Reg 88 MFR_COMPARE_USER_ALL 0xF0 Compare operating memory with EEPROM contents. Send Byte N MFR_TEMPERATURE_2_PEAK 0xF4 Maximum internal temperature measurement since last MFR_CLEAR_PEAKS. R Word N L11 MFR_PWM_CONFIG_LTC3882 0xF5 LTC3882 PWM configuration common to R/W Byte both channels. N Reg MFR_IOUT_CAL_GAIN_TC 0xF6 Output current sense element temperature coefficient. R/W Word Y CF MFR_TEMP_1_GAIN 0xF8 Slope for external temperature calculations. R/W Word Y CF MFR_TEMP_1_OFFSET 0xF9 Offset addend for external temperature calculations. R/W Word Y L11 MFR_RAIL_ADDRESS 0xFA Specify unique right-justified 7-bit address for channels comprising a PolyPhase output. R/W Byte Y Reg MFR_RESET 0xFD Force full reset without removing power. Send Byte N 91 87 l 0x4F 69 0x420X 101 101 99 100 °C ppm/°C °C or V 91 l 0x14 73 l 3900ppm/°C 0x0F3C 80 l 1.0 0x4000 83 l 0.0 0x8000 83 l 0x80 69 71 NVM l Indicates a command value stored to internal EEPROM using STORE_USER_ALL or restored to RAM from internal EEPROM at power-up or execution of RESTORE_USER_ALL or MFR_RESET. Rev. C 40 For more information www.analog.com LTC3882 APPLICATIONS INFORMATION Efficiency Considerations Normally, one of the primary goals of any LTC3882 application will be to obtain the highest practical conversion efficiency. The efficiency of a switching regulator is equal to the output power divided by the input power. It is often useful to analyze individual losses to determine what is limiting the efficiency and to ascertain which change would produce the most improvement. Balancing or limiting these individual losses plays a dominant role in the component selection process outlined over the next few sections. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + …) where L1, L2, et al, are the individual losses as a percentage of input power: 100 • PLn /PIN. Although all dissipative elements in the system produce losses, four main sources usually account for most of the losses in LTC3882 applications: IC supply current, I2R losses, topside power MOSFET transition losses and total gate drive current. 1. The LTC3882 IC supply current is a DC value given in the Electrical Characteristics table. The absolute loss created by the IC itself is approximately this current times the VCC supply voltage. IC supply current typically results in a small loss (> VOUT, the top MOSFET on-resistance MILLER EFFECT VGS QA QB QIN CMILLER = (QB – QA)/VDS 3882 F21 Figure 21. Typical MOSFET Gate Charge Curve CMILLER is the most important selection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. CMILLER is equal to the increase in gate charge along the horizontal axis of Figure 21 while the curve is approximately flat, divided by the specified change in VDS. This result is then multiplied by the ratio of the actual application VDS to the VDS specified on the gate charge curve. When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: V Main Switch Duty Cycle = OUT VIN V –V Synchronous Switch Duty Cycle = IN OUT VIN Rev. C 42 For more information www.analog.com LTC3882 APPLICATIONS INFORMATION The power dissipation for the main and synchronous MOSFETs at maximum output current are given by: V 2 PMAIN = OUT (IMAX ) (1+ δ)R DS(ON) + VIN VIN 2 IMAX 2 voltage rating of the MOSFET. If this ringing cannot be avoided and exceeds the maximum rating of the device, choose a higher voltage rated MOSFET. MOSFET Driver Selection (RDR ) ( CMILLER ) • ⎡ 1 1 ⎤ + ⎢ ⎥ ( fPWM ) ⎢⎣ VGG – VTH(IL) VTH(IL) ⎥⎦ V –V 2 PSYNC = IN OUT (IMAX ) (1+ δ)R DS(ON) VIN where δ is the temperature dependency of RDS(ON), RDR is the effective top driver resistance, VIN is the drain potential and the change in drain potential in the particular application. VGG is the applied gate voltage, VTH(IL) is the typical gate threshold voltage specified in the power MOSFET data sheet at the specified drain current, and CMILLER is the capacitance calculated using the technique previously described. The term (1 + δ) is generally given for a MOSFET in the form of a normalized RDS(ON) versus temperature curve. Typical values for δ range from 0.005/°C to 0.01/°C depending on the particular MOSFET used. Both MOSFETs have I2R losses while the topside N-channel losses also include transition losses, which are highest at high input voltages. For VIN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CMILLER actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. Multiple MOSFETs can be used in parallel to lower RDS(ON) and meet the current and thermal requirements if desired. If using discrete drivers and MOSFETs, check the stress on the MOSFETs by independently measuring the drainto-source voltages directly across the device terminals. Beware of inductive ringing that could exceed the maximum Gate driver ICs, DrMOS devices and power blocks with an interface compatible with the LTC3882 3.3V PWM control output(s) can be used. An external resistor divider may be needed to set three-state control voltage outputs to midrail while in the high impedance state, depending on the driver selected. In some cases an external pull-up resistor may be necessary to connect an open-drain enable control to a particular FET driver. These external driver/power circuits do not typically present a heavy capacitive load to the LTC3882 PWM outputs. Suitable drivers such as the LTC4449 are capable of driving large gate capacitances at high transition rates. In fact, when driving MOSFETs with very low gate charge, it is sometimes helpful to slow down the drivers by adding small gate resistors (5Ω or less) to reduce noise and EMI caused by fast transitions. Using PWM Protocols For successful utilization of the driver selected, the appropriate LT3882 PWM control protocol must be programmed. The LTC3882 supports a wide range of PWM control protocols. See bits[2:1] of the MFR_PWM_MODE_LTC3882 PMBus command. When the LTC3882 first initializes, a basic 1-wire, 3-state control is selected. This places the PWM pin in high impedance and loads EN with a light pull-down test current. In this protocol (bits[2:1] = 0x0), EN functions as an input to select an additional sub-protocol feature. If EN is left floating or tied to ground, DCM operation is allowed. If EN is wired to VDD33 (a 3.3k pull-up is recommended), then all DCM operation is disabled, even during soft-start and regardless of the state of MFR_PWM_MODE_LTC3882 bit 0. The first of these sub-protocols is for drivers controlled by a single 3-state input that have sufficiently short delay to the diode emulation state (both top and bottom power MOSFETs disabled in a fraction of a PWM cycle), such as the LTC4449. The second sub-protocol handles all other 3.3V compatible drivers with a single 3-state control input. Rev. C For more information www.analog.com 43 LTC3882 APPLICATIONS INFORMATION The LTC3882 may require as much as 35ms from the beginning of initialization to retrieve and set the programmed protocol from EEPROM. This protocol is always applied before any PWM operation begins. However, if the initialization is due to a rapidly applied VIN system supply, the LTC3882 PWM outputs may not be in the best state to maintain the desired level of power FET control during this period. This is especially true if VCC powers the controller and also has ramp-up delay after VIN is applied. In the case of rapidly applied VIN, the system supply will immediately be available to provide power to the top FET, and the high impedance PWM output(s) can easily be moved with dV/dt current through parasitic capacitances. This situation could result in damage to the power stage or loss of VOUT control, depending on the power state design. It is highly recommended that a resistor no larger than 10k be considered to help maintain power stage control during initialization in the following cases. For protocol 0x1, this resistor should be placed between EN and ground. For protocol 0x3, this resistor should be placed between TG and ground. For protocol 0x2, it may be necessary to actively pull EN low with an external signal FET controlled by a separate POR circuit. Careful evaluation of the actual power stage during power-up is recommended to determine if these additional safety measures are needed. CIN Selection The input bypass capacitance for an LTC3882 circuit needs to have ESR low enough to keep the supply drop low as the top MOSFETs turn on, RMS current capability adequate to withstand the ripple current at the input, and a capacitance value large enough to maintain the input voltage until the input supply can make up the difference. Generally, a capacitor that meets the first two requirements (particularly a non-ceramic type) will have far more capacitance than is required to keep capacitance-based droop under control. The input capacitance voltage rating should be at least 1.4 times the maximum input voltage. Power loss due to ESR occurs as I2R dissipation in the capacitor itself. The input capacitor RMS current and its impact on any preceding input network is reduced by PolyPhase architecture. It can be shown that the worst case RMS current occurs when only one controller is operating. The controller with the highest (VOUT)(IOUT) product should be used to determine the maximum RMS current requirement. Increasing the output current drawn from the other out-of-phase controller will decrease the input RMS ripple current from this maximum value. Two channel out-of-phase operation typically reduces the input capacitor RMS ripple current by a factor of 30% to 70%. In continuous inductor conduction mode, the source current of the top power MOSFET is approximately a square wave of duty cycle VOUT/VIN. The maximum RMS capacitor current in this case is given by: IRMS ≈ IOUT(MAX) VOUT ( VIN – VOUT ) VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2 This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that manufacturer ripple current ratings for capacitors are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the manufacturer if there is any question. Ceramic, tantalum, semiconductor electrolyte (OS-CON), hybrid conductive polymer (SUNCON) and switcher-rated electrolytic capacitors can be used as input capacitors, but each has drawbacks. Ceramics have high voltage coefficients of capacitance and may have audible piezoelectric effects; tantalums need to be surge-rated; OS-CONs suffer from higher inductance, larger case size and limited surface mount applicability; and electrolytic capacitors have higher ESR and can dry out. Sanyo OS-CON SVP(D) series, Sanyo POSCAP TQC series, or Panasonic EE-FT series aluminum electrolytic capacitors can be used in parallel with a couple of high performance ceramic capacitors as an effective means of achieving low ESR and high bulk capacitance. Rev. C 44 For more information www.analog.com LTC3882 APPLICATIONS INFORMATION In addition to PWM bulk input capacitance, a small (0.01μF to 1μF) bypass capacitor between the chip VINSNS pin and ground, placed close to the LTC3882, is also suggested. A small resistor placed between the bulk CIN and the VINSNS pin provides further isolation between the two channels. However, if the time constant of any such R-C network on the VINSNS pin exceeds 30ns, dynamic line transient response can be adversely affected. COUT Selection The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple ΔVOUT is approximately bounded by: ⎛ ⎞ 1 ΔVOUT ≤ ΔIL ⎜ ESR + 8 • f PWM • C OUT ⎟⎠ ⎝ where ΔIL is the inductor ripple current. ΔIL = VOUT ⎛ VOUT ⎞ 1– L • f PWM ⎜⎝ VIN ⎟⎠ Since ΔIL increases with input voltage, the output ripple voltage is highest at maximum input voltage. Typically once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Manufacturers such as Sanyo, Panasonic and Cornell Dubilier should be considered for high performance throughhole capacitors. The OS-CON semiconductor electrolyte capacitor available from Sanyo has a good (ESR)(size) product. An additional ceramic capacitor in parallel with polarized capacitors is recommended to offset the effect of lead inductance. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or transient current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent output capacitor choices include the Sanyo POSCAP TPD/E/F series, the Kemet T520, T530 and A700 series, NEC/Tokin NeoCapacitors and Panasonic SP series. Other suitable capacitor types include Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. Feedback Loop Compensation The LTC3882 is a voltage mode controller with a second, dedicated current sharing loop to provide excellent phaseto-phase current sharing in PolyPhase applications. The current sharing loop is internally compensated. While Type 2 compensation for the voltage control loop may be adequate in some applications (such as with the use of high ESR bulk capacitors), Type 3 compensation and ceramic capacitors are recommended for optimum transient response. Figure 22 shows a simplified view of the error amplifier EA for one LTC3882 channel. The positive input of the error amplifier is connected to the output of an internal 12-bit DAC fed by a 1.024V reference, while the negative input is connected to the FB pin and other internal circuits (not all shown). R1 is internal to the IC with a value range given by the RVSFB parameter in the Electrical Characteristics table. The output is connected to COMP, from which the PWM controller derives the required output duty cycle. To speed up overshoot recovery time, the maximum potential at the COMP pin is internally clamped. C2 VOUT C3 R1 INTERNAL C1 R2 R3 – FB VDAC + EA COMP 3882 F22 Figure 22. Type 3 Compensation Circuit Unlike many regulators that use a transconductance (gm) amplifier, the LTC3882 is designed to use an inverting summing amplifier topology with the FB pin configured as a virtual ground. This allows feedback gain to be tightly controlled by external components, which is not possible with a simple gm amplifier. The voltage feedback amplifier Rev. C For more information www.analog.com 45 LTC3882 APPLICATIONS INFORMATION 0 –1 GAIN +1 –1 PHASE (DEG) GAIN (dB) also provides flexibility in choosing pole and zero locations. In particular, it allows the use of Type 3 compensation to provide phase boost at the LC pole frequency for significantly improving the control loop phase margin, as shown in Figure 23. FREQ –180 BOOST –270 –380 The transfer function of the Type 3 circuit shown in Figure 22 is given by the following equation: VCOMP –90 PHASE ESR, and the roll-off due to the capacitor will stop, leaving –20dB/decade and 90° of phase shift. 3882 F23 Figure 23. Type 3 Compensation Frequency Response In a typical LTC3882 circuit, the feedback loop closed around this control amplifier and compensation network consists of the line feedforward circuit, the modulator, the external inductor and the output capacitor. All these components affect loop behavior and need to be accounted for in the frequency compensation. The modulator consists of the PWM generator, the output MOSFET drivers and the external MOSFETs themselves. Step-down modulator gain varies linearly with the input voltage. The line feedforward circuit compensates for this change in gain, and provides a constant gain AMOD of 4V/V from the error amplifier output COMP to the inductor input (average DC voltage) regardless of VIN. The combination of the line feedforward circuit and the modulator looks like a linear voltage transfer function from COMP to the inductor input with a fairly benign AC behavior at typical loop compensation frequencies. Significant phase shift will not begin to occur in this transfer function until half the switching frequency. The external inductor/output capacitor combination makes a more significant contribution to loop behavior. These components cause a 2nd order amplitude roll-off that filters the PWM waveform, resulting in the desired DC output voltage. But the additional 180° phase shift produced by this filter causes stability issues in the feedback loop and must be frequency compensated. At higher frequencies, the reactance of the output capacitor will approach its VOUT = –(1+ sC1R2)[1+ s(R1+ R3)C3] sR1(C1+ C2)[1+ s(C1//C2)R2](1+ sC3R3) The RC network across the error amplifier and the feedforward components R3 and C3 introduce two pole-zero pairs to obtain a phase boost at the system unity-gain (crossover) frequency, fC. In theory, the zeros and poles are placed symmetrically around fC, and the spread between the zeros and the poles is adjusted to give the desired phase boost at fC. However, in practice, if the crossover frequency is much higher than the LC double-pole frequency, this method of frequency compensation normally generates a phase dip within the unity bandwidth and creates some concern regarding conditional stability. If conditional stability is a concern, move the error amplifier zero to a lower frequency to avoid excessive phase dip. The following equations can be used to compute the feedback compensation component values: fLC = 1 2π LC OUT 1 fESR = 2πR ESRC OUT choose: f fC = crossover frequency = PWM 10 1 fZ1(ERR) = fLC = 2πR2C1 f 1 fZ2(RES) = C = 5 2π(R1+ R3)C3 fP1(ERR) = fESR = fP2(RES) = 5fC = 1 2πR2(C1//C2) 1 2πR3C3 Rev. C 46 For more information www.analog.com LTC3882 APPLICATIONS INFORMATION Required error amplifier gain at frequency fC is: 2 2 ⎛ f ⎞ ⎛ f ⎞ ≈ 40 log 1+ ⎜ C ⎟ – 20 log 1+ ⎜ C ⎟ – 15.56 ⎝ fLC ⎠ ⎝ fESR ⎠ Once the value of resistor R1 (function of selected VOUT range) and pole/zero locations have been decided, the value of R2, C1, C2, R3 and C3 can be obtained from the previous equations. Compensating a switching power supply feedback loop is a complex task. The applications shown in this data sheet provide typical values, optimized for the power components shown. Though similar power components should suffice, substantially changing even one major power component may degrade performance significantly. Stability also may depend on circuit board layout. To verify the calculated component values, all new circuit designs should be prototyped and tested for stability. The LTpowerCAD® software tool can be used as a guide through the entire power supply design process, including optimization of circuit component values according to system requirements. PCB Layout Considerations To prevent magnetic and electrical field radiation or high frequency resonant problems and to ensure correct IC operation, proper layout of the components connected to the LTC3882 is essential. Refer to Figure 24, which also illustrates current waveforms typically present in the circuit branches. RSENSE will be replaced with a dead short if DCR sensing is used. For maximum efficiency, the switch node rise and fall times should be minimized. The following PCB design priority list will help ensure proper topology. 1. Place a ground or DC voltage layer between a power layer and a small-signal layer. Generally, power planes should be placed on the top layer (4-layer PCB), or top and bottom layer if more than 4 layers are used. Use wide/short copper traces for power components and avoid improper use of thermal relief around power plane vias to minimize resistance and inductance. 2. Low ESR input capacitors should be placed as close as possible to switching FET supply and ground connections with the shortest copper traces possible. The switching FETs must be on the same layer of copper as the input capacitors with a common topside drain connection at CIN. Do not attempt to split the input decoupling for the two channels, as a large resonant loop can result. Vias should not be used to make these connections. Avoid blocking forced air flow to the switching FETs with large size passive components. 3. If using a discrete FET driver, place that IC close to the switching FET gate terminals, keeping the connecting traces short to produce clean drive signals. This rule also applies to driver IC supply and ground pins that connect to the switching FET source pins. The driver IC can be placed on the opposite side of the PCB from the switching FETs. 4. Place the inductor input as close as possible to the switching FETs. Minimize the surface area of the switch node. Make the trace width the minimum needed to support the maximum output current. Avoid copper fills or pours. Avoid running the connection on multiple copper layers in parallel. Minimize capacitance from the switch node to any other trace or plane. 5. Place the output current sense resistor (if used) immediately adjacent to the inductor output. PCB traces for remote voltage and current sense should be run together back to the LTC3882 in pairs with the smallest spacing possible on any given layer on which they are routed. Avoid high frequency switching signals and ideally shield with ground planes. Locate any filter component on these traces next to the LTC3882, and not at the Kelvin sense location. However, if DCR sensing is used, place the top resistor (R1, Figure 25) close to the switch node. 6. Place low ESR output capacitors adjacent to the sense resistor output and ground. Output capacitor ground connections must feed into the same copper that connects to the input capacitor ground before connecting back to system ground. Rev. C For more information www.analog.com 47 LTC3882 APPLICATIONS INFORMATION SW1 L1 RSENSE1 D1 VOUT1 COUT1 RL1 VIN RIN CIN SW0 BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. L0 RSENSE0 D0 VOUT0 COUT0 RL0 3882 F24 Figure 24. High Frequency Paths and Branch Current Waveforms 7. Connection of switching ground to system ground, small-signal analog ground or any internal ground plane should be single-point. If the system has an internal system ground plane, a good way to do this is to cluster vias into a single star point to make the connection. This cluster should be located directly beneath the IC GND paddle, which serves as both analog signal ground and the negative sense for VOUT1. A useful CAD technique is to make separate ground nets and use a 0Ω resistor to connect them to system ground. 8. Place all small-signal components away from high frequency switching nodes. Place decoupling capacitors for the LTC3882 immediately adjacent to the IC. 9. A good rule of thumb for via count in a given high current path is to use 0.5A per via. Be consistent when applying this rule. 10. Copper fills or pours are good for all power connections except as noted above in rule 3. Copper planes on multiple layers can also be used in parallel. This helps with thermal management and lowers trace inductance, which further improves EMI performance. Output Current Sensing The ISENSE+ and ISENSE– pins are high impedance inputs to internal current comparators, the current-sharing loop and telemetry ADC. The common mode range of the current sense inputs is approximately 0V to 5.5V. Continuous linear Rev. C 48 For more information www.analog.com LTC3882 APPLICATIONS INFORMATION operation is provided throughout this range. Maximum differential current sense input (ISENSE+ – ISENSE–) is 70mV, including any variation over temperature. These inputs must be properly connected in the application at all times. To maximize efficiency at full load the LTC3882 is designed to sense current through the inductor’s DCR, as shown in Figure 25. The DCR of the inductor represents the small amount of DC winding resistance of the copper, which for most inductors suitable to LTC3882 applications, is between 0.3mΩ and 1mΩ. If the filter RC time constant is chosen to be exactly equal to the L/DCR time constant of the inductor, the voltage drop across the external capacitor is equal to the voltage drop across the inductor DCR. Check the manufacturer’s data sheet for specifications regarding the inductor DCR in order to properly dimension the external filter components. The DCR of the inductor can also be measured using a good RLC meter. Use the nominal or measured value of DCR to program IOUT_CAL_GAIN (in mΩ). The temperature coefficient of the inductor’s DCR is typically high, like copper. Again, consult the manufacturer’s data sheet. The LTC3882 can adjust for this non-ideality if the correct MFR_IOUT_CAL_ GAIN_TC value is programmed. Typically this coefficient is around 3900ppm/°C. Resistor R1 should be placed close to the switch node, to prevent noise from coupling into sensitive small-signal nodes. Capacitor C1 should be placed close to the IC pins. An example of discrete resistor sensing of output current is shown in Figure 26. Previously, the parasitic inductance of VIN 12V VINSNS 5V LTC3882 VCC VDD33 PWM VCC BOOST INDUCTOR VLOGIC TG LTC4449 IN TS – + GND ISENSE ISENSE GND L DCR VOUT BG R1* C1* 3882 F25 R1 • C1 = L *PLACE R1 NEAR INDUCTOR DCR PLACE C1 NEAR I + – SENSE , ISENSE PINS Figure 25. Inductor DCR Output Current Sense VIN 12V VINSNS LTC3882 5V VCC VCC VDD33 VLOGIC TG LTC4449 IN TS PWM – + GND ISENSE ISENSE CF SENSE RESISTOR PLUS PARASITIC INDUCTANCE BOOST GND L BG RS ESL VOUT CF • 2RF ≤ ESL/RS POLE-ZERO CANCELLATION RF RF 3882 F26 FILTER COMPONENTS PLACED NEAR SENSE PINS Figure 26. Discrete Resistor Output Current Sense Rev. C For more information www.analog.com 49 LTC3882 APPLICATIONS INFORMATION the sense resistor could represent a relatively small error. New high current density solutions may utilize low sense resistor values producing sense voltages less than 20mV. In addition, inductor ripple currents greater than 50% with operation up to 1MHz are becoming more common. Under these conditions, the voltage drop across the sense resistor’s parasitic inductance is no longer negligible. An RC filter can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. For example, Figure 27 illustrates the voltage waveform across a 2mΩ resistor with a 2010 footprint. The waveform is the superposition of a purely resistive component and a purely inductive component. If the RC time constant is chosen to be close to the parasitic inductance divided by the sense resistor (L/R), the resultant waveform looks resistive, as shown in Figure 28. VRSENSE 20mV/DIV VESL(STEP) 500ns/DIV resistor to extract the magnitude of the ESL step and the following equation to determine the ESL. ESL = VESL(STEP) tON • tOFF • ∆IL tON + tOFF If low value (