LTC6603IUF#PBF

LTC6603 Dual Adjustable Lowpass Filter FEATURES DESCRIPTION n The LTC®6603 is a dual, matched, programmable lowpass filter for communications receivers and transmitters. The selectivity of the LTC6603, combined with its linear phase, phase matching and dynamic range, make it suitable for filtering in many communications systems. With 1.5° phase matching between channels, the LTC6603 can be used in applications requiring pairs of matched filters, such as transceiver I and Q channels. Furthermore, the differential inputs and outputs provide a simple interface for most communications systems. n n n n n n n n n n n Guaranteed Phase and Gain Matching Specs Programmable BW Up to 2.5MHz Programmable Gain (0dB/6dB/12dB/24dB) 9th Order Linear Phase Response Differential, Rail-to-Rail Inputs and Outputs Low Noise: –145dBm/Hz (Input Referred) Low Distortion: –75dBc at 200kHz Simple Pin Programming or SPI Interface Set the Max Speed/Power with an External R Operates from 2.7V to 3.6V Input Range from 0V to 5.5V 4mm × 4mm QFN Package APPLICATIONS n n n n Small/Low Cost Basestations: IDEN, PHS, TD-SCDMA, CDMA2000, WCDMA, UMTS Low Cost Repeaters, Radio Links, and Modems 802.11x Receivers JTRS L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. The sampled data filter does not require an external clock yet its cutoff frequency can be set with a single external resistor with an accuracy of 3.5% or better. The external resistor programs an internal oscillator whose frequency is divided prior to being applied to the filter networks. This allows up to three cutoff frequencies that can be obtained for each external resistor value, allowing the cutoff frequency to be programmed over a range of more than six octaves. Alternatively, the cutoff frequency can be set with an external clock. The filter gain can also be programmed to 1, 2, 4 or 16. The LTC6603 features a low power shutdown mode that can be programmed through the serial interface and is available in a 24-pin 4mm × 4mm QFN package. TYPICAL APPLICATION 2.5MHz I and Q Lowpass Filter and Dual ADC 5V 3V LTC2297 49.9Ω 100nH* 0.1μF 0.1μF Phase Matching 180pF 10pF 180pF 10pF I OUTPUT V+A V+D 49.9Ω 100nH* IIN QIN 30.9k 0.1μF +INA –INA –OUTA +INB +OUTB –INB LTC6603 –OUTB RBIAS CLKIO VOCM SER 180pF 49.9Ω 100nH* GAIN1 GAIN0 VS = 3V, BW = 156.25kHz f = 125kHz, TA = 25°C 1000 UNITS 40 49.9Ω 100nH* 10pF Q OUTPUT CAP 50 +OUTA 0.1μF BASEBAND GAIN CONTROL 14-BIT ADC CLKCNTL UNITS (%) V+IN 60 3V 20 14-BIT ADC 180pF 10pF 10 VCM 0 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 MISMATCH (DEG) 2.2μF SDO LPFO GND LPF1 1.5 2 2.5 6603 TA01b SDI GND 30 3V *COILCRAFT 0603HP 6603 TA01a 6603fa 1 LTC6603 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) +OUTA CAP GAIN0(D0) GAIN1 –INA +INA TOP VIEW 24 23 22 21 20 19 V+IN 1 18 –OUTA V+A 2 17 SER VOCM 3 16 V+D 25 RBIAS 4 15 CLKIO CLKCNTL 5 14 GND LPF1(CS) 6 –OUTB LPFO(SCLK) SDO 9 10 11 12 SDI 8 –INB 13 +OUTB 7 +INB V+IN to GND ................................................................6V V+A , V+D to GND .........................................................4V V+A to V+D .............................................. –0.3V to +0.3V Filter Inputs to GND ....................... –0.3V to V+IN + 0.3V Pins 3, 4 to GND ............................. –0.3V to V+A + 0.3V Pins 5, 6, 9-11, 15, 17, 21, 22 to GND ..................... –0.3V to V+D + 0.3V Output Short-Circuit Duration .......................... Indefinite Operating Temperature Range (Note 2) LTC6603CUF .......................................–40°C TO 85°C LTC6603IUF ........................................–40°C TO 85°C Specified Temperature Range (Note 3) LTC6603CUF ...........................................0°C TO 70°C LTC6603IUF ........................................–40°C TO 85°C Storage Temperature Range................... –65°C to 150°C UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN TJMAX = 150°C, θJA = 37°C/W, θJC = 4.3°C/W EXPOSED PAD (PIN 25) IS GND. MUST BE SOLDERED TO THE PCB. ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION LTC6603CUF#PBF LTC6603CUF#TRPBF 6603 24-Lead (4mm × 4mm) Plastic QFN 0°C to 70°C SPECIFIED TEMPERATURE RANGE LTC6603IUF#PBF LTC6603IUF#TRPBF 6603 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted. PARAMETER CONDITIONS Filter Gain Either Channel External Clock = 80MHz, Filter Cutoff (fC)= 156.25kHz, VIN = 3.6VP-P, Pin 3 Open DC Gain, Gain Set = 0dB fIN = 62.5kHz (0.4 • fC), Relative to DC Gain fIN = 125kHz (0.8 • fC), Relative to DC Gain fIN = 156.25kHz (fC), Relative to DC Gain fIN = 234.375kHz (1.5 • fC), Relative to DC Gain Matching of Filter Gain External Clock = 80MHz, Filter Cutoff (fC)= 156.25kHz, VIN = 3.6VP-P, Pin 3 Open DC Gain, Gain Set = 0dB fIN = 62.5kHz (0.4 • fC) fIN = 125kHz (0.8 • fC) fIN = 156.25kHz (fC) l l l l l l l l l MIN TYP MAX UNITS 0.25 –0.5 0.4 –0.6 0.4 –0.3 0.6 –0.4 –32 0.55 –0.1 0.8 –0.2 –29.5 dB dB dB dB dB ±0.03 ±0.03 ±0.03 ±0.03 ±0.1 ±0.1 ±0.1 ±0.15 dB dB dB dB 6603fa 2 LTC6603 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted. PARAMETER CONDITIONS Filter Phase Either Channel External Clock = 80MHz, Filter Cutoff (fC) = 156.25kHz, VIN = 3.6VP-P, Pin 3 Open fIN = 62.5kHz (0.4 • fC) fIN = 125kHz (0.8 • fC) fIN = 156.25kHz (fC) l l l Matching of Filter Phase External Clock = 80MHz, Filter Cutoff (fC) = 156.25kHz, VIN = 3.6VP-P, Pin 3 Open fIN = 62.5kHz (0.4 • fC) fIN = 125kHz (0.8 • fC) fIN = 156.25kHz (fC) l l l Filter Gain Either Channel External Clock = 80MHz, Filter Cutoff (fC) = 2.5MHz, VIN = 3.6VP-P, Pin 3 Open DC Gain, Gain Set = 0dB fIN = 1MHz (0.4 • fC), Relative to DC Gain fIN = 2MHz (0.8 • fC), Relative to DC Gain fIN = 2.5MHz (fC), Relative to DC Gain fIN = 4MHz (1.5 • fC), Relative to DC Gain l l l l l Matching of Filter Gain External Clock = 80MHz, Filter Cutoff (fC) = 2.5MHz, VIN = 3.6VP-P, Pin 3 Open fIN = 2MHz (0.8 • fC) fIN = 2.5MHz (fC) l l Filter Phase Either Channel External Clock = 80MHz, Filter Cutoff (fC) = 2.5MHz, VIN = 3.6VP-P, Pin 3 Open fIN = 1MHz (0.4 • fC) fIN = 2MHz (0.8 • fC) fIN = 2.5MHz (fC) l l l Matching of Filter Phase External Clock = 80MHz, Filter Cutoff (fC) = 2.5MHz, VIN = 3.6VP-P, Pin 3 Open fIN = 1MHz (0.4 • fC) fIN = 2MHz (0.8 • fC) fIN = 2.5MHz (fC) Filter Cutoff Accuracy CLKCNTL = 3V (Note 4) when Self Clocked RBIAS = 200k RBIAS = 54.9k RBIAS = 30.9k DC Gain DC Gain Matching Noise At 200kHz MIN TYP MAX UNITS 158 –44 –152 161 –39 –146 163 –36 –142 deg deg deg ±0.2 ±0.4 ±0.5 ±1.5 ±3 ±4 deg deg deg 0.5 –0.8 0.4 0.1 –43 1.2 –0.1 1.5 1 –32.6 dB dB dB dB dB ±0.05 ±0.2 ±0.2 ±0.4 dB dB 155 –39 –141 159 –28 –126 deg deg deg l l l ±2.5 ±4 ±4 deg deg deg l l l ±3 ±3 ±3.5 % % % 0.5 6 11.8 23.2 1.2 6.6 12.5 24 dB dB dB dB ±0.1 ±0.05 ±0.05 ±0.1 ±0.2 ±0.1 ±0.15 ±0.2 dB dB dB dB Filter Cutoff (fC) = 2.5MHz, 0.6V to 2.4V Each Output, Pin 3 Open Gain Setting = 0dB Gain Setting = 6dB Gain Setting = 12dB Gain Setting = 24dB l l l l Filter Cutoff (fC) = 2.5MHz, 0.6V to 2.4V Each Output, Pin 3 Open Gain Setting = 0dB Gain Setting = 6dB Gain Setting = 12dB Gain Setting = 24dB l l l l 0 –2 –0.7 –1.1 150 –45 –152 0 5.6 11.2 22.5 Voltage Noise Referred to the Input Gain = 0dB Gain = 6dB Gain = 12dB Gain = 24dB –124 –129 –135 –145 dBm/Hz dBm/Hz dBm/Hz dBm/Hz Noise Bandwidth = 5MHz, Referred to the Input Gain = 0dB Gain = 6dB Gain = 12dB Gain = 24dB –53 –59 –65 –76 dBm dBm dBm dBm THD VIN = 2VP-P, fIN = 200kHz, Gain Setting = 24dB –75 dB Input Impedance Gain = 24dB, RBIAS = 30.9k, Filter Cutoff (fC) = 2.5MHz Differential Common Mode 1.6 5 kΩ kΩ Integrated Noise 6603fa 3 LTC6603 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted. PARAMETER CONDITIONS VOS Differential Input Referred Differential Offset Voltage at Either Output Lowest Cutoff Frequency, Gain Setting = 24dB Highest Cutoff Frequency, Gain Setting = 24dB Lowest Cutoff Frequency, Gain Setting = 0dB Highest Cutoff Frequency, Gain Setting = 0dB l l l l fC = 625kHz Common Mode Input from 0V to 3V, V+IN = 3V Common Mode Input from 0V to 5V, V+IN = 5V l l 60 60 90 90 VOCM Pin Voltage V+A = V+D = 3V, Pin 3 Open, fC = 156.25kHz l 1.3 1.45 1.5 V VOCM Pin Input Impedance V+A = V+D = 3V, Pin 3 Open, fC = 156.25kHz l 2.5 3.4 4.5 kΩ VOSCM Common Mode Offset Voltage, VOCM = 1.5V, Supplies = 3V VOSCM = VOUT-CM – VOCM l 100 185 mV Output Swing fC = 156.25kHz Source 1mA, Relative to V+A Sink 1mA, Relative to GND l l 200 150 500 400 mV mV fC = 156.25kHz Sourcing Sinking l l Internal Clock (RBIAS = 30.9k); Sum of the Currents into V+D, V+A, and V+IN All Supplies Set to 3V fC = 156.25kHz fC = 625kHz fC = 2.5MHz l l l 88 121 162 96 130 175 mA mA mA Supply Current, Shutdown Mode Sum of the Currents into V+D, V+A, and V+IN; All Supplies Set to 3V Shutdown Via Serial Interface l 170 235 μA Supply Voltage V+D, V+A Relative to GND V+IN Relative to GND l l 2.7 2.7 3.6 5.5 V V PSRR V+D = V+A = V+IN, All from 2.7V to 3.6V V+D = V+A = 3V, V+IN from 4.5V to 5.5V l l 40 65 l l 30.9 54.9 CMRR Differential Short-Circuit Current Supply Current RBIAS Resistor Range CLKCNTL = 3V Clock Frequency Error < ±3.5% Clock Frequency Error < ±3% RBIAS Pin Voltage MIN 7 11 30.9k < RBIAS < 200k UNITS ±8 ±14 ±40 ±60 mV mV mV mV dB dB 25 30 mA mA 50 85 dB dB 54.9 200 l Output Clock Duty Cycle l 45 CLKIO Pin High Level CLKCNTL = 0V (Note 5) Input Voltage l V+D – 0.3 CLKIO Pin Low Level Input Voltage CLKCNTL = 0V (Note 5) l CLKIO Pin Input Current CLKCNTL = 0V CLKIO = 0V (Note 6) CLKIO = V+D l l kΩ kΩ V 40 Clock Frequency Drift V+A, V+D from 2.7V to 3.6V, RBIAS = 30.9k Over Supply CLKCNTL Pin Open CLKIO Pin High Level V+A = V+D = 3V, CLKCNTL = 3V Output Voltage IOH = –1mA IOH = –4mA MAX 1.17 Clock Frequency Drift RBIAS = 30.9k CLKCNTL Pin Open Over Temperature RBIAS = 30.9k TYP ppm/ºC 0.2 0.5 %/V 50 55 % V 0.3 V 10 μA μA –1 2.95 2.9 V V 6603fa 4 LTC6603 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+A = V+D = V+IN = 3V, VICM = VOCM = 1.5V, Gain = 0dB, lowpass cutoff = 2.5MHz, internal clocking with RBIAS = 30.9k unless otherwise noted. PARAMETER CONDITIONS MIN CLKIO Pin Low Level Output Voltage V+A = V+D = 3V, CLKCNTL = 3V IOL = 1mA IOL = 4mA 0.05 0.1 V V CLKIO Pin Rise Time V+A = V+D = CLKCNTL = 3V, CLOAD = 5pF 0.3 ns CLKIO Pin Fall Time V+A = V+D = CLKCNTL = 3V, CLOAD = 5pF 0.3 ns SER High Level Input Voltage Pin 17 l SER Low Level Input Voltage Pin 17 l SER Input Current Pin 17 = 0V (Note 6) Pin 17 = V+D l l –10 CLKCNTL High Level Input Voltage Pin 5 l V+D – 0.5 CLKCNTL Low Level Input Voltage Pin 5 CLKCNTL Input Current CLKCNTL = 0V (Note 6) CLKCNTL = V+D l l TYP MAX V+D – 0.3 –25 UNITS V 0.3 V 2 μA μA V –15 15 0.5 V 25 μA μA Pin Programmable Control Mode Specifications. Specifications apply to Pins 6, 9, 21 and 22 in pin programmable control mode. SYMBOL PARAMETER CONDITIONS MIN VIH Digital Input High Voltage Pins 6, 9, 21, 22 l VIL Digital Input Low Voltage Pins 6, 9, 21, 22 l IIN Digital Input Current Pins 6, 9, 21, 22 (Note 6) l TYP MAX UNITS V+D = 2.7V to 3.6V 2 V –1 0.8 V 1 μA Serial Port DC and Timing Specifications. Specifications apply to Pins 6, 9-11, and 21 in serial programming mode. SYMBOL PARAMETER CONDITIONS MIN VIH Digital Input High Voltage Pins 6, 9, 10 l VIL Digital Input Low Voltage Pins 6, 9, 10 l –1 VSUPPLY – 0.3 TYP MAX UNITS V+D = 2.7V to 3.6V 2 V 0.8 V 1 μA IIN Digital Input Current Pins 6, 9, 10 (Note 6) l VOH Digital Output High Voltage Pins 11, 21 Sourcing 500μA l VOL Digital Output Low Voltage Pins 11, 21 Sinking 500μA l t1 (Note 5) SDI Valid to SCLK Setup l 60 ns t2 (Note 5) SDI Valid to SCLK Hold l 0 ns V 0.3 V t3 SCLK Low l 100 ns t4 SCLK High l 100 ns t5 CS Pulse Width l 60 ns t6 (Note 5) LSB SCLK to CS l 60 ns t7 (Note 5) CS Low to SCLK l 30 t8 SDO Output Delay t9 (Note 5) SCLK Low to CS Low CL = 15pF l l ns 125 0 ns ns 6603fa 5 LTC6603 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: LTC6603C and LTC6603I are guaranteed functional over the operating temperature range of –40°C to 85°C. Note 3: LTC6603C is guaranteed to meet specified performance from 0°C to 70°C. The LTC6603C is designed, characterized and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LTC6603I is guaranteed to meet the specified performance limits from –40°C to 85°C. Note 4: This test measures the internal oscillator accuracy (deviation from the fCLK equation). Variations in the internal oscillator cause variations in the filter cutoff frequency. See the “Applications Information” section. Note 5: Guaranteed by design, not subject to test. Note 6: To conform to the logic IC standard, current out of a pin is arbitrarily given a negative value. TYPICAL PERFORMANCE CHARACTERISTICS DC Gain Matching DC Gain Matching VS = 3V, BW = 2.5MHz GAIN SETTING = 0dB, TA = 25°C 60 1000 UNITS VS = 3V, BW = 156.25kHz GAIN SETTING = 0dB, TA = 25°C 60 1000 UNITS 50 50 40 30 30 20 40 30 20 20 10 10 5 0 –0.06 –0.04 –0.02 0 0.02 0.04 0.06 0.08 0.1 MISMATCH (dB) 6603 G01 6603 G02 20 800 GAIN = 24dB 760 10 720 GAIN (dB) 0 35 30 20 10 1.5 2 2.5 6603 G04 –10 –20 –30 680 GAIN = 0dB 640 GAIN = 12dB 600 GAIN = 6dB 560 GROUP DELAY –40 520 –50 480 RBIAS = 30.9k, VS = 3V –60 LPF1 = 1, BW = 2.5MHz TA = 25°C –70 10k 100k 1M FREQUENCY (Hz) GROUP DELAY (ns) 40 UNITS (%) 6603 G03 30 VS = 3V, BW = 156.25kHz f = 125kHz, TA = 25°C 1000 UNITS 0 –2.5 –2 –1.5 –1 –0.5 0 0.5 1 MISMATCH (DEG) 0 –2.5 –2–1.5–1–0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 MISMATCH (DEG) Gain and Group Delay vs Frequency Phase Matching 50 15 10 0 –0.2 –0.15 –0.1 –0.05 0 0.05 0.1 0.15 0.2 MISMATCH (dB) 60 VS = 3V, BW = 2.5MHz f = 2MHz, TA = 25°C 1000 UNITS 25 UNITS (%) UNITS (%) UNITS (%) Phase Matching 70 70 440 400 10M 6603 G05 6603fa 6 LTC6603 TYPICAL PERFORMANCE CHARACTERISTICS Gain and Group Delay vs Frequency Gain and Group Delay vs Frequency 10 3.1 10 2.9 0 –10 2.7 –20 2.5 –30 GROUP DELAY 2.3 –40 2.1 RBIAS = 30.9k, VS = 3V –50 LPF1 = 0, LPF0 = 1, –60 BW = 625kHz TA = 25°C –70 10k 100k 1M FREQUENCY (Hz) 11.0 10.5 GAIN = 12dB –10 10.0 GAIN = 6dB GAIN = 0dB –20 9.5 GROUP DELAY –30 9.0 8.5 RBIAS = 30.9k, VS = 3V –50 LPF1 = LPF0 = 0, –60 BW = 156.25kHz TA = 25°C –70 1k 10k 100k FREQUENCY (Hz) 1.7 1.5 10M Distortion vs Input Frequency 7.0 1M –75 HD2, GAIN = 0dB HD2, GAIN = 24dB 700 500 900 INPUT FREQUENCY (kHz) –75 HD3, GAIN = 24dB –80 HD2, GAIN = 24dB HD2, GAIN = 0dB –90 20 120 220 420 320 INPUT FREQUENCY (kHz) 6603 G09 HD3, f = 1MHz HD2, f = 1MHz –80 HD3, f = 200kHz HD2, f = 200kHz –100 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 OUTPUT VOLTAGE (VP-P) 6603 G11 HD3, GAIN = 24dB –80 HD2, GAIN = 24dB –85 HD2, GAIN = 0dB –90 –95 RBIAS = 30.9k, VS = 3V LPF1 = LPF0 = 0, BW = 156.25kHz VOUT = 2VP-P, TA = 25°C –100 50 90 110 130 10 30 70 INPUT FREQUENCY (kHz) 0.2 Filter Cutoff Accuracy vs Temperature LPF1 = LPF0 = 0, BW = 156.25kHz 0.1 0.0 –0.1 –0.2 LPF1 = 0, LPF0 = 1, BW = 625kHz –0.3 –0.4 150 6603 G11 Filter Cutoff Accuracy vs Supply Voltage FILTER CUTOFF FREQUENCY DEVIATION (%) DISTORTION (dBc) 520 HD3, GAIN = 0dB –75 6603 G10 Distortion vs Output Voltage –90 6603 G08 Distortion vs Input Frequency –70 –85 1100 RBIAS = 30.9k, VS = 3V, LPF1 = 0, LPF0 = 1, BW = 2.5MHz, GAIN = 24dB, TA = 25°C 500 900 1300 1700 INPUT FREQUENCY (kHz) –70 HD3, GAIN = 24dB 300 HD2, GAIN = 24dB –90 100 DISTORTION (dBc) –70 –90 100 HD2, GAIN = 0dB 7.5 RBIAS = 30.9k, VS = 3V LPF1 = 0, LPF0 = 1, BW = 625kHz –65 VOUT = 2VP-P, TA = 25°C HD3, GAIN = 0dB DISTORTION (dBc) DISTORTION (dBc) HD3, GAIN = 0dB –85 –70 Distortion vs Input Frequency RBIAS = 54.9k, VS = 3V LPF1 = 1, BW = 1.41MHz TA = 25°C –80 HD3, GAIN = 0dB –80 –60 –65 HD3, GAIN = 24dB 6603 G07 –60 –70 –60 8.0 6603 G06 –60 RBIAS = 30.9k, VS = 3V LPF1 = 1, BW = 2.5MHz VOUT = 2VP-P, TA = 25°C 11.5 GAIN = 24dB –40 1.9 –50 LPF1 = 1, BW = 2.5MHz –0.5 –0.6 –0.7 –0.8 RBIAS = 30.9k TA = 25°C –0.9 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) 6603 G13 FILTER CUTOFF FREQUENCY DEVIATION (%) GAIN (dB) 20 Distortion vs Input Frequency 12.0 GROUP DELAY (μs) GAIN = 0dB 3.3 GROUP DELAY (ns) 0 30 DISTORTION (dBc) GAIN = 12dB GAIN = 6dB GAIN = 24dB 20 3.5 GAIN (dB) 30 1.0 VS = 3V 0.8 RBIAS = 30.9k 0.6 0.4 0.2 BW = 156.25kHz BW = 625kHz 0.0 –0.2 –0.4 BW = 2.5MHz –0.6 –0.8 –50 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 6603 G14 6603fa 7 LTC6603 TYPICAL PERFORMANCE CHARACTERISTICS Common Mode Rejection Ratio Common Mode Rejection Ratio 110 GAIN = 0dB 90 80 50 VS = 3V, RBIAS = 30.9k 30 LPF1 = 1, BW = 2.5MHz TA = 25°C 20 10k 100k 1M FREQUENCY (Hz) GAIN = 12dB 60 40 90 GAIN = 0dB 70 40 50 20 10k 100k 1M FREQUENCY (Hz) COMMON MODE REJECTION (dB) 10M 80 GAIN = 6dB 70 GAIN = 12dB 60 GAIN = 24dB 50 100 70 VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF1 = 1, BW = 625kHz, TA = 25°C GAIN = 0dB GAIN = 6dB GAIN = 12dB GAIN = 24dB 60 CMR = ΔVIN-CM/ΔVOUT-DIFF 50 10k 100k 1M FREQUENCY (Hz) 10M 6603 G18 80 GAIN = 24dB GAIN = 0dB 70 60 50 10M GAIN = 6dB CMR = ΔVIN-CM/ΔVOUT-DIFF VS = 3V, RBIAS = 30.9k LPF1 = LPF0 = 0, BW = 156.25kHz, TA = 25°C 1k 10k 100k FREQUENCY (Hz) 1M 6603 G20 OIP3 vs Average Signal Frequency 46 43 GAIN = 12dB GAIN = 6dB GAIN = 0dB 42 40 44 GAIN = 12dB GAIN = 0dB 41 39 GAIN = 12dB GAIN = 6dB OIP3 (dBm) OIP3 (dBm) 90 OIP3 vs Average Signal Frequency 41 GAIN = 24dB 37 36 GAIN = 12dB 6603 G19 OIP3 vs Average Signal Frequency 38 Common Mode Rejection 100 90 80 1M 6603 G17 42 GAIN = 24dB 40 GAIN = 0dB VS = 3V, RBIAS = 30.9k, TA = 25°C 35 LPF1 = 0, LPF0 = 1, BW = 625kHz VOUT = 6dBm PER TONE FOR 2-TONE TEST Δf = 10kHz 34 100 500 900 1300 1700 2100 2500 AVERAGE FREQUENCY OF TWO TONES (kHz) 6603 G21 38 VS = 3V, RBIAS = 30.9k, TA = 25°C LPF1 = 0, LPF0 = 1, BW = 625kHz VOUT = 6dBm PER TONE FOR 2-TONE TEST Δf = 10kHz 36 0 100 200 300 400 500 600 AVERAGE FREQUENCY OF TWO TONES (kHz) 6603 G22 OIP3 (dBm) COMMON MODE REJECTION (dB) 110 CMR = ΔVIN-CM/ΔVOUT-DIFF 40 VS = 3V, RBIAS = 30.9k LPF1 = 1, BW = 2.5MHz, TA = 25°C 30 10k 100k 1M FREQUENCY (Hz) VS = 3V, RBIAS = 30.9k 40 LPF1 = LPF0 = 0, BW = 156.25kHz, TA = 25°C 30 1k 10k 100k FREQUENCY (Hz) Common Mode Rejection GAIN = 0dB GAIN = 6dB 6603 G16 Common Mode Rejection 90 GAIN = 0dB 70 60 6603 G15 100 80 50 30 10M GAIN = 12dB 100 GAIN = 24dB CMRR (dB) 60 GAIN = 24dB 110 80 GAIN = 6dB GAIN = 12dB GAIN = 24dB CMRR (dB) CMRR (dB) 70 VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF0 = 1, BW = 625kHz, TA = 25°C 100 GAIN = 6dB 90 Common Mode Rejection Ratio 120 COMMON MODE REJECTION (dB) 100 40 39 GAIN = 6dB GAIN = 24dB 38 37 36 35 VS = 3V, RBIAS = 30.9k, TA = 25°C LPF1 = 0, LPF0 = 1, BW = 156.25kHz VOUT = 6dBm PER TONE FOR 2-TONE TEST Δf = 10kHz 20 40 60 80 100 120 140 160 AVERAGE FREQUENCY OF TWO TONES (kHz) 6603 G23 6603fa 8 LTC6603 TYPICAL PERFORMANCE CHARACTERISTICS Output Impedance vs Frequency 41 39 BW = 625kHz, FREQUENCY = 200kHz 38 BW = 156.25kHz, FREQUENCY = 60kHz 37 36 VS = 3V, RBIAS = 30.9k, TA = 25°C 180 LPF1 = 0, LPF0 = 1, BW = 625kHz 1 LPF1 = LPF0 = 0, BW = 156.25kHz 0.1 LPF1 = 1, BW = 2.5MHz 0.01 0.001 –30 –10 10 30 50 TEMPERATURE (°C) 70 90 1k 10k 100k 1M FREQUENCY (Hz) TA = 25°C RBIAS = 30.9k BW = 625kHz 100 BW = 156.25kHz –10 10 30 50 TEMPERATURE (°C) 70 2 1 –2 –14 –12 –10 90 –2 0 2 VOLTAGE NOISE DENSITY (nV/√Hz) GAIN = 12dB GAIN = 24dB 1 VS = 3V, RBIAS = 30.9k LPF1 = 1, BW = 2.5MHz TA = 25°C 10M 6603 G30 0 5 10 15 IRBIAS (μA) 20 25 6603 G29 Input Referred Noise Density GAIN = 0dB GAIN = 6dB 100k 1M FREQUENCY (Hz) 1.15 1.10 –8 –6 –4 TIME (ns) Input Referred Noise Density 1000 1000 0.1 10k 1.20 6603 G28 Input Referred Noise Density 10 TA = 25°C VS = 3V –1 1000 VOLTAGE NOISE DENSITY (nV/√Hz) 6603 G26 RBIAS = 30.9k, VS = 3V TA = 25°C 6603 G27 100 BW = 156.25kHz RBIAS Pin Voltage vs IRBIAS 0 –30 100 1.25 3 140 VOLTAGE (V) SUPPLY CURRENT (mA) 4 BW = 2.5MHz 60 –50 BW = 625kHz 120 60 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) 10M RBIAS PIN VOLTAGE (V) 5 80 140 Clock Output Operating at 80MHz Supply Current vs Temperature 120 BW = 2.5MHz 160 6603 G25 6603 G23 160 TA = 25°C RBIAS = 30.9k 80 BW = 2.5MHz, FREQUENCY = 1MHz 35 –50 180 Supply Current vs Supply Voltage 200 VOLTAGE NOISE DENSITY (nV/√Hz) OIP3 (dBm) 40 OUTPUT IMPEDANCE (Ω) VS = 3V, RBIAS = 30.9k PASSBAND GAIN = 24dB VOUT = 6dBm PER TONE FOR 2-TONE TEST Δf = 10kHz 10 SUPPLY CURRENT (mA) OIP3 vs Temperature 42 GAIN = 0dB GAIN = 6dB 100 GAIN = 12dB GAIN = 24dB 10 VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF0 = 1, BW = 625kHz TA = 25°C 1 10k 100k 1M FREQUENCY (Hz) GAIN = 0dB GAIN = 6dB 100 GAIN = 24dB 10 1 10M 6603 G31 GAIN = 12dB VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF0 = 0, BW = 156.25kHz TA = 25°C 1k 10k 100k FREQUENCY (Hz) 1M 6603 G32 6603fa 9 LTC6603 TYPICAL PERFORMANCE CHARACTERISTICS Integral Input Referred Noise VS = 3V, RBIAS = 30.9k LPF1 = 1,BW = 2.5MHz TA = 25°C GAIN = 6dB 100 VOLTAGE NOISE (μV) VOLTAGE NOISE (μV) 1000 GAIN = 0dB 10 GAIN = 12dB Integral Input Referred Noise 1000 VS = 3V, RBIAS = 30.9k LPF1 = 0, LPF0 = 1, BW = 625kHz TA = 25°C GAIN = 0dB GAIN = 6dB 100 GAIN = 12dB GAIN = 24dB 10 VOLTAGE NOISE (μV) Integral Input Referred Noise 1000 VS = 3V, RBIAS = 30.9k LPF1 = LPF0 = 0, BW = 156.25kHz TA = 25°C GAIN = 0dB 100 GAIN = 6dB GAIN = 12dB GAIN = 24dB 10 GAIN = 24dB 1 10k 100k 1M INTEGRATION BW (Hz) 10M 1 10k 100k 1M INTEGRATION BW (Hz) 6603 G33 10M 6603 G34 1 10k 100k INTEGRATION BW (Hz) 1M 6603 G35 PIN FUNCTIONS V+IN (Pin 1): Input Voltage Supply (2.7V ≤ V ≤ 5.5V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1μF capacitor unless it is tied to V+A (Pin 2). The bypass should be as close as possible to the IC, but is not as critical as the bypassing of V+A and V+D (Pin16). V+A (Pin 2): Analog Voltage Supply (2.7V ≤ V ≤ 3.6V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1μF capacitor. The bypass should be as close as possible to the IC. VOCM (Pin 3): Output Common Mode Voltage Reference. If floated, an internal resistive divider sets the voltage on this pin to half the supply voltage (typically 1.5V), maximizing the dynamic range of the filter. If this pin is floated, it must be bypassed with a quality 1μF capacitor to ground. This pin has a typical input impedance of 3.4k and may be overdriven. Driving this pin to a voltage other than the default value will reduce the signal range the filter can handle before clipping. RBIAS (Pin 4): Oscillator Frequency-Setting Resistor Input. The value of the resistor connected between this pin and ground determines the frequency of the master oscillator, and sets the bias currents for the filter networks. The voltage on this pin is held by the LTC6603 to approximately 1.17V. For best performance, use a precision metal film resistor with a value between 30.9k and 200k and limit the capacitance on this pin to less than 10pF. This resistor is necessary even if an external clock is used. CLKCNTL (Pin 5): Clock Control Input. This three-state input selects the function of CLKIO (Pin 15). Tying the CLKCNTL pin to ground allows the CLKIO pin to be driven by an external clock (CLKIO is the master clock input). If the CLKCNTL pin is floated, the internal oscillator is enabled, but the master clock is not present at the CLKIO pin (CLKIO is a no-connect). If the CLKCNTL pin is tied to V+D (Pin 16), the internal oscillator is enabled and the master clock is present at the CLKIO pin (CLKIO is the master clock output). To detect a floating CLKCNTL pin, the LTC6603 attempts to pull the pin toward mid-supply. This is realized with two internal 15μA current sources, one tied to V+D and CLKCNTL and the other one tied to ground and CLKCNTL. Therefore, driving the CLKCNTL pin high requires sourcing approximately 15μA. Likewise, driving the CLKCNTL pin low requires sinking 15μA. When the CLKCNTL pin is floated, it should be bypassed by a 1nF capacitor to ground or be surrounded by a ground shield to prevent excessive coupling from other PCB traces. 6603fa 10 LTC6603 PIN FUNCTIONS LPF1(CS) (Pin 6): TTL Level Input. When in pin programmable control mode, this pin is the MSB of the lowpass cutoff frequency control code; in serial control mode, this pin is the chip select input (active low). +INB, –INB (Pins 7, 8): Channel B Differential Inputs. The input range and input resistance are described in the Applications Information section. Input voltages which exceed V+IN (Pin 1) should be avoided. LPF0 (SCLK) (Pin 9): TTL Level Input. When in pin programmable control mode, this pin is the LSB of the lowpass cutoff frequency control code; in serial control mode, this pin is the clock of the serial interface. SDI (Pin 10): TTL Level Input. When in pin programmable control mode, this pin is left floating; in serial control mode, this pin is the serial data input. SDO (Pin 11): TTL Level Input. When in pin programmable control mode, this pin is left floating; in serial control mode, this pin is the serial data output. –OUTB, +OUTB (Pins 12, 13): Channel B Differential Filter Outputs. These pins can drive 1k and/or 50pF loads. For larger capacitive loads, an external 100Ω series resistor is recommended for each output. The common mode voltage of the filter outputs is the same as the voltage at VOCM (Pin 3). GND (Pin 14): Ground. Should be tied to a ground plane for best performance. CLKIO (Pin 15): When CLKCNTL (Pin 5) is tied to ground, CLKIO is the master clock input. When CLKCNTL is floated, CLKIO is pulled to ground by a weak pulldown. When CLKCNTL is tied to V+D (Pin 16), CLKIO is the master clock output. When configured as a clock output, this pin can drive 1k and/or 5pF loads (heavier loads will cause inaccuracies). V+D (Pin 16): Digital Voltage Supply (2.7V ≤ V ≤ 3.6V). This supply must be kept free from noise and ripple. It should be bypassed directly to a ground plane with a 0.1μF capacitor. The bypass should be as close as possible to the IC. SER (Pin 17): Interface Selection Input. When tied to V+D (Pin 16) or floated, the interface is in pin programmable control mode, i.e. the filter gain and cutoff frequencies are programmed by the GAIN1, GAIN0, LPF1 and LPF0 pins. When SER is tied to ground, the filter gain, the filter cutoff frequency and shutdown mode are programmed by the serial interface. –OUTA, +OUTA (Pins 18, 19): Channel A Differential Filter Outputs. These pins can drive 1k and/or 50pF loads. For larger capacitive loads, an external 100Ω series resistor is recommended for each output. The common mode voltage of the filter outputs is the same as the voltage at VOCM (Pin 3). CAP (Pin 20): Connect a 0.1μF bypass capacitor to this pin. Pin 20 is a buffered version of Pin 3. GAIN0(D0) (Pin 21): TTL Level Input. When in pin programmable control mode, this pin is the LSB of the gain control code; in serial control mode, this pin is the LSB of the serial control register, an output. GAIN1 (Pin 22): TTL Level Input. When in pin programmable control mode, this pin is the MSB of the gain control code; in serial control mode, this pin is a no-connect. –INA, +INA (Pins 23, 24): Channel A Differential Inputs. The input range and input resistance are described in the Applications Information section. Input voltages which exceed V+IN (Pin 1) should be avoided. Exposed Pad (Pin 25): Ground. The Exposed Pad must be soldered to PCB. 6603fa 11 LTC6603 BLOCK DIAGRAM +INA –INA GAIN1 GAIN0(D0) CAP +OUTA 24 23 22 21 20 19 V+IN 1 18 –OUTA CHANNEL A GAIN LPF 17 SER V+A 2 CONTROL BIAS CLK V+A TO PIN 20 VOCM 3 16 V+D CONTROL LOGIC BIAS/OSC GND CLOCK GENERATOR RBIAS 4 15 CLKIO BIAS CLKCNTL 5 CONTROL GAIN CLK 14 GND LPF CHANNEL B LPF1(CS) 6 13 +OUTB 7 8 9 10 11 12 +INB –INB LPF0(SCLK) SDI SDO –OUTB 6603 BD TIMING DIAGRAM Timing Diagram of the Serial Interface t4 t1 t2 t6 t3 t7 SCLK t9 D3 SDI D2 D1 D0 D7 • • • • D4 D3 t5 CS t8 SDO D4 PREVIOUS BYTE D3 D2 D1 D0 D7 • • • • D4 CURRENT BYTE D3 6603 TD 6603fa 12 LTC6603 APPLICATIONS INFORMATION Theory of Operation (Refer to Block Diagram) pull-up to V+D. None of the logic inputs have an internal pull-up or pull-down. The LTC6603 features two matched filter channels, each containing gain control and lowpass filter networks that are controlled by a single control block and clocked by a single clock generator. The gain and cutoff frequency can be separately programmed. The two channels are not independent, i.e. if the gain is set to 24dB then both channels have a gain of 24dB. The filter can be clocked with an external clock source, or using the internal oscillator. A resistor connected to the RBIAS pin sets the bias currents for the filter networks and the internal oscillator frequency (unless driven by an external clock). Altering the clock frequency changes the filter bandwidth. This allows the filters to be “tuned” to many different bandwidths. Serial Interface Connecting SER to ground allows the filter to be controlled through the SPI serial interface. When CS is low, the serial data on SDI is shifted into an 8-bit shift register on the rising edge of the clock (SCLK), with the MSB transferred first (see Figure 3). Serial data on SDO is shifted out on the clock’s falling edge. A high CS will load the 8 bits of the shift register into an 8-bit D-latch, which is the serial control register. The clock is disabled internally when CS is pulled high. Note: SCLK must be low before CS is pulled low to avoid an extra internal clock pulse. SDO is always active in serial mode (never tri-stated) and cannot be “wire-ORed” to other SPI outputs. In addition, SDO is not forced to zero when CS is pulled high. Pin Programmable Interface As shown in Figure 1, connecting SER to V+D allows the filter to be directly controlled through the pin programmable control lines GAIN1, GAIN0, LPF1 and LPF0. The GAIN0(D0) pin is bidirectional (input in pin programmable control mode, output in serial mode). In pin programmable control mode, the voltage at GAIN0(D0) cannot exceed V+D; otherwise, large currents can be injected to V+D through the parasitic diodes (see Figure 2). Connecting a 10k resistor at the GAIN0(D0) pin (see Figure 1) is recommended for current limiting, to less than 10mA. SER has an internal An LTC6603 may be daisy-chained with other LTC6603s or other devices having serial interfaces. Daisy chaining is accomplished by connecting the SDO of the lead chip to the SDI of the next chip, while SCLK and CS remain common to all chips in the daisy chain. The serial data is clocked to all the chips then the CS signal is pulled high to update all of them simultaneously. Figure 4 shows an example of two LTC6603s in a daisychained SPI configuration. 3.3V 3.3V LTC6603 0.1μF + V+IN V+A V+A V+D V+D +INA +OUTA –INA –OUTA + + VOUT VIN – LTC6603 0.1μF V+IN +INA +OUTA –INA –OUTA – + VOUT VIN – SER – SER LPF1 LPF1(CS) LPF1(CS) LPF0 LPF0(SCLK) LPF0(SCLK) μP GAIN1 GAIN0(D0) GND LOWPASS CUTOFF = 2.5MHz (fCLK = 80MHz) GAIN = 4 GAIN1 GAIN1 GAIN0 10k GAIN0(D0) GND GAIN, BANDWIDTHS ARE SET BY MICROPROCESSOR. 10k RESISTORS ON GAIN0(OUT) PROTECTS THE DEVICE WHEN VGAIN0 > V+D 6603 F01 Figure 1. Filter in Pin Programmable Control Mode 6603fa 13 LTC6603 APPLICATIONS INFORMATION SHUTDOWN NO 4-BIT GAIN, BW FUNCTION CONTROL CODE OUT V+D CS GAIN0(D0) (INTERNAL NODE) 8-BIT LATCH Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8-BIT SHIFT-REGISTER SDI SDO SCLK 6603 F02 6603 F03 Figure 2. Bidirectional Design of GAIN0(OUT) Pin Figure 3. Diagram of Serial Interface (MSB First Out) 3.3V 3.3V 0.1μF V+IN + LTC6603 #1 0.1μF V+A V+A V+D V+D SCLK +OUTA + –INA –OUTA – SER SER LPF1(CS) LPF1(CS) LPF0(SCLK) SDI +INA VOUT2 – – –OUTA –INA LTC6603 #2 VIN2 VOUT1 CSX μP + + +OUTA +INA VIN1 – V+IN GAIN0(D0) OUT1 LPF0(SCLK) SDO SDI GAIN0(D0) SDO SDO SDI GND OUT2 GND SCLK SDI D15 D11 D10 D9 D8 GAIN, BW CONTROL WORD FOR #2 SHUTDOWN FOR #2 D7 D3 D2 D1 D0 GAIN, BW CONTROL WORD FOR #1 SHUTDOWN FOR #1 CS 6603 F04 Figure 4. Two Devices in a Daisy Chain Serial Control Register Definition D7 D6 D5 D4 GAIN0 GAIN1 LPF0 LPF1 D3 D2 NO FUNCTION NO FUNCTION D1 D0 SHDN OUT 6603fa 14 LTC6603 APPLICATIONS INFORMATION GAIN1 and GAIN0 are the gain control bits (register bits D6 and D7 when in serial mode). Their function is shown in Table 1. In serial mode, register bit D1 can be set to 1 to put the device into a low power shutdown mode. Register bit D0 is a general purpose output (Pin 21) when in serial mode. Table 1. Gain Control GAIN 1 GAIN 0 PASSBAND GAIN (dB) 0 0 0 0 1 6 1 0 12 1 1 24 Self-Clocking Operation The LTC6603 features a unique internal oscillator which sets the filter cutoff frequency using a single external resistor connected to the RBIAS pin. The clock frequency is determined by the following simple formula (see Figure 5): fCLK = 247.2MHz • 10k/RBIAS be accurately varied from 24.14kHz to 2.5MHz. Table 2 summarizes the cutoff frequencies that can be obtained with an external resistor (RBIAS) value of 30.9k. Note that the cutoff frequencies scale with the clock frequency. For example, if LPF1 and LPF0 are both equal to zero, and RBIAS is increased from 30.9k to 200k, fCLK will decrease from 80MHz to 12.36MHz and the cutoff frequency will be reduced from 156.25kHz to 24.14kHz. The cutoff frequencies that can be obtained with external resistor values of 54.9k and 200k are shown in Table 3 and Table 4, respectively. When the LTC6603 is programmed for the cutoff frequencies lower than the maximum, the power is automatically reduced. The power savings at the middle bandwidth setting (LPF1 = 0, LPF0 = 1), is about 23%, while the power savings at the lowest bandwidth setting (LPF1 = 0, LPF0 = 0) is about 60%. Table 2. Cutoff Frequency Control, RBIAS = 30.9k, fCLK = 80MHz LPF1 LPF0 LOWPASS BW(kHz) 0 0 156.25 0 1 625 1 0 2500 1 1 2500 Note: RBIAS ≤ 200k The design is optimized for V+A, V+D = 3V, fCLK = 45MHz, where the filter cutoff frequency error is typically