LTC2942CDCB

LTC2942 Battery Gas Gauge with Temperature, Voltage Measurement FEATURES n n n n n n n n n n n n DESCRIPTION The LTC®2942 measures battery charge state, battery voltage and chip temperature in handheld PC and portable product applications. Its operating range is perfectly suited for single cell Li-Ion batteries. A precision coulomb counter integrates current through a sense resistor between the battery’s positive terminal and the load or charger. Battery voltage and on-chip temperature are measured with an internal 14-bit No Latency ΔΣ™ ADC. The three measured quantities (charge, voltage and temperature) are stored in internal registers accessible via the onboard SMBus/I2C interface. The LTC2942 features programmable high and low thresholds for all three measured quantities. If a programmed threshold is exceeded, the device communicates an alert using either the SMBus alert protocol or by setting a flag in the internal status register. The LTC2942 requires only a single low value sense resistor to set the measured current range. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. No Latency ΔΣ is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Indicates Accumulated Battery Charge and Discharge High Accuracy Analog Integration ADC Measures Battery Voltage and Temperature Integrated Temperature Sensor High Side Sense 1% Voltage and Charge Accuracy ±50mV Sense Voltage Range SMBus/I2C Interface Configurable Alert Output/Charge Complete Input 2.7V to 5.5V Operating Range Quiescent Current Less than 100μA Small 6-Pin 2mm × 3mm DFN package APPLICATIONS n n n n n Low Power Handheld Products Cellular Phones MP3 Players Cameras GPS TYPICAL APPLICATION Total Charge Error vs Differential Sense Voltage 2.0 1.5 CHARGER SENSE+ I2C/SMBus TO HOST LTC2942 AL/CC SDA SENSE– SCL GND RSENSE 100mΩ CHARGE ERROR (%) LOAD 0.1μF 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0.1 1 VSENSE (mV) 2942 TA01b VSENSE+ = 3.6V + 1-CELL Li-Ion 2942 TA01a 10 100 2942f 1 LTC2942 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION TOP VIEW SENSE+ 1 GND 2 SCL 3 7 GND 6 SENSE– 5 AL/CC 4 SDA Supply Voltage (SENSE+) ............................. –0.3V to 6V SCL, SDA, AL/CC ......................................... –0.3V to 6V SENSE– .................................. –0.3V to (VSENSE+ + 0.3V) Operating Ambient Temperature Range LTC2942C ................................................ 0°C to 70°C LTC2942I.............................................. –40°C to 85°C Storage Temperature Range................... –65°C to 150°C DCB PACKAGE 6-LEAD (2mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 120°C/W EXPOSED PAD (PIN 7) IS GND, MUST BE SOLDERED TO PCB OR LEFT FLOATING ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) LTC2942CDCB#TRMPBF TAPE AND REEL LTC2942CDCB#TRPBF PART MARKING* LDVN PACKAGE DESCRIPTION 6-Lead (2mm × 3mm) Plastic DFN TEMPERATURE RANGE 0°C to 70°C –40°C to 85°C LTC2942IDCB#TRMPBF LTC2942IDCB#TRPBF LDVN 6-Lead (2mm × 3mm) Plastic DFN TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS SYMBOL VSENSE+ ISUPPLY PARAMETER Supply Voltage Supply Current (Note 3) CONDITIONS Power Requirements The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) MIN 2.7 Battery Gas Gauge On, ADC Sleep Battery Gas Gauge On, ADC Converting Voltage Shutdown Shutdown, VSENSE+ ≤ 4.2V l l l l l TYP MAX 5.5 UNITS V μA μA μA μA μA V mV kΩ 70 300 350 100 350 420 2.5 1 Battery Gas Gauge On, ADC Converting Temperature l VUVLO VSENSE RIDR Undervoltage Lockout Threshold Sense Voltage Differential Input Range Differential Input Resistance, Across SENSE+ and SENSE– (Note 8) Charge LSB (Note 4) Total Charge Error (Note 5) VSENSE+ Falling VSENSE+ – VSENSE– 2.5 2.6 2.7 ±50 Coulomb Counter 400 qLSB TCE Prescaler M = 128 (Default), RSENSE = 50mΩ 10mV ≤ |VSENSE| ≤ 50mV DC 10mV ≤ |VSENSE| ≤ 50mV DC, VSENSE + ≤ 4.2V 1mV ≤ |VSENSE| < 50mV DC (Note 8) l l 0.085 ±1 ±1.5 ±3.5 mAh % % % 2942f 2 LTC2942 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER Resolution (No Missing Codes) VFS ΔVLSB TUEV Gain VOS INL tCONV Full-Scale Voltage Quantization Step of 14-Bit Voltage ADC Voltage Total Unadjusted Error Gain Accuracy Offset Integral Nonlinearity Conversion Time Resolution (No Missing Code) TFS ΔTLSB TUET tCONV VITH VOL IIN CIN tPCC Full-Scale Temperature Quantization Step of 10-Bit Temperature ADC Temperature Total Unadjusted Error Conversion Time Logic Input Threshold, A L /CC, SCL, SDA Low Level Output Voltage, AL/CC, I = 3mA SDA Input Leakage, AL/CC, SCL, SDA Input Capacitance, AL/CC, SCL, SDA Minimum Charge Complete (CC) Pulse Width Maximum SCL Clock Frequency Bus Free Time Between Stop/Start l l l l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) CONDITIONS (Note 8) (Note 6) l l MIN 14 TYP MAX UNITS Bits Voltage Measurement ADC 6 366.2 1 1.3 1.3 ±1 l l V μV % % % LSB LSB ms Bits l l Extrapolated from Measurements at 5.5V and 2.7V ±10 ±4 15 ±1 Temperature Measurement ADC (Note 8) l 10 600 0.586 l l l l l l K K ±5 ±3 15 K K ms V V μA pF μs (Note 6) VSENSE+ ≥ 2.8V (Note 8) Digital Inputs and Digital Outputs 0.3 • VSENSE+ 0.7 • VSENSE+ 0.4 1 10 1 VIN = VSENSE+/2 (Note 8) I2C Timing Characteristics fSCL(MAX) tBUF(MIN) 400 900 1.3 600 600 600 100 kHz μs ns ns ns ns tSU,STA(MIN) Minimum Repeated Start Set-Up Time tHD,STA(MIN) Minimum Hold Time (Repeated) Start Condition tSU,STO(MIN) Minimum Set-Up Time for Stop Condition tSU,DAT(MIN) Minimum Data Setup Time Input 2942f 3 LTC2942 ELECTRICAL CHARACTERISTICS SYMBOL tHD,DATO tof PARAMETER Data Hold Time Output Data Output Fall Time (Notes 7, 8) CONDITIONS l l l The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 2) MIN 0.3 20 + 0.1 • CB TYP MAX 0 0.9 300 UNITS μs μs ns tHD,DATI(MIN) Minimum Data Hold Time Input Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specified Note 3: ISUPPLY = ISENSE+ + ISENSE– Note 4: The equivalent charge of an LSB in the accumulated charge register depends on the value of RSENSE and the setting of the internal prescaling factor M: qLSB = 0.085mAh • 50mΩ M • RSENSE 128 Note 5: Deviation of qLSB from its nominal value. Note 6: The quantization step of the 14-bit ADC in voltage mode and 10-bit ADC in temperature mode is not to be mistaken with the LSB of the combined 16-bit voltage registers (I, J) and 16-bit temperature registers (M, N). Note 7: CB = Capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF). See Voltage and Temperature Registers section for more information. Note 8: Guaranteed by design, not subject to test. See Choosing RSENSE and Choosing Coulomb Counter Prescaler M section for more information. 1mAh = 3.6C (Coulombs). TIMING DIAGRAM tof SDA tSU, DAT tHD, DATO, tHD, DATI tSU, STA tHD, STA tBUF tSU, STO 2942 F01 SCL tHD, STA START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 1. Definition of Timing on I2C Bus 2942f 4 LTC2942 TYPICAL PERFORMANCE CHARACTERISTICS Total Charge Error vs Differential Sense Voltage 3 2 CHARGE ERROR (%) 1 0 –1 –2 –3 0.1 VSENSE+ = 2.7V VSENSE+ = 4.2V 1 VSENSE (mV) 2942 G01 Total Charge Error vs Supply Voltage 1.00 0.75 CHARGE ERROR (%) CHARGE ERROR (%) 0.50 0.25 0 1.00 0.75 0.50 0.25 0 –0.25 –0.50 VSENSE = –50mV VSENSE = –10mV 2.5 3.0 3.5 4.0 4.5 5.0 VSENSE+ (V) 5.5 6.0 –0.75 Total Charge Error vs Temperature –0.25 –0.50 –0.75 –1.00 10 100 –1.00 –50 VSENSE = –50mV VSENSE = –10mV –25 25 0 50 TEMPERATURE (°C) 75 100 2942 G03 2942 G02 Supply Current vs Supply Voltage 100 90 80 70 60 50 40 2.5 0 TA = 25°C TA = –40°C TA = 85°C ISHUTDOWN (μA) 2.0 Shutdown Supply Current vs Supply Voltage 10 8 TOTAL UNADJUSTED ERROR (mV) 1.5 6 4 2 0 –2 –4 –6 –8 –10 Voltage Measurement ADC Total Unadjusted Error TA = 85°C ISUPPLY (μA) 1.0 TA = –45°C 0.5 TA = 25°C TA = –40°C TA = 85°C 3.0 3.5 4.0 4.5 5.0 VSENSE+ (V) 5.5 6.0 2.5 3.0 3.5 4.0 4.5 5.0 VSENSE+ (V) 5.5 6.0 TA = 25°C 2.5 3.0 3.5 4.0 4.5 5.0 VSENSE– (V) 5.5 6.0 2942 G04 2942 G05 2942 G06 Voltage Measurement ADC Integral Nonlinearity 1.0 TA = 85°C 2 0.5 INL (VLSB) TEMPERATURE ERROR (°C) 1 0 –1 –2 –1.0 2.5 3 Temperature Error vs Temperature 0 TA = –40°C –0.5 TA = 25°C 3.0 3.5 4.0 4.5 5.0 VSENSE– (V) 5.5 6.0 –3 –50 –25 0 25 50 TEMPERATURE (°C) 75 100 2942 G08 2942 G07 2942f 5 LTC2942 PIN FUNCTIONS SENSE+ (Pin 1): Positive Current Sense Input and Power Supply. Connect to the load/charger side of the sense resistor. VSENSE+ operating range is 2.7V to 5.5V. GND (Pin 2, Exposed Pad Pin 7): Device Ground. Connect directly to the negative battery terminal. Exposed pad may be left open or connected to device ground. SCL (Pin 3): Serial Bus Clock Input. SDA (Pin 4): Serial Bus Data Input and Output. AL/CC (Pin 5): Alert Output or Charge Complete Input. Configured either as an SMBus alert output or charge complete input by control register bits B[2:1]. At power-up, the pin defaults to alert mode conforming to the SMBus alert response protocol. It behaves as an open-drain logic output that pulls to GND when any threshold register value is exceeded. When configured as a charge complete input, connect to the charge complete output from the battery charger circuit. A high level at CC sets the value of the accumulated charge (registers C, D) to FFFFh. SENSE– (Pin 6): Negative Current Sense Input. Connect SENSE– to the positive battery terminal side of the sense resistor. The voltage between SENSE– and SENSE+ must remain within ±50mV in normal operation. SENSE– is also the input for the ADC in voltage measurement mode. BLOCK DIAGRAM LTC2942 1 SENSE+ VSUPPLY ACCUMULATED CHARGE REGISTER CC COULOMB COUNTER REF CLK AL I2C/ SMBus AL/CC 5 TEMPERATURE SENSOR REFERENCE GENERATOR OSCILLATOR SCL SDA 3 REF+ MUX IN REF– GND ADC CLK DATA AND CONTROL REGISTERS 4 6 SENSE– 2 2942 BD 2942f 6 LTC2942 OPERATION Overview The LTC2942 is a battery gas gauge device designed for use with single Li-Ion cells and other battery types with a terminal voltage at 2.7V to 5.5V. It measures battery charge and discharge, battery voltage and chip temperature. A precision coulomb counter integrates current through a sense resistor between the battery’s positive terminal and the load or charger. Battery voltage and on-chip temperature are measured with an internal 14-bit/10-bit ADC. Coulomb Counter Charge is the time integral of current. The LTC2942 measures battery current by monitoring the voltage developed across a sense resistor and then integrates this information to infer charge. The differential voltage between SENSE+ and SENSE– is applied to an auto-zeroed differential analog integrator to convert the measured current to charge. When the integrator output ramps to REFHI or REFLO levels, switches S1, S2, S3 and S4 toggle to reverse the ramp direction. By observing the condition of the switches and the ramp direction, polarity is determined. A programmable prescaler effectively increases integration time by a factor M programmable from 1 to 128. At each underflow or overflow of the prescaler, the accumulated charge register (ACR) value is incremented or decremented one count. The value of accumulated charge is read via the I2C interface. Voltage and Temperature ADC The LTC2942 includes a 14-bit No Latency ΔΣ analog-todigital converter, with internal clock and voltage reference circuits. The ADC can either be used to monitor the battery voltage at SENSE– or to convert the output of the on-chip temperature sensor. The sensor generates a voltage proportional to temperature with a slope of 2.5mV/K resulting in a voltage of 750mV at 27°C. Conversion of either temperature or voltage is triggered by setting the control register via the I2C interface. The LTC2942 features an automatic mode where a voltage and a temperature conversion are executed every two seconds. At the end of each conversion the corresponding registers are updated and the converter goes to sleep to minimize quiescent current. CHARGER LOAD VCC SENSE+ S1 REFHI + CONTROL LOGIC RSENSE IBAT 6 SENSE– S2 S4 GND REFLO BATTERY + 2 Figure 2. Coulomb Counter Section of the LTC2942 + S3 – 1 – M PRESCALER ACR + POLARITY DETECTION – 2942 F02 2942f 7 LTC2942 OPERATION Power-Up Sequence When SENSE+ rises above a threshold of approximately 2.5V, the LTC2942 generates an internal power-on reset (POR) signal and sets all registers to their default state. In the default state, the coulomb counter is active while the voltage and temperature ADC is switched off. The accumulated charge register is set to mid-scale (7FFFh), all low threshold registers are set to 0000h and all high threshold registers are set to FFFFh. The alert mode is enabled and the coulomb counter pre-scaling factor M is set to 128. APPLICATIONS INFORMATION I2C/SMBus Interface The LTC2942 communicates with a bus master using a 2-wire interface compatible with I2C and SMBus. The 7-bit hard-coded I2C address of the LTC2942 is 1100100. The LTC2942 is a slave-only device. Therefore the serial clock line (SCL) is an input only while the serial data line (SDA) is bidirectional. The device supports I2C standard and fast mode. For more details refer to the I2C Protocol section. Internal Registers The LTC2942 integrates current through a sense resistor, measures battery voltage and temperature and stores the results in internal 16-bit registers accessible via I2C. High and low limits can be programmed for each measurement quantity. The LTC2942 continuously monitors these limits and sets a flag in the onboard status register when a limit is exceeded. If the alert mode is enabled, the AL/CC pin pulls low. The sixteen internal registers are organized as shown in Table 1. Table 1. Register Map ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh NAME REGISTER DESCRIPTION A B C D E F G H I J K L M N O P Status Control Accumulated Charge MSB Accumulated Charge LSB Charge Threshold High MSB Charge Threshold High LSB Charge Threshold Low MSB Charge Threshold Low LSB Voltage MSB Voltage LSB Voltage Threshold High Voltage Threshold Low Temperature MSB Temperature LSB Temperature Threshold High Temperature Threshold Low R/W R R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W DEFAULT See Below 3Ch 7Fh FFh FFh FFh 00h 00h XXh XXh FFh 00h XXh XXh FFh 00h R = Read, W = Write, XX = unknown 2942f 8 LTC2942 APPLICATIONS INFORMATION Status Register (A) The status of the charge, voltage and temperature alerts is reported in the status register shown in Table 2. Table 2. Status Register A (Read only) BIT NAME OPERATION 0: LTC2942 1: LTC2941 DEFAULT 0 0 0 0 The hard-coded bit A[7] of the status register enables the host to distinguish the LTC2942 from the pin compatible LTC2941, allowing the same software to be used with both devices. Control Register (B) The operation of the LTC2942 is controlled by programming the control register. Table 3 shows the organization of the 8-bit control register B[7:0]. Table 3. Control Register B BIT NAME OPERATION [11] Automatic Mode. Performs voltage and temperature conversion every second. [10] Manual Voltage Mode. Performs single voltage conversion, then sleeps. [01] Manual Temperature Mode. Performs single temperature conversion, then sleeps. [00] Sleep. Sets coulomb counter prescaling factor M between 1 and 128. Default is 128. M = 2(4 • B[5] + 2 • B[4] + B[3]) Default [00] B[7:6] ADC Mode A[7] Chip Identification A[6] Reserved A[5] Accumulated Charge Indicates that the value of the Overflow/Underflow ACR hit either top or bottom. A[4] Temperature Alert Indicates one of the temperature limits was exceeded. Indicates that the ACR value exceeded the charge threshold high limit. Indicates that the ACR value dropped below the charge threshold low limit. Indicates one of the battery voltage limits was exceeded. Indicates recovery from undervoltage. If set to 1, a UVLO has occurred and the contents of the registers are uncertain. A[3] Charge Alert High 0 A[2] Charge Alert Low 0 A[1] Voltage Alert A[0] Undervoltage Lockout Alert 0 X B[5:3] Prescaler M [111] All status register bits except A[7] are cleared after being read by the host, if the conditions which set these bits have been removed. As soon as one of the three measured quantities exceeds the programmed limits, the corresponding bit A[4], A[3], A[2] or A[1] in the status register is set. Bit A[5] is set if the LTC2942’s accumulated charge registers (ACR) overflows or underflows. In these cases, the ACR stays at FFFFh or 0000h and does not roll over. The undervoltage lockout (UVLO) bit of the status register A[0] is set if, during operation, the voltage on SENSE+ pin drops below 2.7V without reaching the POR level. The analog parts of the coulomb counter are switched off while the digital register values are retained. After recovery of the supply voltage the coulomb counter resumes integrating with the stored value in the accumulated charge registers but it has missed any charge flowing while SENSE+ < 2.7V. B[2:1] AL/CC Configure Configures the AL/CC pin. [10] Alert Mode. Alert functionality enabled. Pin becomes logic output. [01] Charge Complete Mode. Pin becomes logic input and accepts “charge complete” signal (e.g., from a charger) to set accumulated charge register (C,D) to FFFFh. [00] AL/CC pin disabled. [11] Not allowed. B[0] Shutdown Shut down analog section to reduce ISUPPLY. [10] [0] Power Down B[0] Setting B[0] to 1 shuts down the analog parts of the LTC2942, reducing the current consumption to less than 1μA. All analog circuits are inoperative while the values in the registers are retained. Note that any charge flowing while B[0] is 1 is not measured and the charge information below 1LSB of the accumulated charge register is lost. 2942f 9 LTC2942 APPLICATIONS INFORMATION Alert/Charge Complete Configuration B[2:1] The AL/CC pin is a dual function pin configured by the control register. By setting bits B[2:1] to [10] (default) the AL/CC pin is configured as an alert pin following the SMBus protocol. In this configuration the AL/CC pin is a digital output and is pulled low if one of the three measured quantities (charge, voltage, temperature) exceeds its high or low threshold or if the value of the accumulated charge register overflows or underflows. An alert response procedure started by the master resets the alert at the AL/CC pin. For further information see the Alert Response Protocol section. Setting the control bits B[2:1] to [01] configures the AL/CC pin as a digital input. In this mode, a high input on the AL/CC pin communicates to the LTC2942 that the battery is full and the accumulated charge register is set to its maximum value FFFFh. The AL/CC pin would typically be connected to the “charge complete” output from the battery charger circuitry. If neither the alert nor the charge complete functionality is desired, bits B[2:1] should be set to [00]. The AL/CC pin is then disabled and should be tied to GND. Avoid setting B[2:1] to [11] as it enables the alert and the charge complete modes simultaneously. Choosing RSENSE To achieve the specified precision of the coulomb counter, the differential voltage between SENSE+ and SENSE– must stay within ±50mV. For differential input signals up to ±300mV the LTC2942 will remain functional but the precision of the coulomb counter is not guaranteed. The required value of the external sense resistor, RSENSE, is determined by the maximum input range of VSENSE and the maximum current of the application: RSENSE ≤ 50mV IMAX coulomb counting. Thus the amount of charge represented by the least significant bit (qLSB) of the accumulated charge (registers C, D) is equal to: qLSB = 0.085mAh • or qLSB = 0.085mAh • 50mΩ RSENSE 50mΩ M • RSENSE 128 when the prescaler is set to its default value of M = 128. Note that 1mAh = 3.6C (coulomb). Choosing RSENSE = 50mV/IMAX is not sufficient in applications where the battery capacity (QBAT) is very large compared to the maximum current (IMAX): QBAT > IMAX • 5.5 Hours For such low current applications with a large battery, choosing RSENSE according to RSENSE = 50mV/IMAX can lead to a qLSB smaller than QBAT/216 and the 16-bit accumulated charge register may underflow before the battery is exhausted or overflow during charge. Choose, in this case, a maximum RSENSE of: RSENSE ≤ 0.085mAh • 216 • 50mΩ QBAT In an example application where the maximum current is IMAX = 100mA, calculating RSENSE = 50mV/IMAX would lead to a sense resistor of 500mΩ. This gives a qLSB of 8.5μAh and the accumulated charge register can represent a maximum battery capacity of QBAT = 8.5μAh • 65535 = 557mAh. If the battery capacity is larger, RSENSE must be lowered. For example, RSENSE must be reduced to 150mΩ if a battery with a capacity of 1800mAh is used. Choosing Coulomb Counter Prescaler M B[5:3] If the battery capacity (QBAT) is very small compared to the maximum current (IMAX) (QBAT < IMAX • 0.1 Hours) the prescaler value M should be changed from its default value (128). In these applications with a small battery but a high maximum current, qLSB can get quite large with respect 2942f The choice of the external sense resistor value influences the gain of the coulomb counter. A larger sense resistor gives a larger differential voltage between SENSE+ and SENSE– for the same current which results in more precise 10 LTC2942 APPLICATIONS INFORMATION to the battery capacity. For example, if the battery capacity is 100mAh and the maximum current is 1A, the standard equation leads to choosing a sense resistor value of 50mΩ, resulting in: qLSB = 0.085mAh = 306mC The battery capacity then corresponds to only 1176 qLSBs and less than 2% of the accumulated charge register is utilized. To preserve digital resolution in this case, the LTC2942 includes a programmable prescaler. Lowering the prescaler factor M allows reducing qLSB to better match the accumulated charge register to the capacity of the battery. The prescaling factor M can be chosen between 1 and its default value 128. The charge LSB then becomes: qLSB = 0.085mAh • 50mΩ M • RSENSE 128 The ADC has four different modes of operation as shown in Table 3. These modes are controlled by bits B[7:6] of the control register. At power-up, bits B[7:6] are set to [00] and the ADC is in sleep mode. A single voltage conversion is initiated by setting the bits B[7:6] to [10]. A single temperature conversion is started by setting bits B[7:6] to [01]. After a single voltage or temperature conversion, the ADC resets B[7:6] to [00] and goes to sleep. The LTC2942 also offers an automatic scan mode where the ADC converts voltage, then temperature, then sleeps for approximately two seconds before repeating the voltage and temperature conversions. The LTC2942 is set to this automatic mode by setting B[7:6] to [11] and stays in this mode until B[7:6] are reprogrammed by the host. Programming B[7:6] to [00] puts the ADC to sleep. If control bits B[7:6] change within a conversion, the ADC will complete the current conversion before entering the newly selected mode. A conversion of either voltage or temperature requires 10ms conversion time (typical). At the end of each conversion, the corresponding registers are updated. If the converted quantity exceeds the values programmed in the threshold registers, a flag is set in the status register and the AL/CC pin is pulled low (if alert mode is enabled). During a voltage conversion, the SENSE– pin is connected through a small resistor to a sampling circuit with an equivalent resistance of 2MΩ, leading to a mean input current of I = VSENSE–/2MΩ. Accumulated Charge Register (C,D) The coulomb counter of the LTC2942 integrates current through the sense resistor. The result of this charge integration is stored in the 16-bit accumulated charge register (registers C, D). As the LTC2942 does not know the actual battery status at power-up, the accumulated charge register (ACR) is set to mid-scale (7FFFh). If the host knows the status of the battery, the accumulated charge (C[7:0]D[7:0]) can be either programmed to the correct value via I2C or it can be set after charging to FFFFh (full) by pulling the AL/CC pin high if charge complete mode is enabled via bits B[2:1]. Before writing the accumulated charge regis2942f To use as much of the range of the accumulated charge register as possible the prescaler factor M should be chosen for a given battery capacity QBAT and a sense resistor RSENSE as: M ≥ 128 • RSENSE 216 • 0.085mAh 50mΩ QBAT • M can be set to 1, 2, 4, 8, … 128 by programming B[5:3] of the control register as M = 2(4 • B[5] + 2 • B[4] + B[3]). The default value after power up is M = 128 = 27 (B[5:3] = 111). In the above example of a 100mAh battery and an RSENSE of 50mΩ, the prescaler should be programmed to M = 4. The qLSB then becomes 2.656μAh and the battery capacity corresponds to roughly 37650 qLSBs. Note that the internal digital resolution of the coulomb counter is higher than indicated by qLSB. The digitized charge qINTERNAL is M • 8 times smaller than qLSB. qINTERNAL is typically 299μAs for a 50mΩ sense resistor. ADC Mode B[7:6] The LTC2942 features an ADC which measures either voltage on SENSE– (battery voltage) or temperature via an internal temperature sensor. The reference voltage and clock for the ADC are generated internally. 11 LTC2942 APPLICATIONS INFORMATION ters, the analog section should be shut down by setting B[0] to 1. In order to avoid a change in the accumulated charge registers between reading MSBs C[7:0] and LSBs D[7:0], it is recommended to read them sequentially as shown in Figure 10. Voltage and Temperature Registers (I, J),(M, N) The result of the 14-bit ADC conversion of the voltage at SENSE– is stored in the voltage registers (I, J), whereas the temperature measurement result is stored in the temperature registers (M, N). The voltage and temperature registers are read only. As the ADC resolution is 14-bit in voltage mode and 10-bit in temperature mode, the lowest two bits of the combined voltage registers (I, J) and the lowest six bits of the combined temperature registers (M, N) are always zero. From the result of the 16-bit voltage registers I[7:0]J[7:0] the measured voltage can be calculated as: VSENSE – = 6V • RESULTDEC RESULTh = 6V • FFFFh 65535 sets the corresponding flag in the status register and pulls the AL/CC pin low if alert mode is enabled via bits B[2:1]. Note that the voltage and temperature threshold registers are single byte registers and only the 8 MSBs of the corresponding quantity are checked. To set a low level threshold for the battery voltage of 3V, register L should be programmed to 80h; a high temperature limit of 60°C is programmed by setting register O to 8Eh. I2C Protocol The LTC2942 uses an I2C/SMBus compatible 2-wire opendrain interface supporting multiple devices and masters on a single bus. The connected devices can only pull the bus wires low and they never drive the bus high. The bus wires must be externally connected to a positive supply voltage via a current source or pull-up resistor. When the bus is idle, both SDA and SCL are high. Data on the I2C bus can be transferred at rates of up to 100kbit/s in standard mode and up to 400kbit/s in fast mode. Each device on the I2C/SMbus is recognized by a unique address stored in that device and can operate as either a transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices can also be classified as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At the same time any device addressed is considered a slave. The LTC2942 always acts as a slave. Figure 3 shows an overview of the data transmission for fast and standard mode on the I2C bus. Start and Stop Conditions When the bus is idle, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. When the bus is in use, it stays busy if a repeated START (Sr) is generated instead of a STOP condition. The repeated START (Sr) conditions are functionally identical to the START (S). 2942f Example: a register value of I[7:0] = B0h and J[7:0] = 1Ch corresponds to a voltage on SENSE– of: VSENSE – = 6 V • 45084DEC B01Ch = 6V • ≈ 4.1276V 7 FFFFh 65535 The actual temperature can be obtained from the two byte register C[7:0]D[7:0] by: T = 600K • RESULTDEC RESULTh = 600K • FFFFh 65535 Example: a register value of C[7:0] = 80h D[7:0] = 00h corresponds to 300K or 27°C. Threshold Registers (E, F G, H, K, L, O, P) , For each of the measured quantities (battery charge, voltage and temperature) the LTC2942 features a high and a low threshold registers. At power-up, the high thresholds are set to FFFFh while the low thresholds are set to 0000h. All thresholds can be programmed to a desired value via I2C. As soon as a measured quantity exceeds the high threshold or falls below the low threshold, the LTC2942 12 LTC2942 APPLICATIONS INFORMATION Data Transmission After a START condition, the I2C bus is considered busy and data transfer begins between a master and a slave. As data is transferred over I2C in groups of nine bits (eight data bits followed by an acknowledge bit), each group takes nine SCL cycles. The transmitter releases the SDA line during the acknowledge clock pulse and the receiver issues an acknowledge (ACK) by pulling SDA low or leaves SDA high to indicate a not acknowledge (NAK) condition. Change of data state can only happen while SCL is low. Write Protocol The master begins a write operation with a START condition followed by the seven bit slave address 1100100 and the R/W bit set to zero, as shown in Figure 4. The LTC2942 acknowledges this by pulling SDA low and then the master sends a command byte which indicates which internal register the master is to write. The LTC2942 acknowledges and latches the command byte into its internal register address pointer. The master delivers the data byte, the LTC2942 acknowledges once more and latches the data into the desired register. The transmission is ended when the master sends a STOP condition. If the master continues by sending a second data byte instead of a stop, the LTC2942 acknowledges again, increments its address pointer and latches the second data byte in the following register, as shown in Figure 5. Read Protocol The master begins a read operation with a START condition followed by the seven bit slave address 1100100 and the R/W bit set to zero, as shown in Figure 6. The LTC2942 SDA a6 - a0 b7 - b0 b7 - b0 SCL S 1-7 8 9 1-7 8 9 1-7 8 9 P ADDRESS START CONDITION R/W ACK DATA ACK DATA ACK STOP CONDITION 2942 F03 Figure 3. Data Transfer Over I2C or SMBus S ADDRESS 1100100 W 0 A 0 REGISTER 01h A 0 DATA FCh A 0 2942 F04 P FROM MASTER TO SLAVE FROM SLAVE TO MASTER A: ACKNOWLEDGE (LOW) A: NOT ACKNOWLEDGE (HIGH) S: START CONDITION P: STOP CONDITION R: READ BIT (HIGH) W: WRITE BIT (LOW) Figure 4. Writing FCh to the LTC2942 Control Register (B) S ADDRESS 1100100 W 0 A 0 REGISTER 02h A 0 DATA F0h A 0 DATA 01h A 0 2942 F05 P S ADDRESS 1100100 W 0 A 0 REGISTER 00h A 0 S ADDRESS 1100100 R 1 A 0 DATA 01h A 1 P 2942 F06 Figure 5. Writing F001h to the LTC2942 Accumulated Charge Register (C, D) S ADDRESS 1100100 W 0 A 0 REGISTER 08h A 0 S ADDRESS 1100100 Figure 6. Reading the LTC2942 Status Register (A) R 1 A 0 DATA F1h A 0 DATA 24h A 1 P 2942 F07 Figure 7. Reading the LTC2942 Voltage Register (I, J) 2942f 13 LTC2942 APPLICATIONS INFORMATION acknowledges and then the master sends a command byte which indicates which internal register the master is to read. The LTC2942 acknowledges and then latches the command byte into its internal register address pointer. The master then sends a repeated START condition followed by the same seven bit address with the R/W bit now set to one. The LTC2942 acknowledges and sends the contents of the requested register. The transmission is ended when the master sends a STOP condition. If the master acknowledges the transmitted data byte, the LTC2942 increments its address pointer and sends the contents of the following register as depicted in Figure 7. Alert Response Protocol In a system where several slaves share a common interrupt line, the master can use the alert response address (ARA) to determine which device initiated the interrupt (Figure 8). The master initiates the ARA procedure with a START condition and the special 7-bit ARA bus address (0001100) followed by the read bit (R) = 1. If the LTC2942 is asserting the AL/CC pin in alert mode, it acknowledges and responds by sending its 7-bit bus address (1100100) and a 1. While it is sending its address, it monitors the SDA pin to see if another device is sending an address at the same time using standard I2C bus arbitration. If the LTC2942 is sending a 1 and reads a 0 on the SDA pin on the rising edge of SCL, it assumes another device with a lower address is sending and the LTC2942 immediately aborts its transfer and waits for the next ARA cycle to try again. If transfer is successfully completed, the LTC2942 will stop pulling down the AL/CC pin and will not respond to further ARA requests until a new Alert event occurs. PC Board Layout Suggestions Keep all traces as short as possible to minimize noise and inaccuracy. Use a 4-wire Kelvin sense connection for the sense resistor, locating the LTC2942 close to the resistor with short sense traces to the SENSE+ and SENSE– pins. Use wider traces from the resistor to the battery, load and/or charger (see Figure 11). Put the bypass capacitor close to SENSE+ and GND. TO CHARGER/LOAD 1 C 2 3 LTC2942 RSENSE TO BATTERY 6 5 4 2942 F10 Figure 11. Kelvin Connection on Sense Resistor S ALERT RESPONSE ADDRESS 0001100 R 1 A 0 DEVICE ADDRESS 11001001 A 1 P 2942 F08 Figure 8. LTC2942 Serial Bus SDA Alert Response Protocol S ADDRESS W A REGISTER A DATA P 1100100 0 0 01h 0 BC 10ms S ADDRESS W A REGISTER A S ADDRESS R A DATA A DATA A P 1100100 0 0 08h 0 1100100 1 0 F1h 0 80h 1 2942 F09 Figure 9. Voltage Conversion Sequence S ADDRESS 1100100 W 0 A 0 REGISTER 02h A 0 S ADDRESS 1100100 R 1 A 0 DATA 80h A 0 DATA 01h A 1 P 2942 F10 Figure 10. Reading the LTC2942 Accumulated Charge Registers (C, D) 2942f 14 LTC2942 PACKAGE DESCRIPTION DCB Package 6-Lead Plastic DFN (2mm × 3mm) (Reference LTC DWG # 05-08-1715) 0.70 0.05 3.55 0.05 1.65 0.05 (2 SIDES) PACKAGE OUTLINE 2.15 0.05 0.25 0.50 BSC 1.35 0.05 (2 SIDES) 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 2.00 0.10 (2 SIDES) R = 0.05 TYP R = 0.115 TYP 4 6 0.40 0.10 3.00 0.10 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6) 1.65 0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 45 CHAMFER 3 1 0.25 0.50 BSC 1.35 0.10 (2 SIDES) (DCB6) DFN 0405 0.05 0.200 REF 0.75 0.05 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2942f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC2942 TYPICAL APPLICATION Single Cell Lithium-Ion Coulomb Counter with Battery Charger for Charge and Discharge Currents of up to 500mA 500mA 3.3V 2k 1 VDD μP 2k 2k 1 SENSE+ LTC2942 5 AL/CC 4 6 SDA SENSE– 3 SCL GND 2 2942 TA02 VIN 5V 1μF 4 VCC BAT 3 LOAD 0.1μF LTC4057-4.2 (CHARGER) 5 PROG SHDN GND 2 RSENSE 100mΩ 2k + 1-CELL Li-Ion RELATED PARTS PART NUMBER LTC2942-1 LTC2941 LTC2941-1 LTC4150 Battery Chargers LTC1734 LTC4002 LTC4052 LTC4053 LTC4057 LTC4058 LTC4059 LTC4061 LTC4063 LTC4088 Lithium-Ion Battery Charger in ThinSOT™ Switch Mode Lithium-Ion Battery Charger Monolithic Lithium-Ion Battery Pulse Charger USB Compatible Monolithic Li-Ion Battery Charger Lithium-Ion Linear Battery Charger Standalone 950mA Lithium-Ion Charger in DFN 900mA Linear Lithium-Ion Battery Charger Standalone Linear Li-Ion Battery Charger with Thermistor Input Li-Ion Charger with Linear Regulator High Efficiency Battery Charger/USB Power Manager Simple ThinSOT Charger, No Blocking Diode, No Sense Resistor Needed Standalone, 4.7V ≤ VIN ≤ 24V, 500kHz Frequency No Blocking Diode or External Power FET Required, ≤1.5A Charge Current Standalone Charger with Programmable Timer, Up to 1.25A Charge Current Up to 800mA Charge Current, Thermal Regulation, ThinSOT Package C/10 Charge Termination, Battery Kelvin Sensing, ±7% Charge Accuracy 2mm × 2mm DFN Package, Thermal Regulation, Charge Current Monitor Output 4.2V, ±0.35% Float Voltage, Up to 1A Charge Current, 3mm × 3mm DFN Package Up to 1A Charge Current, 100mA, 125mV LDO, 3mm × 3mm DFN Package Maximizes Available Power from USB Port, Bat-Track™, Instant-On Operation, 1.5A Max Charge Current, 180mΩ Ideal Diode with