LTC3738

FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ LTC3738 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning DESCRIPTIO The LTC®3738 is a 3-phase synchronous step-down switching regulator controller that drives all N-channel external power MOSFET stages in a phase-lockable, fixed frequency architecture. The 3-phase technique effectively triples the fundamental frequency, improving transient response while operating each controller at an optimal frequency for efficiency and ease of thermal design. Light load efficiency is optimized by using a choice of output Stage Shedding or Pulse Skip mode technology. The LTC3738 also allows users to program load slope via a resistor for AVP control. Both external and internal thermal sensing are available from the on-chip thermal detector and comparator. A differential amplifier provides sensing of both the high and low sides of the output voltage. Soft-start and a defeatable, timed short-circuit shutdown protect the MOSFETs and the load. A foldback current circuit also provides protection for the external MOSFETs under short-circuit or overload conditions. An all- “1” VID detector turns off the regulator after a 1µs timeout. , LTC and LT are registered trademarks of Linear Technology Corporation. OPTI-LOOP is a registered trademark of Linear Technology Corporation. Stage Shedding is a trademark of Linear Technology Corporation. 3-Phase Controller with Onboard MOSFET Drivers Programmable Active Voltage Positioning (AVP) with True Current Sensing Programmable External Thermal Detection or Internal Thermal Sensing Precise Output Current Matching Optimizes Thermal Performance and Solution Size Supports Starting into Precharged VOUTS Differential Amplifier Accurately Senses VOUT PWM, Pulse Skip and Stage SheddingTM Operation Synchronizable 210kHz to 530kHz Per Phase, Fixed Frequency Output Power Good Indicator with Adaptive Blanking Adjustable Soft-Start Current Ramping Short-Circuit Shutdown Timer with Defeat Option OPTI-LOOP® Compensation Minimizes COUT 38-Lead (5mm × 7mm) QFN Package APPLICATIO S ■ ■ High Performance Notebook Computers Servers, Desktop Computers and Workstations U.S. Patent Numbers: 5481178, 5994885, 5929620, 6177787, 6144194, 6580258, 6462525, 6593724, 6674274, 6100678 pending on AVP technique. TYPICAL APPLICATIO 5V VRM10 Step-Down Controller VCC 10µF LTC3738 BOOST1 BOOST2 BOOST3 0.1µF SW3 SW2 SW1 POWER GOOD INDICATOR MODE SELECTION/SYNC IN PGOOD FCB/SYNC PLLFLTR THERMAL INPUT VR HOT INDICATOR ON/OFF 680pF ITH 5k 0.1µF SS SGND EAIN AVP IN + IN – TSNS VR_HOTB OUTEN TG1 SW1 BG1 SENSE1+ SENSE1– TG2 SW2 BG2 PGND SENSE2+ SENSE2– TG3 SW3 BG3 SENSE3+ SENSE3– VID0-VID5 6 VID BITS VIN 0.8µH 0.002Ω VIN 0.8µH 0.002Ω VOUT 0.8375V TO 1.6000V 0.8µH 0.002Ω 100pF U + U U + VIN 5V TO 28V 22µF ×2 470µF ×4 3738 TA01 3738f 1 LTC3738 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO BOOST1 TOP VIEW PGOOD OUTEN VID2 VID1 VID0 VID5 Topside Driver Voltages (BOOSTN) ............ 38V to –0.3V Switch Voltage (SWN)................................... 32V to –5V Boosted Driver Voltage (BOOSTN – SWN) .... 7V to –0.3V Peak Output Current fOSC Oscillator and Phase-Locked Loop VPLLFLTR = 1.2V VPLLFLTR = 0V VPLLFLTR = 2.4V 325 190 480 365 220 550 1.2 20 20 120 240 1 1.000 0.5 5 415 250 630 kHz kHz kHz V µA µA Deg Deg µs V/V mV V dB MHz V kΩ mA mA mV V V V The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = VOUTEN = VSS = 5V unless otherwise noted. CONDITIONS MIN TYP MAX UNITS RRELPHS No_CPU Detection tNOCPU AV VOS CM CMRR GBP VO(MAX) RIN ISINK ISOURCE Differential Amplifier Active Voltage Positioning VAVP – VO(MAX) Max Voltage Drops VAVP to VO Thermal Detection VINT VINT_HYS VTH_TH Thermal Comparator Trip Threshold Hysteresis Internal Detection Enable Threshold Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD × 34°C/W) Note 3: The IC is tested in a feedback loop that includes the differential amplifier driving the VID DAC into the error amplifier and servoing the resultant voltage to the midrange point for the error amplifier (VITH = 1.2V). Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 5: The minimum on-time condition corresponds to an inductor peakto-peak ripple current of ≥ 40% of IMAX (see minimum on-time considerations in the Applications Information Section). Note 6: ATTENERR specification is in addition to the output voltage accuracy specified at VID code 110101. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 3738f 4 LTC3738 TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs IOUT 100 90 80 EFFICIENCY (%) VFCB/SYNC = 5V 92 91 IL = 20A 90 EFFICIENCY (%) EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 VFCB/SYNC = OPEN VFCB/SYNC = 0V VIN = 12V VOUT = 1.2V FREQUENCY = 210kHz 10 1 INDUCTOR CURRENT (A) 100 3738 G01 Reference Voltage vs Temperature 610 4.0 605 3.5 MAXIMUM ISENSE THRESHOLD (mV) ERROR AMPLIFIER gm (mmho) REFERENCE VOLTAGE (mV) 600 595 590 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) Oscillator Frequency vs Temperature 600 550 500 FREQUENCY (kHz) VPLLFLTR = 5V VPLLFLTR = 2.4V FREQUENCY (kHz) UNDERVOLTAGE RESET (V) 450 400 350 300 250 200 150 VPLLFLTR = 0V VPLLFLTR = 1.2V 100 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) UW 75 90 3738 G04 TA = 25°C unless otherwise noted. Efficiency vs Frequency Efficiency vs VIN VIN = 12V FREQUENCY = 210kHz 92 91 90 89 88 87 86 VIN = 5V VIN = 10V VIN = 14V 89 88 IL = 50A 87 86 85 4 5 6 7 8 9 10 VIN (V) 11 12 13 14 3733 G02 VIN = 12V 85 VOUT = 1.2V ILOAD = 20A 84 250 300 200 400 350 FREQUENCY (kHz) 450 500 3738 G03 Error Amplifier gm vs Temperature 85 Maximum ISENSE Threshold vs Temperature 80 VO = 1.85V 75 VO = 0.8V 70 3.0 2.5 2.0 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 65 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 3738 G05 3738 G06 Oscillator Frequency vs VPLLFLTR 550 500 450 400 350 300 250 200 75 90 0 0.4 0.8 1.2 1.6 VPLLFLTR (V) 2.0 2.4 3738 G08 Undervoltage Reset Voltage vs Temperature 5.0 4.5 4.0 3.5 3.0 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 3738 G07 3738 G09 3738f 5 LTC3738 TYPICAL PERFOR A CE CHARACTERISTICS Short-Circuit Arming and Latchoff vs Temperature 5.0 4.5 4.0 3.5 LATCHOFF 3.0 2.5 2.0 –45 –30 –15 ARMING SUPPLY CURRENT (mA) SHUTDOWN CURRENT (µA) SS PIN VOLTAGE (V) 0 15 30 45 60 TEMPERATURE (°C) SS Pull-Up Current vs Temperature 2.5 75 ISENSE VOLTAGE THRESHOLD (mV) SS PULL-UP CURRENT (µA) 2.0 ISENSE VOLTAGE (mV) 1.5 1.0 0.5 0 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) Percentage of Nominal Output vs Peak ISENSE (Foldback) 80 70 MAXIMUM DUTY FACTOR (%) TOTAL ISENSE CURRENT (µA) PEAK ISENSE VOLTAGE (mV) 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 PERCENTAGE OF NOMINAL OUTPUT VOLTAGE (%) 3738 G16 6 UW 75 90 3738 G10 TA = 25°C unless otherwise noted. Shutdown Current vs Temperature 65 60 Supply Current vs Temperature 2.9 2.7 55 50 45 40 35 30 2.5 2.3 2.1 1.9 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 25 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) 75 90 3738 G11 3738 G12 Maximum Current Sense Threshold vs Duty Factor 90 80 70 60 50 40 30 20 10 0 –10 0 75 90 0 20 40 60 DUTY FACTOR (%) 80 100 3738 G14 Peak Current Threshold vs VITH 50 25 –20 0 0.4 0.8 1.2 1.6 VITH (V) 2.0 2.4 3738 G15 3738 G13 Maximum Duty Factors vs Temperature 100 VPLLFLTR = 0V 98 0 –20 –40 –60 –80 Total ISENSE Current vs VOUT 96 94 –100 –120 –140 –160 92 90 –45 –30 –15 –180 0 15 30 45 60 TEMPERATURE (°C) 75 90 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOUT (V) 2 3738 G17 3738 G18 3738f LTC3738 TYPICAL PERFOR A CE CHARACTERISTICS MAXIMUM CURRENT THRESHOLD MISMATCH (mV) Maximum Current Threshold Mismatch vs Temperature 3.0 2.5 VAVP – VIN+ (mV) 180 2.0 1.5 1.0 0.5 0 –45 –30 –15 0 15 30 45 60 TEMPERATURE (°C) Shed Mode at 1A, Light Load Current VOUT 10mV/DIV VSW1 5V/DIV VSW2 5V/DIV VSW3 5V/DIV VIN = 12V 2µs/DIV VOUT = 1.5V VFCB = VCC FREQUENCY = 210kHz 3738 G21 Continuous Mode at 1A, Light Load Current VOUT 10mV/DIV VSW1 5V/DIV VSW2 5V/DIV VSW3 5V/DIV VIN = 12V 2µs/DIV VOUT = 1.5V VFCB = GND FREQUENCY = 210kHz 3738 G23 UW TA = 25°C unless otherwise noted. (VAVP – VIN+) vs (VSENSE+ – VSENSE–) 135 90 45 0 75 90 –45 –15 0 30 45 15 VSENSE+ – VSENSE– (mV) 60 3738 G20 3738 G19 Pulse Skip Mode at 1A, Light Load Current VOUT 10mV/DIV VSW1 5V/DIV VSW2 5V/DIV VSW3 5V/DIV VIN = 12V 2µs/DIV VOUT = 1.5V VFCB = OPEN FREQUENCY = 210kHz 3738 G22 Load Transient with AVP VOUT 50mV/DIV ∆IOUT 100A STEP dI/dt > 200A/µs 80mV INTEL SPEC VIN = 12V VOUT = 1.35V COUT = 10 × 330µF/2.5V SANYO TPE POSCAP + 18 × 22µF/X5R CERAMIC 3738 G24 3738f 7 LTC3738 PI FU CTIO S FCB/SYNC (Pin 1): Forced Continuous Control Input. The voltage applied to this pin sets the operating mode of the controller. The forced continuous current mode is active when the applied voltage is less than 0.6V. Pulse skip mode operation will be active when the pin is allowed to float and Stage Shedding mode will be active if the pin is tied to the VCC pin. When an external clock is present, the controller will be synchronized to the external clock and forced continuous mode is selected internally. (Do not apply voltage to this pin prior to the application of voltage on the VCC pin.) PLLFLTR (Pin 2): The phase-locked loop’s lowpass filter is tied to this pin. Alternatively, this pin can be driven with an AC or DC voltage source to vary the frequency of the internal oscillator. (Do not apply voltage to this pin prior to the application of voltage on the VCC pin.) IN+, IN– (Pins 4, 3): Inputs to a Precision, Unity-Gain Differential Amplifier with Internal Precision Resistors. This provides true remote sensing of both the positive and negative load terminals for precise output voltage control. AVP (Pin 5): Active Voltage Positioning Load Slope Programming Pin. A resistor tied between this pin and IN+ sets the load slope. EAIN (Pin 6): This is the input to the error amplifier which compares the VID divided feedback voltage to the internal 0.6V reference voltage. SENSE1+, SENSE2+, SENSE3+, SENSE1–, SENSE2–, SENSE3– (Pins 7 to 12): The Inputs to Each Differential Current Comparator. The ITH pin voltage and built-in offsets between the SENSE– and SENSE+ pins, in conjunction with RSENSE, set the current trip threshold level. SS (Pin 13): Combination of Soft-Start and Short-Circuit Detection Timer. A capacitor to ground at this pin sets the ramp time to full current output as well as the time delay prior to an output voltage short-circuit shutdown. ITH (Pin 14): Error Amplifier Output and Switching Regulator Compensation Point. All three current comparator’s thresholds increase with this control voltage. TSNS (Pin 15): This pin selects external or internal thermal detection. Tying this pin to VCC will enable the internal thermal detector. When the voltage at this pin is less than VCC – 1.6V, the internal thermal detector is disabled and this pin serves as the input to an internal comparator which is referenced to VCC/3. VR_HOTB (Pin 16): This open-collector output is pulled low when voltage at the TSNS pin is less than VCC/3. If TSNS is tied to VCC, this pin is pulled low when the internal thermal detector is tripped. PGND (Pin 24): Driver Power Ground. This pin connects to the sources of the bottom N-channel external MOSFETs and the (–) terminals of CIN. BG1, BG2, BG3 (Pins 25, 23, 22): High Current Gate Drives for the Bottom N-Channel MOSFETs. Voltage swing at these pins is from ground to VCC. VCC (Pin 26): Main Supply Pin. Because this pin supplies both the controller circuit power as well as the high power pulses supplied to drive the external MOSFET gates, this pin needs to be very carefully and closely decoupled to the IC’s PGND pin. 8 U U U 3738f LTC3738 PI FU CTIO S SW1, SW2, SW3 (Pins 30, 27, 21): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN (where VIN is the external MOSFET supply rail). TG1, TG2, TG3 (Pins 31, 28, 20): High Current Gate Drives for Top N-Channel MOSFETs. These are the outputs of the floating drivers with a voltage swing equal to the boost voltage source superimposed on the switch node voltage SW. BOOST1, BOOST2, BOOST3 (Pins 32, 29, 19): Positive Supply Pins to the Topside Floating Drivers. Bootstrapped capacitors, charged with external Schottky diodes and a boost voltage source are connected between the BOOST and SW pins. Voltage swing at the BOOST pins is from the boost source voltage (typically VCC) to this boost source voltage +VIN (where VIN is the external MOSFET supply rail). PGOOD (Pin 33): This open-drain output is pulled low when the output voltage is outside the PGOOD tolerance window. PGOOD is blanked during VID transitions for approximately 100µs. VID0, VID1, VID2, VID3, VID4, VID5 (Pins 35, 36, 37, 17, 18, 34): Output Voltage Programming Input Pins. When VID5 is tied to VCC, the Intel VRM9 VID table is selected. When voltage of VID5 is less than VCC – 2V, VID5 serves as the fifth VID bit of VRM10. OUTEN (Pin 38): On/Off Control of the Controller. SGND (Pin 39, Exposed Pad): Signal Ground. This pin must be soldered to the ground plane. U U U 3738f 9 LTC3738 FU CTIO AL DIAGRA PGOOD 2.4V 2.5µA FCB/SYNC FCB PHASE DET 0.6V RLP PLLFLTR CLP OSCILLATOR CLK1 CLK2 CLK3 IN– 80k 80k – A1 IN + + 80k RPRE-AVP AVP RAVP 80k SENSE1+ SENSE1– SENSE2+ SENSE2– SENSE3+ SENSE3– SHDN – I1 R1 8k + – + –+ – + – + +– ADDER EAIN 0.600V VFB – + + 0.660V – EA 45k OV 2.4V 45k VOUT ITH CC R2 VARIABLE RC VID SELECTION 1.5µA VCC SHDN RST SHED 0.600V RUN SOFTSTART INTERNAL SUPPLY VREF VCC SGND VCC 5(VFB) VRM9/VRM10 VID DECODER 6V + CCC SS OUTEN 1µs NO_CPU 100k VID5 VID0 VID1 VID2 VID3 VID4 CSS + 10 W TSNS – + 100µs BLANKING VID TRANSITIONS EAIN – + 0.54V VCC/3 INTERNAL THERMAL DETECTION DUPLICATE FOR SECOND AND THIRD CONTROLLER CHANNELS VCC BOOST DB VIN – + MUX TCMP 0.66V VR_HOTB RS LATCH S R Q Q DROP OUT DET FORCED BOT TOP ON SWITCH LOGIC VCC FCB BOT BG PGND TOP TG CB – + U U + CIN SW – ++ 3mV – I2 VCC + 30k SENSE L SLOPE COMP 5(VFB) – 30k SENSE RSENSE COUT 3738 F01 Figure 1 3738f LTC3738 OPERATIO Main Control Loop The IC uses a constant frequency, current mode stepdown architecture. During normal operation, each top MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the main current comparator, I1, resets each RS latch. The peak inductor current at which I1 resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier EA. The EAIN pin receives a portion of the voltage feedback signal via the differential amplifier through the internal VID DAC and is compared to the internal reference voltage. When the load current increases, it causes a slight decrease in the EAIN pin voltage relative to the 0.6V reference, which in turn causes the ITH voltage to increase until each inductor’s average current matches one third of the new load current (assuming all three current sensing resistors are equal). In pulse skip mode and Stage Shedding mode, after each top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by current comparator I2, or the beginning of the next cycle. The top MOSFET drivers are biased from floating bootstrap capacitor CB, which is normally recharged during each off cycle through an external Schottky diode. When VIN decreases to a voltage close to VOUT, however, the loop may enter dropout and attempt to turn on the top MOSFET continuously. The dropout detector counts the number of oscillator cycles that the bottom MOSFET remains off and periodically forces a brief on period to allow CB to recharge. The main control loop is shut down by pulling the OUTEN pin low. Pulling up OUTEN allows an internal 1.5µA current source to charge soft-start capacitor CSS at the SS pin. The internal ITH voltage is clamped to the SS voltage while CSS is slowly charged up. This “soft-start” clamping prevents abrupt current from being drawn from the input power source. When the OUTEN pin is low, all functions are kept in a controlled state. U (Refer to Functional Diagram) Low Current Operation The FCB/SYNC pin is a multifunction pin: 1) a logic input to select between three modes of operation and 2) external clock input pin for synchronization. When the FCB/SYNC pin voltage is below 0.6V, the controller performs as a continuous, PWM current mode synchronous switching regulator. The top and bottom MOSFETs are alternately turned on to maintain the output voltage independent of direction of inductor current. When the FCB/SYNC pin is below VCC – 1.5V, but greater than 0.6V, the controller performs as a pulse skip mode switching regulator. Pulse skip mode operation turns off the synchronous MOSFET(s) when the inductor current goes negative. Switching cycles will be skipped when the output load current drops below 3% of the maximum designed load current in order to maintain the output voltage. Pulse skip operation provides low noise, constant frequency operation at light load conditions. When the FCB/SYNC pin is tied to the VCC pin, Stage Shedding mode is enabled. This mode provides constant frequency, discontinuous current operation over the widest possible output current range. At approximately 10% of maximum designed load current, the second and third output stages are shut off and the first controller alone is active in discontinuous current mode. This “stage shedding” optimizes efficiency by eliminating the gate charging losses and switching losses of the other two output stages. Additional cycles will be skipped when the output load current drops below 1% of maximum designed load current in order to maintain the output voltage. This constant frequency operation is more efficient than pulse skip mode operation at very light load conditions. 3738f 11 LTC3738 OPERATIO Tying the FCB/SYNC pin to ground will force continuous current operation. This is the least efficient operating mode, but may be desirable in certain applications. The output can source or sink current in this mode. When forcing continuous operation and sinking current, this current will be forced back into the main power supply, potentially boosting the input supply to dangerous voltage levels. Feeding a clock signal into the FCB/SYNC pin will synchronize the LTC3738 to the external clock. See Frequency Synchronization or Setup for more information. Frequency Synchronization or Setup The phase-locked loop allows the internal oscillator to be synchronized to an external source using the FCB/SYNC pin. The output of the phase detector at the PLLFLTR pin is also the DC frequency control input of the oscillator which operates over a 210kHz to 530kHz range corresponding to a voltage input from 0V to 2.4V. When locked, the PLL aligns the turn on of the top MOSFET to the rising edge of the synchronizing signal and forced continuous mode is set internally. When no frequency information is supplied to the FCB/SYNC pin, PLLFLTR goes low, forcing the oscillator to minimum frequency. A DC source can be applied to the PLLFLTR pin to externally set the desired operating frequency. Differential Amplifier This amplifier provides true differential output voltage sensing. Sensing both VOUT+ and VOUT– benefits regulation in high current applications and/or applications having electrical interconnection losses. This sensing also isolates the physical power ground from the physical signal ground preventing the possibility of troublesome “ground loops” on the PC layout and prevents voltage errors caused by board-to-board interconnects, particularly helpful in VRM designs. 12 U (Refer to Functional Diagram) Power Good The PGOOD pin is connected to the drain of an internal MOSFET. The MOSFET is turned on when the output voltage exceeds the PGOOD ±10% tolerance window. The PGOOD signal is blanked for approximately 100µs during VID transitions. If a new VID transition occurs before the previous blanking time expires, the timer is reset. Short-Circuit Detection The SS capacitor is used initially to limit the inrush current from the input power source. Once the controllers have been given time, as determined by the capacitor on the SS pin, to charge up the output capacitors and provide full load current, the SS capacitor is then used as a shortcircuit timeout circuit. If the output voltage falls to less than 62.5% of its nominal output voltage, the SS capacitor begins discharging, assuming that the output is in a severe overcurrent and/or short-circuit condition. If the condition lasts for a long enough period, as determined by the size of the SS capacitor, the controller will be shut down until the OUTEN pin voltage is recycled. This built-in latchoff can be overridden by providing >5µA at a compliance of 4V to the SS pin. This current shortens the soft-start period but prevents net discharge of the SS capacitor during a severe overcurrent and/or short-circuit condition. Foldback current limiting is activated when the output voltage falls below 62.5% of its nominal level whether or not the shortcircuit latchoff circuit is enabled. Foldback current limit can be overridden by clamping the EAIN pin such that the voltage is held above the (62.5%)(0.6V) or 0.375V level even when the actual output voltage is low. The SS capacitor will be reset if the input voltage, (VCC) is allowed to fall below approximately 4V. The capacitor on the pin will be discharged until the short-circuit arming latch is disarmed. The SS capacitor will attempt to cycle through a normal soft-start ramp up after the VCC supply rises above 4V. This circuit prevents power supply latchoff in the event of input power switching break-before-make situations. 3738f LTC3738 OPERATIO Start-Up The start-up of the LTC3738 is controlled by the voltage ramp on the SS pin. The start-up is not completed until the short-circuit arming latch is enabled. During start-up, the foldback current limit is temporarily defeated and at the same time no reverse inductor current is allowed. This is helpful for situations where output voltage has been “prebiased” at some voltage before the controller is enabled. This will prevent sinking current during start-up which would otherwise pull current from the pre-biased output. VID Table and NO_CPU Detection The LTC3738 has a VID block which is compatible with VRM9 and VRM10. Tying VID5 to VCC will select the VRM9 table. When the voltage at VID5 is less than VCC – 1.5V, the VRM10 table is selected and this pin serves as the VID5 bit of VRM10. There is a built in –25mV output offset for the VRM10 VID table and a –12.5mV output offset for the VRM9 VID table. The LTC3738 detects the presence of CPU by monitoring the VID bits. If a VID0-VID4 all “1” condition is detected, the controller acknowledges a NO_CPU fault. If this fault condition persists for more than 1µs, the SS pin is pulled low and the controller is shut down. The LTC3738 will attempt a normal start-up when the NO_CPU fault is removed. U (Refer to Functional Diagram) Thermal Detection An accurate comparator and a thermal detector are integrated into the LTC3738 for external or internal thermal detection. Tying TSNS to VCC will enable an internal thermal detector which generates a thermal event at or above 120°C with 10°C hysteresis. When the voltage at TSNS is less than VCC – 1.6V, the internal thermal detector is disabled and this pin serves as the input to an accurate comparator which is referenced to VCC/3 with a hysteresis of VCC/24. A thermal event is generated when the voltage at TSNS is less than VCC/3. VR_HOTB, an open-collector output pin, will be pulled low when a thermal event occurs. Active Voltage Positioning Load slope is programmable in the LTC3738 through external resistors. The inductor current information for all three channels is sensed and combined; the final result is presented as a voltage drop between AVP and IN+. This voltage drop is scaled through two external resistors attached to IN+ and then added to the output voltage as the compensation for load slope. The final load slope is defined by the inductor current sense resistors and the two external resistors mentioned above. 3738f 13 LTC3738 APPLICATIO S I FOR ATIO The basic application circuit is shown on the first page of this data sheet. External component selection is driven by the load requirement, and normally begins with the selection of an inductance value based upon the desired operating frequency, inductor current and output voltage ripple requirements. Once the inductors and operating frequency have been chosen, the current sensing resistors can be calculated. Next, the power MOSFETs and Schottky diodes are selected. Finally, CIN and COUT are selected according to the required voltage ripple requirements. The circuit shown on the first page of this data sheet can be configured for operation up to a MOSFET supply voltage of 28V (limited by the external MOSFETs). Operating Frequency The IC uses a constant frequency architecture with the frequency determined by an internal capacitor. This capacitor is charged by a fixed current plus an additional current which is proportional to the voltage applied to the PLLFLTR pin. Refer to the Phase-Locked Loop and Frequency Synchronization and Setup sections for additional information. A graph for the voltage applied to the PLLFLTR pin versus frequency is given in Figure 2. As the operating frequency is increased the gate charge losses will be higher, reducing efficiency (see Efficiency Considerations). The maximum switching frequency is approximately 530kHz. 550 OPERATING FREQUENCY (kHz) 450 350 250 150 0 0.5 1.0 1.5 2.0 PLLFLTR PIN VOLTAGE (V) 2.5 3738 F02 Figure 2. Operating Frequency vs VPLLFLTR 14 U Inductor Value Calculation and Output Ripple Current The operating frequency and inductor selection are interrelated in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET gate charge and transition losses. In addition to this basic tradeoff, the effect of inductor value on ripple current and low current operation must also be considered. The PolyPhase approach reduces both input and output ripple currents while optimizing individual output stages to run at a lower fundamental frequency, enhancing efficiency. The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL per individual section, N, decreases with higher inductance or frequency and increases with higher VIN or VOUT: ∆IL = VOUT ⎛ VOUT ⎞ ⎜ 1− ⎟ fL ⎝ VIN ⎠ W UU where f is the individual output stage operating frequency. In a PolyPhase converter, the net ripple current seen by the output capacitor is much smaller than the individual inductor ripple currents due to the ripple cancellation. The details on how to calculate the net output ripple current can be found in Application Note 77. Figure 3 shows the net ripple current seen by the output capacitors for the different phase configurations. The output ripple current is plotted for a fixed output voltage as the duty factor is varied between 10% and 90% on the x-axis. The output ripple current is normalized against the inductor ripple current at zero duty factor. The graph can be used in place of tedious calculations. As shown in Figure 3, the zero output ripple current is obtained when: VOUT k = where k = 1, 2, ..., N – 1 VIN N 3738f LTC3738 APPLICATIO S I FOR ATIO 1.0 0.9 0.8 0.7 IO(P-P) VO/fL 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 3738 F03 Figure 3. Normalized Peak Output Current vs Duty Factor [IRMS = 0.3(IO(P-P)] So the number of phases used can be selected to minimize the output ripple current and therefore the output ripple voltage at the given input and output voltages. In applications having a highly varying input voltage, additional phases will produce the best results. Accepting larger values of ∆IL allows the use of low inductances but can result in higher output voltage ripple. A reasonable starting point for setting ripple current is ∆IL = 0.4(IOUT)/N, where N is the number of channels and IOUT is the total load current. Remember, the maximum ∆IL occurs at the maximum input voltage. The individual inductor ripple currents are constant determined by the inductor, input and output voltages. Inductor Core Selection Once the value for the inductors is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of ferrite, molypermalloy or Kool Mµ® cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. U Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Power MOSFET and Schottky Diode Selection At least two external power MOSFETs must be selected for each of the three output sections: One N-channel MOSFET for the top (main) switch and one or more N-channel MOSFET(s) for the bottom (synchronous) switch. The number, type and “on” resistance of all MOSFETs selected take into account the voltage step-down ratio as well as the actual position (main or synchronous) in which the MOSFET will be used. A much smaller and much lower input capacitance MOSFET should be used for the top MOSFET in applications that have an output voltage that is less than 1/3 of the input voltage. In applications where VIN >> VOUT, the top MOSFETs’ “on” resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300kHz. MOSFET manufacturers have designed special purpose devices that provide reasonably low “on” resistance with significantly reduced input capacitance for the main switch application in switching regulators. The peak-to-peak MOSFET gate drive levels are set by the voltage, VCC, requiring the use of logic-level threshold MOSFETs in most applications. Pay close attention to the BVDSS specification for the MOSFETs as well; many of the logic-level MOSFETs are limited to 30V or less. Selection criteria for the power MOSFETs include the “on” resistance RSD(ON), input capacitance, input voltage and maximum output current. MOSFET input capacitance is a combination of several components but can be taken from the typical “gate charge” curve included on most data sheets (Figure 4). Kool Mµ is a registered trademark of Magnetics, Inc. 3738f W UU 15 LTC3738 APPLICATIO S I FOR ATIO MILLER EFFECT VGS a QIN CMILLER = (QB – QA)/VDS b VGS V 3738 F04 Figure 4. Gate Charge Characteristic The curve is generated by forcing a constant input current into the gate of a common source, current source loaded stage and then plotting the gate voltage versus time. The initial slope is the effect of the gate-to-source and the gateto-drain capacitance. The flat portion of the curve is the result of the Miller capacitance effect of the drain-tosource capacitance as the drain drops the voltage across the current source load. The upper sloping line is due to the drain-to-gate accumulation capacitance and the gateto-source capacitance. The Miller charge (the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given VDS drain voltage, but can be adjusted for different VDS voltages by multiplying by the ratio of the application VDS to the curve specified VDS values. A way to estimate the CMILLER term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated VDS voltage specified. CMILLER is the most important selection criteria for determining the transition loss term in the top MOSFET but is not directly specified on MOSFET data sheets. CRSS and COS are specified sometimes but definitions of these parameters are not included. When the controller is operating in continuous mode the duty cycles for the top and bottom MOSFETs are given by: Main Switch Duty Cycle = VOUT VIN ⎛V –V ⎞ Synchronous Switch Duty Cycle = ⎜ IN OUT ⎟ ⎝ ⎠ VIN 16 U VIN W UU The power dissipation for the main and synchronous MOSFETs at maximum output current are given by: VOUT ⎛ IMAX ⎞ ⎜ ⎟ (1 + δ )RDS(ON) + VIN ⎝ N ⎠ I VIN2 MAX (RDR )(CMILLER ) • 2N ⎡ 1 1⎤ + ⎢ ⎥( f ) ⎢ VCC – VTH(MIN) VTH(MIN) ⎥ ⎣ ⎦ 2 2 VDS PMAIN = V –V ⎛I ⎞ PSYNC = IN OUT ⎜ MAX ⎟ (1 + δ )RDS(ON) ⎝N⎠ VIN where N is the number of output stages, δ is the temperature dependency of RDS(ON), RDR is the effective top driver resistance (approximately 2Ω at VGS = VMILLER), VIN is the drain potential and the change in drain potential in the particular application. VTH(MIN) is the data sheet specified typical gate threshold voltage specified in the power MOSFET data sheet. CMILLER is the calculated capacitance using the gate charge curve from the MOSFET data sheet and the technique described above. Both MOSFETs have I2R losses while the topside N-channel equation includes an additional term for transition losses, which peak at the highest input voltage. For VIN < 12V, the high current efficiency generally improves with larger MOSFETs, while for VIN > 12V, the transition losses rapidly increase to the point that the use of a higher RDS(ON) device with lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short circuit when the synchronous switch is on close to 100% of the period. The term (1 + δ ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but δ = 0.005/°C can be used as an approximation for low voltage MOSFETs. 3738f LTC3738 APPLICATIO S I FOR ATIO The Schottky diodes shown in the Typical Application on the first page of this data sheet conduct during the dead time between the conduction of the two large power MOSFETs. This prevents the body diode of the bottom MOSFET from turning on, storing charge during the dead time and requiring a reverse recovery period which could cost as much as several percent in efficiency. A 2A to 8A Schottky is generally a good compromise for both regions of operation due to the relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. CIN and COUT Selection Input capacitance ESR requirements and efficiency losses are reduced substantially in a multiphase architecture because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the RMS current squared. A 3-stage, single output voltage implementation can reduce input path power loss by 90%. In continuous mode, the source current of each top N-channel MOSFET is a square wave of duty cycle VOUT/VIN. A low ESR input capacitor sized for the maximum RMS current must be used. The details of a close form equation can be found in Application Note 77. Figure 5 shows the input capacitor ripple current for different phase configurations with the output voltage fixed and input voltage varied. The input ripple current is normalized against the DC output current. The graph can be used in place of tedious calculations. The minimum input ripple current can be achieved when the product of phase number and output voltage, N(VOUT), is approximately equal to the input voltage VIN or: RMS INPUT RIPPLE CURRNET DC LOAD CURRENT VOUT k = where k = 1, 2, ..., N – 1 VIN N So the phase number can be chosen to minimize the input capacitor size for the given input and output voltages. In the graph of Figure 5, the local maximum input RMS capacitor currents are reached when: VOUT 2k – 1 where k = 1, 2, ..., N = VIN N U These worst-case conditions are commonly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. Always consult the capacitor manufacturer if there is any question. The Figure 5 graph shows that the peak RMS input current is reduced linearly, inversely proportional to the number N of stages used. It is important to note that the efficiency loss is proportional to the input RMS current squared and therefore a 3-stage implementation results in 90% less power loss when compared to a single phase design. Battery/input protection fuse resistance (if used), PC board trace and connector resistance losses are also reduced by the reduction of the input ripple current in a PolyPhase system. The required amount of input capacitance is further reduced by the factor, N, due to the effective increase in the frequency of the current pulses. Ceramic capacitors are becoming very popular for small designs but several cautions should be observed. “X7R”, “X5R” and “Y5V” are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions 0.6 0.5 0.4 0.3 0.2 0.1 0 1-PHASE 2-PHASE 3-PHASE 4-PHASE 6-PHASE 0.1 0.2 0.3 0.4 0.5 0.6 0.7 DUTY FACTOR (VOUT/VIN) 0.8 0.9 3738 F05 W UU Figure 5. Normalized Input RMS Ripple Current vs Duty Factor for One to Six Output Stages 3738f 17 LTC3738 APPLICATIO S I FOR ATIO applied. Physically, if the capacitance value changes due to applied voltage change, there is a concommitant piezo effect which results in radiating sound! A load that draws varying current at an audible rate may cause an attendant varying input voltage on a ceramic capacitor, resulting in an audible signal. A secondary issue relates to the energy flowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge. The voltage can increase at a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing! Ceramic capacitors, when properly selected and used however, can provide the lowest overall loss due to their extremely low ESR. The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR requirement is satisfied the capacitance is adequate for filtering. The steady-state output ripple (∆VOUT) is determined by: ⎛ 1⎞ ∆VOUT ≈ ∆IRIPPLE ⎜ ESR + ⎟ ⎝ 8NfCOUT ⎠ where f = operating frequency of each stage, N is the number of output stages, COUT = output capacitance and ∆IL = ripple current in each inductor. The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. The output ripple will be less than 50mV at max VIN with ∆IL = 0.4IOUT(MAX) assuming: COUT required ESR < N • RSENSE and COUT > 1/(8Nf)(RSENSE) The emergence of very low ESR capacitors in small, surface mount packages makes very small physical implementations possible. The ability to externally compensate the switching regulator loop using the ITH pin allows a much wider selection of output capacitor types. The impedance characteristics of each capacitor type is significantly different than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design. Manufacturers such as Nichicon, United Chemicon and Sanyo should be considered for high performance through- 18 U hole capacitors. The OS-CON semiconductor dielectric capacitor available from Sanyo and the Panasonic SP surface mount types have a good (ESR)(size) product. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. Ceramic capacitors from AVX, Taiyo Yuden, Murata and Tokin offer high capacitance value and very low ESR, especially applicable for low output voltage applications. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several excellent choices are the AVX TPS, AVX TPSV, the KEMET T510 series of surface-mount tantalums or the Panasonic SP series of surface mount special polymer capacitors available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo POS-CAP, Sanyo OS-CON, Nichicon PL series and Sprague 595D series. Consult the manufacturer for other specific recommendations. RSENSE Selection for Output Current Once the frequency and inductor have been chosen, RSENSE1, RSENSE2, RSENSE3 are determined based on the required peak inductor current. The current comparator has a maximum threshold of 75mV/RSENSE and an input common mode range of SGND to (1.1) • VCC. The current comparator threshold sets the peak inductor current, yielding a maximum average output current IMAX equal to the peak value less half the peak-to-peak ripple current, ∆IL. Allowing a margin for variations in the IC and external component values yields: W UU RSENSE = N 50mV IMAX The IC works well with values of RSENSE from 0.001Ω to 0.02Ω. 3738f LTC3738 APPLICATIO S I FOR ATIO VCC Decoupling The VCC pin supplies power not only to the internal circuits of the controller but also to the top and bottom gate drivers and therefore must be bypassed very carefully to ground with a ceramic capacitor, type X7R or X5R (depending upon the operating temperature environment) of at least 1µF immediately next to the IC and preferably an additional 10µF placed very close to the IC due to the extremely high instantaneous currents involved. The total capacitance, taking into account the voltage coefficient of ceramic capacitors, should be 100 times as large as the total combined gate charge capacitance of ALL of the MOSFETs being driven. Good bypassing close to the IC is necessary to supply the high transient currents required by the MOSFET gate drivers while keeping the 5V supply quiet enough so as not to disturb the very small-signal high bandwidth of the current comparators. Topside MOSFET Driver Supply (CB, DB) External bootstrap capacitors, CB, connected to the BOOST pins, supply the gate drive voltages for the topside MOSFETs. Capacitor CB in the Functional Diagram is charged though diode DB from VCC when the SW pin is low. When one of the topside MOSFETs turns on, the driver places the CB voltage across the gate-source of the desired MOSFET. This enhances the MOSFET and turns on the topside switch. The switch node voltage, SW, rises to VIN and the BOOST pin follows. With the topside MOSFET on, the boost voltage is above the input supply (VBOOST = VCC + VIN). The value of the boost capacitor CB needs to be 30 to 100 times that of the total input capacitance of the topside MOSFET(s). The reverse breakdown of DB must be greater than VIN(MAX). Differential Amplifier The IC has a true remote voltage sense capability. The sensing connections should be returned from the load, back to the differential amplifier’s inputs through a U common, tightly coupled pair of PC traces. The differential amplifier rejects common mode signals capacitively or inductively radiated into the feedback PC traces as well as ground loop disturbances. The differential amplifier output signal is divided down through the VID DAC and is compared with the internal, precision 0.6V voltage reference by the error amplifier. The amplifier has a 0 to VCC common mode input range and an output swing range of 0 to VCC – 1.2V. The output uses an NPN emitter follower with 160kΩ feedback resistance. Output Voltage Selection of the VRM9 or VRM10 VID table is through the VID5 pin. Tying VID5 to VCC will select the VRM9 VID table. If the VRM9 VID table is selected (Table 1), output voltage in 25mV increments is produced from 1.1V to 1.85V. There is a built-in –12.5mV DC offset for the output voltage. If the VRM10 VID table is selected (Table 2), output voltage in 12.5mV increments is produced from 0.8375V to 1.6V. There is a built-in –25mV DC offset for output voltage. Active Voltage Position Control The LTC3738 senses inductor current information through monitoring voltage drops on the sense resistor RSENSE of all three channels. The voltage drops are added together and applied as VPRE-AVP between the AVP and IN+ pins, which are connected through resistor RPRE-AVP. Then VPRE-AVP is scaled through RAVP and added to output voltage as the compensation for the load voltage drop. In summary, the load slope is: W UU ⎛ RAVP ⎞ ⎜ RSENSE • ⎟ V/ A ⎝ RPRE− AVP ⎠ The recommended value for RAVP is 90Ω to 100Ω. 3738f 19 LTC3738 APPLICATIO S I FOR ATIO Table 1. VRM9 VID Table PROCESSOR PINS (0 = L0W, 1 = HIGH) VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 20 U Thermal Control VCC(CORE) (VDC) Output Off 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850 W UU When external thermal detection is enabled, the TSNS pin serves as the input to an accurate comparator which is referenced to VCC/3 and has a hysteresis of VCC/24. VR_HOTB is pulled low when the voltage at TSNS is less than VCC/3. In this case, the input of TSNS is an analog signal. If necessary, lowpass filter the signal before feeding it into the pin to avoid a false thermal trip. When VR_HOTB is reported, the operation of LTC3738 will not be affected, although there is another thermal sensor inside the IC for self protection. When the temperature of the IC is around 140°C, the LTC3738 will shut down and not start-up again until this overtemperature situation has been removed. This self shutdown feature is not tested but is guaranteed by design. ON/OFF Control The OUTEN pin provides simple ON/OFF control for the LTC3738. Driving the OUTEN pin above 0.8V permits the controller to start operating. Pulling OUTEN below 0.4V puts the LTC3738 into low current shutdown (IQ ≈ 50µA). Soft-Start Function The SS pin provides two functions: 1) soft-start and 2) a defeatable short-circuit latch off timer. Soft-start reduces the input power sources’ surge currents by gradually increasing the controller’s current limit (proportional to an internal buffered and clamped VITH). The latchoff timer prevents very short, extreme load transients from tripping the overcurrent latch. A small pull-up current (>5µA) supplied to the SS pin will prevent the overcurrent latch from operating. The following explanation describes how this function operates. An internal 1.5µA current source charges up the CSS capacitor. As the voltage on SS increases from 0V to 2.4V, 3738f LTC3738 Table 2. VRM10 VID Table PROCESSOR PINS (0 = LOW, 1 = HIGH) VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT (V) 0.8375 0.8500 0.8625 0.8750 0.8875 0.9000 0.9125 0.9250 0.9375 0.9500 0.9625 0.9750 0.9875 1.0000 1.0125 1.0250 1.0375 1.0500 1.0625 1.0750 1.0875 Off* Off* 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 PROCESSOR PINS (0 = LOW, 1 = HIGH) VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID3 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID5 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VOUT (V) 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500 1.5625 1.5750 1.5875 1.6000 *Output disabled—same as deasserting the Output Enable input the internal current limit is increased from 0V/RSENSE to 75mV/RSENSE. The output current limit ramps up slowly, taking 1.6s/µF to reach full current. The output current thus ramps up slowly, eliminating the starting surge current required from the input power supply. tIRAMP = 2.4V – 0 V CSS = (1.6s/µF) CSS 1.5µA The SS pin has an internal 6V zener clamp (see the Functional Diagram). Fault Conditions: Overcurrent Latchoff The SS pin also provides the ability to latch off the controllers when an overcurrent condition is detected. The SS capacitor is used initially to limit the inrush current of all three output stages. After the controllers have been 3738f 21 LTC3738 APPLICATIO S I FOR ATIO given adequate time to charge up the output capacitor and provide full load current, the SS capacitor is used for a short-circuit timer. If the output voltage falls to less than 62.5% of its nominal value, the SS capacitor begins discharging on the assumption that the output is in an overcurrent condition. If the condition lasts for a long enough period, as determined by the size of the SS capacitor, the controller will be shut down until the RUN pin voltage is recycled. If the overload occurs during startup, the time can be approximated by: tLO1 >> (CSS • 0.6V)/(1.5µA) = 4 • 105 (CSS) If the overload occurs after start-up, the voltage on the SS capacitor will continue charging and will provide additional time before latching off: tLO2 >> (CSS • 3V)/(1.5µA) = 2 • 106 (CSS) This built-in overcurrent latchoff can be overridden by providing a pull-up resistor to the SS pin from VCC as shown in Figure 6. When VCC is 5V, a 200k resistance will prevent the discharge of the SS capacitor during an overcurrent condition but also shortens the soft-start period, so a larger SS capacitor value will be required. Why should you defeat overcurrent latchoff? During the prototyping stage of a design, there may be a problem with noise pick-up or poor layout causing the protection circuit to latch off the controller. Defeating this feature allows troubleshooting of the circuit and PC layout. The internal foldback current limiting still remains active, thereby protecting the power supply system from failure. A decision can be made after the design is complete whether to rely solely on foldback current limiting or to enable the latchoff feature by removing the pull-up resistor. VCC RSS SS PIN CALCULATE FOR 0.375V TO 0.55V CSS 3738 F06 Figure 6. Defeating Overcurrent Latchoff 22 U The value of the soft-start capacitor CSS may need to be scaled with output current, output capacitance and load current characteristics. The minimum soft-start capacitance is given by: CSS > (COUT )(VOUT) (10 –4) (RSENSE) The minimum recommended soft-start capacitor of CSS = 0.1µF will be sufficient for most applications. Current Foldback In certain applications, it may be desirable to defeat the internal current foldback function. A negative impedance is experienced when powering a switching regulator. That is, the input current is higher at a lower VIN and decreases as VIN is increased. Current foldback is designed to accommodate a normal, resistive load having increasing current draw with increasing voltage. The EAIN pin should be artificially held 62.5% above its nominal operating level of 0.6V, or 0.375V in order to prevent the IC from “folding back” the peak current level. A suggested circuit is shown in Figure 7. The emitter of Q1 will hold up the EAIN pin to a voltage in the absence of VOUT that will prevent the internal sensing circuitry from reducing the peak output current. Removing the function in this manner eliminates the external MOSFET’s protective feature under short-circuit conditions. This technique will also prevent the short-circuit latchoff function from turning off the part during a shortcircuit event and the output current will only be limited to N • 75mV/RSENSE. VCC VCC LTC3738 Q1 EAIN 3738 F07 W UU Figure 7. Foldback Current Elimination 3738f LTC3738 APPLICATIO S I FOR ATIO Undervoltage Reset In the event that the input power source to the IC (VCC) drops below 4V, the SS capacitor will be discharged to ground and the controller will be shut down. When VCC rises above 4V, the SS capacitor will be allowed to recharge and initiate another soft-start turn-on attempt. This may be useful in applications that switch between two supplies that are not diode connected, but note that this cannot make up for the resultant interruption of the regulated output. Phase-Locked Loop and Frequency Synchronization The IC has a phase-locked loop comprised of an internal voltage controlled oscillator and phase detector. This allows the top MOSFET of output stage 1’s turn-on to be locked to the rising edge of an external source. The frequency range of the voltage controlled oscillator is ±50% around the center frequency fO. A voltage applied to the PLLFLTR pin of 1.2V corresponds to a frequency of approximately 350kHz. The nominal operating frequency range of the IC is 210kHz to 530kHz. The phase detector used is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. This type of phase detector will not lock the internal oscillator to harmonics of the input frequency. The PLL hold-in range, ∆fH, is equal to the capture range, ∆fC: ∆fH = ∆fC = ±0.5 fO The output of the phase detector is a complementary pair of current sources charging or discharging the external filter components on the PLLFLTR pin. A simplified block diagram is shown in Figure 8. If the external frequency (fPLLIN) is greater than the oscillator frequency, fOSC, current is sourced continuously, pulling up the PLLFLTR pin. When the external frequency is less than fOSC, current is sunk continuously, pulling down the PLLFLTR pin. If the external and internal frequencies are the same, but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. Thus, the voltage on the PLLFLTR pin is adjusted until the phase and frequency of the external and internal oscillators are identical. At this U EXTERNAL OSC PHASE DETECTOR/ OSCILLATOR 2.4V RLP 10k CLP PLLFLTR FCB/SYNC DIGITAL PHASE/ FREQUENCY DETECTOR OSC 3738 F08 W UU Figure 8. Phase-Locked Loop Block Diagram stable operating point, the phase comparator output is open and the filter capacitor CLP holds the voltage. The IC FCB/SYNC pin must be driven from a low impedance source such as a logic gate located close to the pin. When using multiple ICs for a phase-locked system, the PLLFLTR pin of the master oscillator should be biased at a voltage that will guarantee the slave oscillator(s) ability to lock onto the master’s frequency. A voltage of 1.7V or below applied to the master oscillator’s PLLFLTR pin is recommended in order to meet this requirement. The resultant operating frequency will be approximately 500kHz for 1.7V. The loop filter components (CLP, RLP) smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. The filter components CLP and RLP determine how fast the loop acquires lock. Typically RLP =10k and CLP ranges from 0.01µF to 0.1µF. Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest time duration that the IC is capable of turning on the top MOSFET. It is determined by internal timing delays and the gate charge of the top MOSFET. Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT VIN ( f) 3738f 23 LTC3738 APPLICATIO S I FOR ATIO If the duty cycle falls below what can be accommodated by the minimum on-time, the IC will begin to skip every other cycle, resulting in half-frequency operation. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. The minimum on-time for the IC is generally about 120ns. However, as the peak sense voltage decreases the minimum on-time gradually increases. This is of particular concern in forced continuous applications with low ripple current at light loads. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. If an application can operate close to the minimum ontime limit, an inductor must be chosen that is low enough in value to provide sufficient ripple amplitude to meet the minimum on-time requirement. As a general rule, keep the inductor ripple current equal to or greater than 30% of IOUT(MAX) at VIN(MAX). Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD • ESR, where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery 24 U time, VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior, but also provides a DC coupled and AC filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the Figure 1 circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.2 to 5 times their suggested values) to maximize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 80% of full load current having a rise time of 1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can 3738f W UU LTC3738 APPLICATIO S I FOR ATIO alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If CLOAD is greater than 2% of COUT , the switch rise time should be controlled so that the load rise time is limited to approximately 1000 • RSENSE • CLOAD. Thus a 250µF capacitor and a 2mΩ RSENSE resistor would require a 500µs rise time, limiting the charging current to about 1A. Design Example (Using Three Phases) As a design example, assume VIN = 12V(nominal), VIN = 20V(max), VOUT = 1.3V, IMAX = 45A, f = 400kHz and the AVP slope is 1mV/A. The inductance value is chosen first based upon a 30% ripple current assumption. The highest value of ripple current in each output stage occurs at the maximum input voltage. L= = VOUT ⎛ VOUT ⎞ ⎜ 1− ⎟ f( ∆I) ⎝ VIN ⎠ 1.3V ⎛ 1.3V ⎞ ⎜ 1− ⎟ (400kHz)(30%)(15A) ⎝ 20V ⎠ ≥ 0.68µH Using L = 0.6µH, a commonly available value results in 34% ripple current. The worst-case output ripple for the three stages operating in parallel will be less than 11% of the peak output current. RSENSE1, RSENSE2 and RSENSE3 can be calculated by using a conservative maximum sense current threshold of 65mV and taking into account half of the ripple current: 65mV RSENSE = = 0.0037Ω ⎛ 34%⎞ 15A⎜ 1 + ⎟ ⎝ 2⎠ Use a commonly available 0.003Ω sense resistor. Take RAVP as recommended value 100Ω, the RPREAVP is: RPREAVP = 0.003Ω 100Ω = 300Ω 1mV/A U Next verify the minimum on-time is not violated. The minimum on-time occurs at maximum VCC: W UU tON(MIN) = VOUT VIN(MAX) ( f) = 1.3V = 162ns 20 V(400kHz) The output voltage will be set by the VID code according to Table 1. The power dissipation on the topside MOSFET can be estimated. Using a Siliconix Si7390DP for example, RDS(ON) = 13.5mΩ, CMILLER = 2.1nC/15V = 140pF. At maximum input voltage with T(estimated) = 50°C: PMAIN ≈ 1.3V (15)2 1+ (0.005)(50°C − 25°C) 20 V 2 ⎛ 45A ⎞ 0.0135Ω + (20) ⎜ ⎟ (2Ω)(140pF ) ⎝ (2)(3) ⎠ [ ] 1 1⎞ ⎛ + ⎜ ⎟ (400kHz) = 0.51W ⎝ 5V – 1.8 V 1.8 V ⎠ using a Siliconix Si7356DP as bottom side MOSFET. The worst-case power dissipation by the synchronous MOSFET under normal operating conditions at elevated ambient temperature and estimated 50°C junction temperature rise is: 20 V − 1.3V (15A)2 (1.25)(0.004Ω) = 1.05W 20 V A short circuit to ground will result in a folded back current of: PSYNC = ISC ≈ 25mV 1 ⎛ 150ns(20 V ) ⎞ +⎜ = 7.5A (2 + 3)mΩ 2 ⎝ 0.6µH ⎟ ⎠ with a typical value of RDS(ON) and d = (0.005/°C)(50°C) = 0.25. The resulting power dissipated in the bottom MOSFET is: PSYNC = (7.5A)2(1.25)(0.004Ω) ≈ 0.28W which is less than one third of the normal, full load conditions. Incidentally, since the load no longer dissipates any power, total system power is decreased by over 90%. Therefore, the system actually cools significantly during a shorted condition! 3738f 25 LTC3738 APPLICATIO S I FOR ATIO PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 9. Check the following in the PC layout: 1) Are the signal and power ground paths isolated? Keep the SGND at one end of a printed circuit path thus preventing MOSFET currents from traveling under the IC. The IC signal ground pin should be used to hook up all control circuitry on one side of the IC, routing the copper through SGND, under the IC covering the “shadow” of the package, connecting to the PGND pin and then continuing on to the (–) plates of CIN and COUT. The VCC decoupling capacitor should be placed immediately adjacent to the IC between the VCC pin and PGND. A 1µF ceramic capacitor of the X7R or X5R type is small enough to fit very close to the IC to minimize the ill effects of the large current pulses drawn to drive the bottom MOSFETs. An additional 5µF to 10uF of ceramic, tantalum or other very low ESR capacitance is recommended in order to keep the internal IC supply quiet. The power ground returns to the sources of the bottom N-channel MOSFETs, anodes of the Schottky diodes and (–) plates of CIN, which should have as short lead lengths as possible. 2) Does the IC IN+ pin connect to the (+) plates of COUT? A 30pF to 300pF feedforward capacitor between the DIFFOUT and EAIN pins should be placed as close as possible to the IC. 3) Are the SENSE– and SENSE+ printed circuit traces for each channel routed together with minimum PC trace spacing? The filter capacitors between SENSE+ and SENSE– for each channel should be as close as possible to the pins of the IC. Connect the SENSE– and SENSE+ pins to the pads of the sense resistor as illustrated in Figure 10. 4) Do the (+) plates of CIN connect to the drains of the topside MOSFETs as closely as possible? This capacitor provides the pulsed current to the MOSFETs. 5) Keep the switching nodes, SWITCH, BOOST and TG away from sensitive small-signal nodes. Ideally the SWITCH, BOOST and TG printed circuit traces should be routed away and separated from the IC and the “quiet” side of the IC. 26 U 6) The filter capacitors between the ITH and SGND pins should be as close as possible to the pins of the IC. Figure 9 illustrates all branch currents in a three-phase switching regulator. It becomes very clear after studying the current waveforms why it is critical to keep the high switching current paths to a small physical size. High electric and magnetic fields will radiate from these “loops” just as radio stations transmit signals. The output capacitor ground should return to the negative terminal of the input capacitor and not share a common ground path with any switched current paths. The left half of the circuit gives rise to the “noise” generated by a switching regulator. The ground terminations of the synchronous MOSFETs and Schottky diodes should return to the bottom plate(s) of the input capacitor(s) with a short isolated PC trace since very high switched currents are present. A separate isolated path from the bottom plate(s) of the input and output capacitor(s) should be used to tie in the IC power ground pin (PGND). This technique keeps inherent signals generated by high current pulses taking alternate current paths that have finite impedances during the total period of the switching regulator. External OPTI-LOOP compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure. Simplified Visual Explanation of How a 3-Phase Controller Reduces Both Input and Output RMS Ripple Current The effect of multiphase power supply design significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is divided by, and the effective ripple frequency is multiplied up by the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by, and the effective ripple frequency is increased by the number of phases used. Figure 11 graphically illustrates the principle. The worst-case input RMS ripple current for a single stage design peaks at twice the value of the output voltage. The worst-case input RMS ripple current for a two stage design results in peaks at 1/4 and 3/4 of the input voltage, 3738f W UU LTC3738 APPLICATIO S I FOR ATIO SW1 VIN SW2 RIN + CIN D2 COUT BOLD LINES INDICATE HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MININMUM LENGTH SW3 Figure 9. Branch Current Waveforms INDUCTOR LTC3738 SENSE+ SENSE– 1000pF Figure 10. Kelvin Sensing RSENSE 3738f U L1 RSENSE1 D1 L2 RSENSE2 VOUT W UU + RL L3 RSENSE3 D3 3738 F09 SENSE RESISTOR 3738 F10 OUTPUT CAPACITOR 27 LTC3738 APPLICATIO S I FOR ATIO SINGLE PHASE SW V ICIN ICOUT TRIPLE PHASE SW1 V SW2 V SW3 V IL1 IL2 IL3 ICIN ICOUT 3738 F11 Figure 11. Single and Polyphase Current Waveforms and the worst-case input RMS ripple current for a three stage design results in peaks at 1/6, 1/2, and 5/6 of the input voltage. The peaks, however, are at ever decreasing levels with the addition of more phases. A higher effective duty factor results because the duty factors “add” as long as the currents in each stage are balanced. Refer to AN19 for a detailed description of how to calculate RMS current for the single stage switching regulator. Figure 5 illustrates the RMS input current drawn from the input capacitance versus the duty cycle as determined by the ration of input and output voltage. The peak input RMS current level of the single phase system is reduced by 2/3 in a 3-phase solution due to the current splitting between the three stages. The output ripple current is reduced significantly when compared to the single phase solution using the same inductance value because the VOUT/L discharge currents term from the stages that has their bottom MOSFETs on 28 U subtract current from the (VCC – VOUT)/L charging current resulting from the stage which has its top MOSFET on. The output ripple current for a 3-phase design is: IP-P = VOUT (1– 3DC) VIN > 3VOUT ( f)(L) W UU The ripple frequency is also increased by three, further reducing the required output capacitance when VCC < 3VOUT as illustrated in Figure 3. Efficiency Calculation To estimate efficiency, the DC loss terms include the input and output capacitor ESR, each MOSFET RDS(ON), inductor resistance RL, the sense resistance RSENSE and the forward drop of the Schottky rectifier at the operating output current and temperature. Typical values for the design example given previously in this data sheet are: Main MOSFET RDS(ON) = 13.5mΩ (18mΩ at 90°C) Sync MOSFET RDS(ON) = 4mΩ (5.3mΩ at 90°C) CINESR = 20mΩ COUTESR = 3mΩ RL = 2mΩ RSENSE = 3mΩ VSCHOTTKY = 0.8V at 15A (0.7V at 90°C) VOUT = 1.3V VIN = 12V IMAX = 45A δ = 0.5%°C N=3 f = 400kHz The main MOSFET is on for the duty factor VOUT/VIN and the synchronous MOSFET is on for the rest of the period or simply (1 – VOUT/VIN). Assuming the ripple current is small, the AC loss in the inductor can be made small if a good quality inductor is chosen. The average current, IOUT is used to simplify the calaculations. The equation below is not exact but should provide a good technique for the comparison of selected components and give a 3738f LTC3738 APPLICATIO S I FOR ATIO result that is within 10% to 20% of the final application. The temperature of the MOSFET’s die temperature may require interative calculations if one is not familiar typical performance. A maximum operating junction temperature of 90° to 100°C for the MOSFETs is recommended for high reliability applications. Common output path DC loss: ⎛I ⎞ PCOMPATH ≈ N⎜ MAX ⎟ (RL + RSENSE ) + COUTESR Loss ⎝N⎠ 2 This totals 3.375W + COUTESR loss. Total of all three main MOSFET’s DC loss: ⎛ V ⎞⎛I ⎞ PMAIN = N⎜ OUT ⎟ ⎜ MAX ⎟ (1 + δ )RDS(ON) + CINESR Loss ⎝ VIN ⎠ ⎝ N ⎠ 2 This totals 1.3W + CINESR loss. Total of all three synchronous MOSFET’s DC loss: ⎛ V ⎞⎛I ⎞ PSYNC = N⎜ 1 – OUT ⎟ ⎜ MAX ⎟ (1 + δ )RDS(ON) ⎝N⎠ ⎝ VIN ⎠ This totals 3.2W. Total of all three main MOSFET’s AC loss: 45A PMAIN ≈ 3( VIN (2Ω)(140pF) (2)(3) 1 1⎞ ⎛ + ⎜ ⎟ (400kHz) = 6.3W ⎝ 5V – 1.8 V 1.8 V ⎠ )2 2 U This totals 0.14W at VIN = 8V, 0.315W at VIN = 12V and 0.875W at VIN = 20V. Total of all three synchronous MOSFET’s AC loss: (3)QG VIN VDSSPEC ( f) = (3)(16nC) VIN VDSSPEC (400kHz) W UU This totals 0.085W at VIN = 8V, 0.128W at VIN = 12V and 0.213W at VIN = 20V. The bottom MOSFET does not experience the Miller capacitance dissipation issue that the main switch does because the bottom switch turns on when its drain is close to ground. The Schottky rectifier loss assuming 50ns nonoverlap time: 2 • 3(0.7V)(15A)(50ns)(400kHz) This totals 1.26W. The total output power is (1.3V)(45A) = 58.5W and the total input power is approximately 67W so the % loss of each component is as follows: Main switch AC loss (VIN = 12V) Main switch DC loss Synchronous switch AC loss Synchronous switch DC loss Power path loss 0.315W 0.47% 1.3W 3.2W 1.9% 4.8% 0.128W 0.2% 3.375W 5.05% The numbers above represent the values at VIN = 12V. 3738f 29 LTC3738 TYPICAL APPLICATIO VID2 IN VCC 100pF 51k 10k RAVP 100Ω 30pF S1+ S1– S2+ S2 – ON/0FF OUTEN VID2 FCB/SYNC PLLFLTR IN– IN+ PGOOD VID0 IN VID1 IN VID5 IN VID1 VID0 VID5 PGOOD BOOST1 TG1 SW1 BOOST2 TG2 SW2 RPREAVP 220Ω 1000pF AVP EAIN SENSE1+ SENSE1– SENSE2+ SENSE2– SENSE3– SENSE3+ SS LTC3738 (EXPOSED PAD IS SGND) 10Ω ×6 1000pF S3– S3+ 1000pF TG3 ITH TSNS VR_HOTB VID3 VID4 BOOST3 VCC 2.2k 2200pF 200Ω VCC VID4 IN VID3 IN VCC 0.1µF 100pF VIN: 7V TO 21V VOUT: 0.8V TO 1.55V, 65A SWITCHING FREQUENCY: 300kHz CIN: SANYO OS-CON 25SP68M COUT: 330µF/2.5V × 10 SANYO POSCAP 2R5TPE330M9 D1 TO D3: MBRS340T3 VIN CLK 60° EAIN FCB/SYNC 3-PHASE LTC3738 3738 TA03 ITH 30 U 65A Power Supply for VRM10 47k 1Ω VCC 5V 0.1µF M1 VCC 0.1µF VIN M3 1µF 10µF L2 D2 S2+ S2– 0.002Ω 10µF 35V ×5 VIN L1 0.002Ω 10µF 6.3V ×3 VOUT + COUT M2 D1 S1+ S1– VCC BG1 PGND BG2 BG3 SW3 + M4 VIN CIN 7V TO 21V 68µF 25V VIN M5 0.1µF M6 D3 S3+ S3– L3 0.002Ω 3738 TA02 L1 TO L3: 0.6µH PULSE PG0006.601 OR TOKO FDA1055 0.56µH M1, M3, M5: Si7390DP × 1 OR HAT2168H × 1 M2, M4, M6: Si7356DP × 2 OR HAT2165H × 2 Block Diagram—6-Phase LTC3731/LTC3738 Supply 3-PHASE LTC3731 CLKOUT VOUT VRM9/VRM10 90A TO 120A 3738f LTC3738 PACKAGE DESCRIPTIO 5.50 ± 0.05 (2 SIDES) 4.10 ± 0.05 (2 SIDES) 3.20 ± 0.05 (2 SIDES) 5.00 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 7.00 ± 0.10 (2 SIDES) 0.75 ± 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U UHF Package 38-Lead Plastic QFN (7mm × 5mm) (Reference LTC DWG # 05-08-1701) 0.70 ± 0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 5.20 ± 0.05 (2 SIDES) 6.10 ± 0.05 (2 SIDES) 7.50 ± 0.05 (2 SIDES) RECOMMENDED SOLDER PAD LAYOUT 0.75 ± 0.05 0.00 – 0.05 3.15 ± 0.10 (2 SIDES) 0.435 0.18 0.18 37 38 1 2 0.23 5.15 ± 0.10 (2 SIDES) 0.40 ± 0.10 0.200 REF 0.25 ± 0.05 0.200 REF 0.00 – 0.05 0.50 BSC R = 0.115 TYP (UH) QFN 0303 BOTTOM VIEW—EXPOSED PAD 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3738f 31 LTC3738 RELATED PARTS PART NUMBER LTC1628/LTC1628-PG/ LTC1628-SYNC LTC1629/ LTC1629-PG LTC1702 LTC1703 LTC1708-PG LT®1709/ LT1709-8 LTC1735 LTC1736 LTC1778 LTC1929/ LTC1929-PG LTC3708 LTC3711 LTC3717 LTC3719 LTC3729 LTC3731 LTC3732 LTC3733 LTC3734 DESCRIPTION 2-Phase, Dual Output Synchronous Step-Down DC/DC Controllers 20A to 200A PolyPhase Synchronous Controllers No RSENSETM 2-Phase Dual Synchronous Step-Down Controller No RSENSE 2-Phase Dual Synchronous Step-Down Controller with 5-Bit Mobile VID Control 2-Phase, Dual Synchronous Controller with Mobile VID High Efficiency, 2-Phase Synchronous Step-Down Switching Regulators with 5-Bit VID High Efficiency Synchronous Step-Down Switching Regulator High Efficiency Synchronous Controller with 5-Bit Mobile VID Control No RSENSE Current Mode Synchronous Step-Down Controller 2-Phase Synchronous Controllers 2-Phase, Dual DC/DC Synchronous Buck Controller with Output Tracking No RSENSE Current Mode Synchronous Step-Down Controller with Digital 5-Bit Interface DDR/QDR Memory Termination Regulator 2-Phase, 5-Bit VID Current Mode, High Efficiency Synchronous Step-Down Controller 20A to 200A, 550kHz PolyPhase Synchronous Controller 3-Phase, 600kHz Synchronous Buck Switching Regulator Controller 3-Phase, 5-Bit VID, 600kHz Synchronous Buck Switching Regulator Controller 3-Phase, 5-Bit VID, 600kHz Synchronous Buck Switching Regulator Controller COMMENTS Reduces CIN and COUT, Power Good Output Signal, Synchronizable, 3.5V ≤ VIN ≤ 36V, IOUT up to 20A, 0.8V ≤ VOUT ≤ 5V Expandable from 2-Phase to 12-Phase, Uses All Surface Mount Components, No Heat Sink, VIN up to 36V 550kHz, No Sense Resistor Mobile Pentium® III Processors, 550kHz, VIN ≤ 7V 3.5V ≤ VIN ≤ 36V, VID Sets VOUT1, PGOOD 1.3V ≤ VOUT ≤ 3.5V, Current Mode Ensures Accurate Current Sharing, 3.5V ≤ VIN ≤ 36V Output Fault Protection, 16-Pin SSOP Output Fault Protection, 24-Pin SSOP, 3.5V ≤ VIN ≤ 36V Up to 97% Efficiency, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ (0.9)(VIN), IOUT up to 20A Up to 42A, Uses All Surface Mount Components, No Heat Sinks, 3.5V ≤ VIN ≤ 36V Tracks Two or More Supplies, Fast Transient Response, No RSENSE Up to 97% Efficiency, Ideal for Pentium III Processors, 0.925V ≤ VOUT ≤ 2V, 4V ≤ VIN ≤ 36V, IOUT up to 20A VOUT = 0.5VIN, ±20A, ±0.65% VOUT Accuracy AMD Hammer-K8 Processors, Wide VIN Range: 4V to 36V Operation Expandable from 2-Phase to 12-Phase, Uses all Surface Mount Components, VIN up to 36V Expandable from 3-Phase to 12-Phase, Uses all Surface Mount Components, VIN up to 36V VRM9.0 and VRM9.1 (VID = 1.1V to 1.85V) AMD OpteronTM (VID = 0.8V to 1.55V) Single Phase DC/DC Controller for Intel IMVP-4 6-Bit IMVP-4 VID: 0.7V ≤ VOUT ≤ 1.708V, 4V ≤ VIN ≤ 30V, IOUT ≤ 25A, Compatible Processors Lossless Voltage Positioning LTC3735 2-Phase DC/DC Controller for Pentium (Centrino) 40A, 0.7V ≤ VOUT ≤1.708V, 4V ≤ VIN ≤ 30V Processors No RSENSE is a trademark of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation. Opteron is a trademark of AMD Corporation. 3738f 32 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LT/TP 0604 1K • PRINTED IN USA www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004