TB62726AFG

TB62726ANG/AFG TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic TB62726ANG,TB62726AFG 16-bit Constant-Current LED Driver with Operating Voltage of 3.3-V and 5-V The TB62726A series are comprised of constant-current drivers designed for LEDs and LED displays. The output current value can be set using an external resistor. As a result, all outputs will have virtually the same current levels. This driver incorporates 16-bit constant-current outputs, a 16-bit shift register, a 16-bit latch and a 16-bit AND-gate circuit. These drivers have been designed using the Bi-CMOS process. This devices are a product for the Pb free. TB62726ANG Features • • • • • • • • • • • Output current capability and number of outputs: 90 mA × 16 outputs Constant current range: 2 to 90 mA Application output voltage: 0.7 V (output current 2 to 80 mA) 0.4 V (output current 2 to 40 mA) For anode-common LEDs Input signal voltage level: 3.3-V and 5-V CMOS level (Schmitt trigger input) Power supply voltage range VDD = 3.0 to 5.5 V Maximum output terminal voltage: 17 V Serial and parallel data transfer rate: 20 MHz (max, cascade connection) Operating temperature range Topr = −40 to 85°C Package: Type ANG: SDIP24-P-300-1.78 Type AFG: SSOP24-P-300-1.00B Current accuracy (All output ON) Output Voltage > 0.4 V = > 0.7 V = Current Accuracy Between Bits ±4% Between ICs ±15% ±12% 2 to 5 mA 5 to 80 mA Output Current TB62726AFG Weight SDIP24-P-300-1.78: 1.22 g (typ.) SSOP24-P-300-1.00B: 0.32 g (typ.) Company Headquarters 3 Northway Lane North Latham, New York 12110 Toll Free: 800.984.5337 Fax: 518.785.4725 Web: www.marktechopto.com | Email: info@marktechopto.com California Sales Office: 950 South Coast Drive, Suite 225 Costa Mesa, California 92626 Toll Free: 800.984.5337 Fax: 714.850.9314 TB62726ANG/AFG Pin Assignment (top view) GND SERIAL-IN CLOCK LATCH OUT0 VDD R-EXT SERIAL-OUT ENABLE OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 Warnings: Short-circuiting an output terminal to GND or to the power supply terminal may broken the device. Please take care when wiring the output terminals, the power supply terminal and the GND terminals. Block Diagram OUT0 OUT1 OUT15 R-EXT I-REG ENABLE Q ST LATCH D ST Q D ST Q D SERIAL-IN D CK Q D CK Q D CK Q SERIAL-OUT CLOCK Truth Table CLOCK LATCH H L H X X ENABLE L L L L H SERIAL-IN Dn Dn + 1 Dn + 2 Dn + 3 Dn + 3 OUT0 … OUT7 … OUT15 Dn … Dn − 7 … Dn − 15 No change Dn + 2 … Dn − 5 … Dn − 13 Dn + 2 … Dn − 5 … Dn − 13 OFF SERIAL-OUT Dn − 15 Dn − 14 Dn − 13 Dn − 13 Dn − 13 Note 1: OUT0 to OUT15 = On when Dn = H; OUT0 to OUT15 = Off when Dn = L. In order to ensure that the level of the power supply voltage is correct, an external resistor must be connected between R-EXT and GND. 2 2005-12-21 TB62726ANG/AFG Timing Diagram n=0 CLOCK 0V 3.3 V/5 V SERIAL-IN 0V 3.3 V/5 V LATCH 0V ENABLE 3.3 V/5 V 0V On 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 3.3 V/5 V OUT0 Off On OUT1 Off On OUT3 Off On OUT15 Off 3.3 V/5 V SERIAL-OUT 0V Warning: Latch circuit is leveled-latch circuit. Be careful because it is not triggered-latch circuit. Note 2: The latches circuit holds data by pulling the LATCH terminal Low. And, when LATCH terminal is a High level, latch circuit doesn’t hold data, and it passes from the input to the output. When ENABLE terminal is a Low level, output terminal OUT0 to OUT15 respond to the data, and on and off does. And, when ENABLE terminal is a High level, it offs with the output terminal regardless of the data. 3 2005-12-21 TB62726ANG/AFG Terminal Description Pin No. 1 2 3 4 5 to 20 Pin Name GND SERIAL-IN CLOCK LATCH GND terminal for control logic Input terminal for serial data for data shift register Input terminal for clock for data shift on rising edge Input terminal for data strobe When the LATCH input is driven High, data is not latched. When it is pulled Low, data is latched. Function OUT0 to OUT15 Constant-current output terminals Input terminal for output enable. All outputs ( OUT0 to OUT15 ) are turned off, when the ENABLE terminal is driven High. And are turned on, when the terminal is driven Low. Output terminal for serial data input on SERIAL-IN terminal Input terminal used to connect an external resistor. This regulated the output current. 3.3-V/5-V supply voltage terminal 21 ENABLE 22 23 24 SERIAL-OUT R-EXT VDD Equivalent Circuits for Inputs and Outputs 1. ENABLE terminal R (UP) VDD 2. LATCH terminal VDD LATCH ENABLE GND GND R (DOWN) 3. CLOCK, SERIAL-IN terminal VDD 4. SERIAL-OUT terminal VDD CLOCK, SERIAL-IN SERIAL-OUT Internal data GND GND 5. OUT0 to OUT15 terminals OUT0 to OUT15 Parasitic Diode GND 4 2005-12-21 TB62726ANG/AFG Maximum Ratings (Topr = 25°C) Characteristics Supply voltage Input voltage Output current Output voltage ANG-type (when not mounted) Power dissipation ANG-type (on PCB) (Note 3) AFG-type (when not mounted) AFG-type (on PCB) ANG-type (when not mounted) Thermal resistance ANG-type (on PCB) (Note 3) AFG-type (when not mounted) AFG-type (on PCB) Operating temperature Storage temperature Topr Tstg Symbol VDD VIN IOUT VOUT Pd1 1.78 W 0.83 Pd2 1.00 104 Rth (j-a) 1 70 °C/W 140 Rth (j-a) 2 120 Rating 6 Unit V V mA/ch V −0.2 to VDD + 0.2 +90 −0.2 to 17 1.25 −40 to 85 −55 to 150 °C °C Note 3: ANG-Type: Powers dissipation is derated by 14.28 mW/°C if device is mounted on PCB and ambient temperature is above 25°C. AFG-Type: Powers dissipation is derated by 6.67 mW/°C if device is mounted on PCB and ambient temperature is above 25°C. With device mounted on glass-epoxy PCB of less than 40% Cu and of dimensions 50 mm × 50 mm × 1.6 mm. Recommended Operating Conditions (Topr = −40°C to 85°C unless otherwise specified) Characteristics Supply voltage Output voltage Symbol VDD VOUT IOUT Output current IOH IOL VIH Input voltage VIL Clock frequency LATCH pulse width CLOCK pulse width ENABLE pulse width (Note 4) Set-up time for CLOCK terminal Hold time for CLOCK terminal Set-up time for LATCH terminal fCLK twLAT twCLK twENA tSETUP1 tHOLD tSETUP2 Cascade connected Each DC 1 circuit SERIAL-OUT SERIAL-OUT Conditions Min 3 Typ. Max 5.5 4 80 Unit V V mA/ch mA ⎯ ⎯ ⎯ 0.7 ⎯ 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.7 × VDD −1 1 VDD + 0.15 0.3 × VDD 20 ⎯ V −0.15 ⎯ 50 MHz ns ns ns ns ns ns ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Upper IOUT = 20 mA Lower IOUT = 20 mA 25 2000 3000 10 ⎯ 10 50 Note 4: When the pulse of the Low level is inputted to the ENABLE terminal held in the High level. 5 2005-12-21 TB62726ANG/AFG Electrical Characteristics (Topr = 25°C, VDD = 3.0 V to 5.5 V unless otherwise specified) Characteristics Supply voltage Symbol VDD IOUT1 IOUT2 Output current IOUT3 IOUT4 Conditions Normal operation VOUT = 0.4 V, VDD = 3.3 V VOUT = 0.4 V, VDD = 5 V VOUT = 0.7 V, VDD = 3.3 V VOUT = 0.7 V, VDD = 5 V VOUT ≥ 0.4 V, All outputs ON VOUT ≥ 0.4 V, All outputs ON VOUT = 15.0 V Min 3.0 31.96 REXT = 490 Ω 31. 59 63.63 REXT = 250 Ω 62.75 REXT = 490 Ω 71.30 79.95 35.90 72.30 40.20 mA 80.97 Typ. Max 5.5 40.54 Unit V ⎯ 36.20 ∆IOUT1 Output current error between bits ⎯ REXT = 250 Ω ±1 ±4 % ∆IOUT2 Output leakage current input voltage IOZ ⎯ ⎯ 0.7 VDD GND ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ −1 1 VDD µA Input voltage VIN V 0.3 VDD 0.3 0.3 V ⎯ VOL SOUT terminal voltage VOH Output current Supply voltage Regulation Pull-up resistor Pull-down resistor IOL = 1.0 mA, VDD = 3.3 V IOL = 1.0 mA, VDD = 5 V IOH = − 1.0 mA, VDD = 3.3 V IOH = 1.0 mA, VDD = 5 V When VDD is changed 3 V to 5.5 V ENABLE terminal LATCH terminal VOUT = 15.0 V VOUT = 15.0 V, All outputs OFF VOUT = 15.0 V, All outputs OFF VOUT = 0.7 V, All outputs ON REXT = OPEN REXT = 490 Ω REXT = 250 Ω REXT = 490 Ω ⎯ ⎯ 3 4.7 ⎯ ⎯ −5 %/VDD R (Up) R (Down) IDD (OFF) 1 IDD (OFF) 2 IDD (OFF) 3 ⎯ % 115 230 0.1 3.5 6 9 460 0.5 5 9 15 20 25 40 kΩ ⎯ 1 4 Supply current IDD (ON) 1 ⎯ ⎯ ⎯ ⎯ mA Same as the above, Topr = −40°C IDD (ON) 2 VOUT = 0.7 V, All outputs ON REXT = 250 Ω ⎯ 18 Same as the above, Topr = −40°C ⎯ 6 2005-12-21 TB62726ANG/AFG Switching Characteristics (Topr = 25°C unless otherwise specifed) Characteristics Symbol tpLH1 Conditions CLK- OUTn , LATCH = “H”, ENABLE = “L” Min Typ. Max Unit ⎯ ⎯ ⎯ 3 150 300 tpLH2 tpLH3 tpLH tpHL1 tpHL2 tpHL3 tpLH Output rise time Output fall time Maximum CLOCK rise time Maximum CLOCK fall time tor tof tr tf LATCH - OUTn , ENABLE = “L” ENABLE - OUTn , LATCH = “H” CLK-SERIAL OUT CLK- OUTn , LATCH = “H”, ENABLE = “L” LATCH - OUTn , ENABLE = “L” ENABLE - OUTn , LATCH = “H” CLK-SERIAL OUT 10 to 90% of voltage waveform 90 to 10% of voltage waveform When not on PCB (Note 5) 140 300 140 6 170 300 Propagation delay ⎯ 340 ns ⎯ ⎯ ⎯ 4 40 40 170 340 170 7 85 70 340 ⎯ 150 150 5 5 ns ns ⎯ ⎯ ⎯ ⎯ µs µs Conditions: (Refer to test circuit.) Topr = 25°C, VDD = VIH = 3.3 V and 5 V, VOUT = 0.7 V, VIL = 0 V, REXT = 490 Ω , VL = 3.0 V, RL = 60 Ω, CL = 10.5 pF Note 5: If the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to achieve the timing required for data transfer. Please consider the timings carefully. Test Circuit IDD VIH, VIL ENABLE CLOCK VDD RL OUT0 CL Function generator IOL LATCH SERIAL-IN SERIAL-OUT R-EXT GND CL Iref VL OUT15 Logic input waveform VDD = VIH = 3.3 V VIL = 0 V tr = tf = 10 ns (10% to 90%) 7 2005-12-21 TB62726ANG/AFG Timing Waveforms 1. CLOCK, SERIAL-IN, SERIAL-OUT twCLK CLOCK 50% tSETUP1 SERIAL-IN 50% tHOLD SERIAL-OUT 50% tpLH/tpHL 50% 50% 2. CLOCK, SERIAL-IN, LATCH , ENABLE , OUTn CLOCK 50% SERIAL-IN tSETUP2 LATCH 50% twLAT ENABLE tSETUP3 50% 50% twENA 50% OUTn tpHL1/LH1 tpHL2/LH2 50% tpHL3/LH3 3. OUTn 90% OUTn 10% tof 10% tor ON 90% OFF 8 2005-12-21 TB62726ANG/AFG Output Current – Duty (LEDS turn-on rate) IOUT – DUTY On PCB 100 100 IOUT – DUTY On PCB 80 80 (mA) 60 (mA) IOUT Topr = 25°C VDD = 3.3 V to 5.0 V VCE = 1.0 V Tj = 120°C (max) 60 IOUT 40 40 Topr = 55°C VDD = 3.3 V to 5.0 V VCE = 1.0 V Tj = 120°C (max) 0 0 20 40 60 20 20 TB62726AFG TB62726ANG TB62726AFG TB62726ANG 80 100 0 0 20 40 60 80 100 DUTY – Turn On Rate (%) DUTY – Turn On Rate (%) IOUT – DUTY On PCB 100 2.0 1.8 NG (On PCB) Pd – Topr (W/IC) PD 80 1.6 1.4 1.2 FG (On PCB) 1.0 0.8 0.6 0.4 0.2 (mA) 60 40 Topr = 85°C VDD = 3.3 V to 5.0 V VCE = 1.0 V Tj = 120°C (max) 0 0 20 40 60 20 TB62726AFG TB62726ANG 80 100 0 0 20 40 60 80 100 Power dissipation IOUT DUTY – Turn On Rate (%) Ambient temperature Ta (°C) Output Current – REXT Resistor IOUT – REXT 90 Theoretical value: 80 70 60 IOUT = (1.15 (V) ÷ R-EXT (Ω )) × 14.9 (mA) IOUT 50 40 Topr = 25°C 30 20 10 VCE = 0.7 V 0 100 500 1000 5000 10000 REXT (Ω) 9 2005-12-21 TB62726ANG/AFG Application Circuit (example 1): The general composition in static lighting of LED. More than VLED (V) ≥ Vf (total max) + 0.7 is recommended with the following application circuit with the LED power supply VLED. r1: The setup resistance for the setup of output current of every IC. r2: The variable resistance for the brightness control of every LED module. Example) TD62M8600F: 8-bit multi-chip PNP transistor array, which is not used in static lighting system. VLED SCAN O0 SERIAL-IN C.U. ENABLE LATCH CLOCK O1 O2 O13 O14 O15 SERIAL-IN SERIAL-OUT ENABLE LATCH O0 O1 O2 O13 O14 O15 SERIAL-OUT 16-bit SIPO, Latches and Constant-sink-current drivers 16-bit SIPO, Latches and Constant-sink-current drivers TB62726ANG/AFG CLOCK TB62726ANG/AFG r1 = 100 Ω (min) r2 r1 = 100 Ω (min) 10 2005-12-21 TB62726ANG/AFG Application Circuit (example 2): When the condition of VLED is VLED > 17 V The unnecessary voltage is one effective technique as to making the voltage descend with the zenor diode. Example) TD62M8600F: 8-bit multi-chip PNP transistor array, which is not used in static lighting system. VLED > 17 V SCAN O0 SERIAL-IN C.U. ENABLE LATCH CLOCK TB62726ANG/AFG 16-bit SIPO, Latches and Constant-sink-current drivers O1 O2 O13 O14 O15 SERIAL-IN SERIAL-OUT ENABLE LATCH CLOCK O0 O1 O2 O13 O14 O15 SERIAL-OUT 16-bit SIPO, Latches and Constant-sink-current drivers TB62726ANG/AFG r1 = 100 Ω (min) r2 r1 = 100 Ω (min) 11 2005-12-21 TB62726ANG/AFG Application Circuit (example 3): When the condition of VLED is Vf +0.7 < VLED < 17 V VOUT = VLED-Vf = 0.7 to 1.0 V is the most suitable for VOUT. Surplus VOUT causes an IC fever and the useless consumption electric power. It is the one way of being effective to build in the r3 in this problem. r3 can make a calculation to the formula r3 Ω = surplus VOUT/IOUT. Though the resistance parts increase, the fixed constant current performance is kept Example) TD62M8600F: 8-bit multi-chip PNP transistor array, which is not used in static lighting system. r3 r3 VLED = 15 V SCAN O0 SERIAL-IN C.U. ENABLE LATCH CLOCK O1 O2 O13 O14 O15 SERIAL-IN SERIAL-OUT LATCH O0 O1 O2 O13 O14 O15 SERIAL-OUT 16-bit SIPO, Latches and Constant-sink-current drivers 16-bit SIPO, Latches and Constant-sink-current drivers TB62726ANG/AFG CLOCK TB62726ANG/AFG r1 = 100 Ω (min) r2 r1 = 100 Ω (min) 12 2005-12-21 TB62726ANG/AFG Notes • Operation may become unstable due to the electromagnetic interference caused by the wiring and other phenomena. To counter this, it is recommended that the IC be situated as close as possible to the LED module. If overvoltage is caused by inductance between the LED and the output terminals, both the LED and the terminals may suffer damage as a result. There is only one GND terminal on this device when the inductance in the GND line and the resistor are large, the device may malfunction due to the GND noise when output switchings by the circuit board pattern and wiring. To achieve stable operation, it is necessary to connect a resistor between the REXT terminal and the GND line. Fluctuation in the output waveform is likely to occur when the GND line is unstable or when a capacitor (of more than 50 pF) is used. Therefore, take care when designing the circuit board pattern layout and the wiring from the controller. This application circuit is a reference example and is not guaranteed to work in all conditions. Be sure to check the operation of your circuits. This device does not include protection circuits for overvoltage, overcurrent or overtemperature. If protection is necessary, it must be incorporated into the control circuitry. The device is likely to be destroyed if a short-circuit occurs between either of the power supply pins and any of the output terminals when designing circuits, pay special attention to the positions of the output terminals and the power supply terminals (VDD and VLED), and to the design of the GND line. • • • • 13 2005-12-21 TB62726ANG/AFG Package Dimensions W eight: 1.22 g (typ.) 14 2005-12-21 TB62726ANG/AFG Package Dimensions W eight: 0.32 g (typ.) 15 2005-12-21 TB62726ANG/AFG Notes on Contents 1. Block Diagrams Some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory purposes. 2. Maximum Ratings The absolute maximum ratings of a semiconductor device are a set of specified parameter values that must not be exceeded during operation, even for an instant. If any of these ratings are exceeded during operation, the electrical characteristics of the device may be irreparably altered and the reliability and lifetime of the device can no longer be guaranteed. Moreover, any exceeding of the ratings during operation may cause breakdown, damage and/or degradation in other equipment. Applications using the device should be designed so that no maximum rating will ever be exceeded under any operating conditions. Before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in this document. 3. Recommended operating conditions The values of the conditions are applied within the range of the operating temperature and not guaranteed. 4. Test Circuits Components in test circuits are used only to obtain and confirm device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure in application equipment. 5. Graphics characteristics Graphics characteristics are reference ones and not guaranteed. 6. Timing Charts Timing charts may be simplified for explanatory purposes. 7. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 8. Application Circuits The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially in the phase of mass production design. In furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights. Handling of the IC Ensure that the product is installed correctly to prevent breakdown, damage and/or degradation in the product or equipment. 16 2005-12-21 TB62726ANG/AFG 17 2005-12-21