TB1311AFG
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB1311AFG
Audio SW, Video SW, Sync Separation and H/V Frequency Counter IC for TVs
The TB1311AFG includes audio and video SW blocks, prefilters for A/D converters, sync separators, and an H/V format detector for TV signals. The TB1311AFG contributes to a reduction in the proportion of the PCB occupied by LCR filters and to the simplification of designs on analog interfaces. 2 The TB1311AFG has an I CBUS interface through which various functions can be controlled.
P-QFP80-1420-0.80C
Weight: 1.6 g (typ.)
Features
Audio SW block ・ Audio (L/R) inputs ・ Audio (L/R) output: 3 channels Audio block ・ Attenuator Video SW block ・ CVBS inputs ・ Y/C inputs ・ Component video inputs (co-use as RGB inputs) ・ SCART inputs ・ Output: 2 channels ・ Monitor output Video block ・ Gain switching: -3 dB / 0 dB / +3 dB ・ Bandwidth filter: prefilter for ADC; 4.5 to 46 MHz variable Sync separation block ・ Supports 525/30p/60i/60p, 625/50i/50p, 750/50p/60p, 1125/24p/24sf/25p/30p/50i/60i/50p/60p, 1250/50i, VGA @60, SVGA@60, XGA@60, SXGA@60, UXGA@60 ・ HD/VD input: 1 channel; positive and negative input acceptable ・ HD/VD output: positive and negative output selectable ・ Masking pseudo-sync for the copyguard signal Others ・ Line detector for Japanese D-pin ・ S2, S1, insertion detection for S-pin ・ Horizontal and vertical frequency counter ・ Format detection circuit to input signal ・ No-input detection ・ Automatic sync process switching mode ・ Programmable number of audio/video inputs
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TB1311AFG
Block Diagram 1 (Simplified Overview)
This IC does not support weak signals, ghost signals or other nonstandard signals. Some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory purposes.
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TB1311AFG
Block Diagram 2 (Video Block)
Some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory purposes.
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Block Diagram 3 (Audio Block)
AR1 IN AL1 IN AR2 IN AL2 IN AR3 IN AL3 IN AR4 IN AL4 IN AR5 IN AL5 IN AR6 IN AL6 IN AR7 IN AL7 IN
35 37 42 43 52 54 56 58 62 63 72 74 76 78
ATT “AU1 ATT”
ATT
ATT
7
Total 0dB
AR1 OUT
ATT
“AU1 FIX”
ATT
5
ATT Total 0dB ATT “AU2 ATT”
AL1 OUT
ATT
20
ATT Total 0dB ATT “AU2 FIX”
AR2 OUT
ATT Total 0dB ATT
18
AL2 OUT
ATT
ATT
3
AR3 OUT
Other block
AR8 IN/DC1(S3) AL8 IN/DC2(S4) AR9 IN/DC4(LINE3-1) AL9 IN/DC5(LINE2-1) AR10 IN/DC9(LINE3-2) AL10 IN/DC10(LINE2-2)
39 40 46 48 66 68
ATT Other block ATT Other block ATT Other block ATT Other block ATT Other block ATT
1
AL3 OUT
“AU1 OUT”
“AU2 OUT”
Some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory purposes.
“AU3 OUT”
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Block Diagram 4 (Other Blocks)
This IC does not support weak signals, ghost signals or other nonstandard signals. Some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory purposes.
I2CBUS FREQ COUNTER
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Pin Assignment
CVBS5 IN AR2 IN AL2 IN FB1 IN/DC3(SW LINE1) Cr1/R1 IN AR9 IN/DC4(LINE3-1) Cb1/B1 IN AL9 IN/DC5(LINE2-1) Y1/G1 IN FB3 IN/DC6(LINE1-1) Cr3/R3 IN AR3 IN Cb3/B3 IN AL3 IN Y3/G3 IN AR4 IN SY1 IN AL4 IN SC1 IN DC7(S1) CVBS6 IN AR5 IN AL5 IN FB2 IN/ DC8(SW LINE2)
AU Vcc (9V) Cr2/R2 OUT FB2 OUT Cb2/B2 OUT AR2 OUT Y2/G2 OUT AL2 OUT CVBS2 OUT V/S GND SYNC2 IN SYNC FILTER VD OUT HD OUT V/S Vcc (5V) Cr1/R1 OUT FB1 OUT Cb1/B1 OUT AR1 OUT Y1/G1 OUT AL1 OUT CVBS1 OUT AR3 OUT MONITOR OUT AL3 OUT
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TB1311AFG
Pin Functions
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
Pin No. Pin Name Function Interface Circuit
11
3.3V
Input Signal/Output Signal
VCC pin for the logical circuits. 29 Vdd (3.3 V) Supply power through a resistor from pin 11 as in the Application Circuit. This pin voltage is clipped to 3.3 V (typ.) by the internal regulator.
29
500Ω
3.3 V (typ.)
27
27 11 16 24 32 36 38 41 61 57 77
Vss V/S VCC (5 V) V/S GND AU VCC (9 V) AU GND CVBS3 IN CVBS4 IN CVBS5 IN CVBS6 IN SY1 IN SY2 IN
GND pin for the logical circuits. VCC pin for the sync and video circuits. Connect 5.0 V (typ.) GND pin for the sync and video circuits. VCC pin for the audio circuits. Connect 9.0 V (typ.) GND pin for the audio circuits.
⎯ ⎯ ⎯ ⎯ ⎯
⎯ 5.0 V (typ.) ⎯ 9.0 V (typ.) ⎯
CVBS or Y input pin. Input the CVBS or Y signal in NTSC, PAL or SECAM via a clamp capacitor.
Sync tip level: 2.3 V (typ.) Y/CVBS signal amplitude: 1.0 Vp-p (with sync)
Chroma signal input pin. 59 79 SC1 IN SC2 IN
100.2kΩ
Input C signal via a capacitor. The voltage of this pin is detected and the 2 status is returned to the I CBUS Read functions, S4 or S8. It is used for detecting whether the S-pin is connected or not.
2.9 V bias (typ.) Burst signal amplitude: 0.3 Vp-p
1V
3V
11
100.2kΩ 200Ω
49 69 55 75
Y1/G1 IN Y2/G2 IN Y3/G3 IN Y4/G4 IN
Y, G or CVBS input pin. Input the signal via a clamp capacitor. The clamp system is selectable by CLAMP1, 2, 3 or 4 registers.
3V/1.5V
49 55 69 75
Sync tip level: 2.3 V (typ.)
200Ω
Bias level: 2.9 V (typ.) Y/G/CVBS signal amplitude: 1.0 Vp-p (with sync)
3V
16
47 67 53 73
Cb1/B1 IN
100.2kΩ
2.9 V bias (typ.) Cb, B or C input pin. Input the signal via a capacitor.
1V
Cb2/B2 IN Cb3/B3 IN Cb4/B4 IN
Cb/B signal amplitude: 0.7 Vp-p (without sync) Burst signal amplitude: 0.3 Vp-p
7
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Pin No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
2.9 V bias (typ.)
100.2kΩ
45 65
Cr1/R1 IN Cr2/R2 IN
Cr, R or C input pin. Input the signal via a capacitor.
1V
Cr/R signal amplitude: 0.7 Vp-p (without sync) Burst signal amplitude: 0.3 Vp-p
3V
11
Sync tip level: 2.3 V (typ.)
100.2kΩ 200Ω
Cr, R or CVBS input pin. 51 71 Cr3/R3 IN Cr4/R4 IN Input the signal via a capacitor. The clamp system is changed according to CbCr PIN3 or 4 registers.
51 71
3V/1.5V
Bias level: 2.9 V (typ.)
200Ω
Cr/R signal amplitude: 0.7 Vp-p (without sync) CVBS signal amplitude: 1.0 Vp-p (with sync)
16
3V
35 37 42 43 52 54 56 58 62 63 72 74 76 78
AR1 IN AL1 IN AR2 IN AL2 IN AR3 IN AL3 IN AR4 IN AL4 IN AR5 IN AL5 IN AR6 IN AL6 IN AR7 IN AL7 IN
39 40 46 48 66 68 24
200Ω 40kΩ
Audio input pin. Input the signal via a resistor and a capacitor. When the resistor value is 5.6 kΩ, the internal gain becomes 0 dB (typ.).
35 37 42 43 52 54 56
58 62 63 72 74 76 78
24
4.5V 47kΩ
1pF
40.2kΩ
Bias level: 4.4 V (typ.) Audio input: 2.8 Ｖp-p (100%)
32
Audio or DC voltage input pin. 39 40 46 48 66 68 AR8 IN/DC1 AL8 IN/DC2 AR9 IN/DC4 AL9 IN/DC5 AR10 IN/DC9 AL10 IN/DC10 The input type is changed by AU8 PIN, AU9 PIN or AU10 PIN. In the case of use as audio input, input the signal via a resistor and a capacitor. When the resistor value is 5.6 kΩ, the internal gain becomes 0 dB (typ.). In the case of use as DC voltage input, input the signal via a resistor for protection.
76kΩ
32 11
Bias level: 4.4 V (typ.) Audio input: 2.8 Ｖp-p (100%)
Th1
Th2
16
44 64 50 70
FB1 IN/DC3 FB2 IN/DC8 FB3 IN/DC6 FB4 IN/DC11
In the case of use as DC voltage input, input the signal via a resistor for protection.
3.25kΩ
FB (Fast Blanking) signal or DC voltage input pin. Connect a resistor between this pin and GND.
FB input:
1V
DC voltage input.
1kΩ
60 80
DC7 DC12
Input the signal via a resistor for protection purposes. This pin is also used as a test signal output pin for shipping only.
3V
DC
1V 3V
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Pin No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal Sync tip level: 1.8 V (typ.)
Composite SYNC input pin to separate into H- and V-SYNC. 33 15 SYNC1 IN SYNC2 IN Input the signal via a clamp capacitor. Remark: SYNC1 IN is not available, when A-SYNC = 1 (ON). or
1Vp-p
HD or VD input pin. 31 30 HD IN VD IN The polarity of the input signal is detected and its leading edge becomes a timing trigger. 4 6 8 10 17 19 21 23 5 7 18 20 1 3 CVBS1 OUT Y1/G1 OUT Cb1/B1 OUT Cr1/R1 OUT CVBS2 OUT Y2/G2 OUT Cb2/B2 OUT Cr2/R2 OUT AL1 OUT AR1 OUT AL2 OUT AR2 OUT AL3 OUT AR3 OUT Video signal output pin for a monitor output. 2 MONITOR OUT Refer to Bus Control Functions for details of the output from the pin. Audio signal output pin. Refer to Bus Control Functions for details of the output from each pin.
1 3 5 7 18 20 32 11 24 11 4 6 8 10 17 19 21 23
1.45 V bias (typ.)
Input a separated horizontal or vertical sync signal (1.0 to 2.0 Vp-p) via a resistor and a coupling capacitor.
or
Video signal output pin. Refer to Bus Control Functions for details of the output from each pin.
100Ω
AC: -3, 0 or +3 dB (typ.)
16
AC: +6 dB (typ.)
2 34
Video signal output pin for the sync separation circuit. 34 Yvi OUT Refer to Bus Control Functions for details of the output from the pin. AC: 0 dB (typ.)
16
HD or VD output pin. 12 13 HD OUT VD OUT The tailing edge of the VD-OUT has a jitter. Use the leading edge only.
9 12 13 22
The polarity of the output is selectable by HV-POL register.
11
or
FB output pin. 9 22 FB1 OUT FB2 OUT Note: If necessary, a resistor can be added between the pin and GND to improve the transient of the falling edge. The value of the resistor must be 440 Ω or more. However, when the resistor is added, the leak pulse from FB edges to video signals is also increased.
100Ω
16
A filter pin for sync detection. 14 SYNC FILTER Connect a capacitor between this pin and GND. ⎯
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Pin No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
Crystal connection pin. 28 XTAL Connect a 3.579545 MHz crystal for NTSC demodulation to generate internal clocks. ⎯
11
25
SDA
SDA pin for I2CBUS.
25
5kΩ 50Ω ACK
H to L: 1.3 V (typ.) L to H: 2.1 V (typ.)
27 11
26
SCL
SCL pin for I2CBUS.
26
5kΩ
H to L: 1.3 V (typ.) L to H: 2.1 V (typ.)
27
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BUS Control Map
Write Mode
SA 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 (0)TEST1 AU1 FIX AU2 FIX AU10 PIN AU9 PIN AU8 PIN HV-SEP1 (0) V-DET FB2 PIN-M (0) (0) HD WIDTH HV POL (0) HV FREQ2 H COUNT MIN SIG RESET N SIG SW SIG DET IMPE SIG DET LVL (0) (0) (0) (0) f0 SW1 f0 SW2 CVBS2 GAIN CbCr PIN4 FB2 DL CbCr PIN3 FB2 MUTE AU2 OUT AU1 ATT AU2 ATT AU3 OUT SYNC LPF2 SYNC LPF1 Yvi OUT HV DET HV OUT YCbCr2 GAIN CbCr PIN2 CbCr PIN1 D7
Slave Address: DEH
D6 CVBS1OUT CVBS2OUT FILPASS2 FILPASS1 D5 D4 fc HALF1 fc HALF2 YC MIX BANDWIDTH1 BANDWIDTH2 CVBS1 GAIN CLAMP4 FB1 DL CLAMP3 FB1 MUTE AU1 OUT YCbCr1 GAIN CLAMP2 CLAMP1 D3 D2 D1 D0 PRESET 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00010001 00000000 00000000 00000001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 YCbCr1OUT YCbCr2OUT MON OUT
FB2 OUT
FB1 OUT
HV-SEP2 A-SYNC (0) H DMY SIG LPF PS MASK V DMY
H COUNT MAX SIG DET N FB2 PIN-L SIG RESET
(00000000) TEST2 (00000000) TEST3
Remark: SA = Sub-address. NOTE: Set 0 (zero) on bits written as (0).
Read Mode
D7 0 1 2 3 4 5 6 7 8 S8 FB DET2 DC4 DC8 POR
Slave Address: DFH
D6 H FM2 D5 V FM2 D4 H IN D3 V IN D2 V-SYNC-W V FORMAT HV-OUT FORMAT DC3 DC7 DC11 S7 S6 S5 S4 DC2 DC6 DC10 S3 S2 DC1 DC5 DC9 S1 D1 HD-POL D0 VD-POL ∗
H FORMAT FB DET1 SIG DET
DC12
H FREQ DET V FREQ DET
∗: Undefined
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Bus Control Functions
Write Mode
Register Name Function Selects the output from CVBS1(2) OUT (pin 4 (17)) for SCART connector. CVBS1(2)OUT 000: Mute 001: Outputs the same Y, selected by YCbCr1(2) OUT 010: CVBS3 (pin 36) 011: CVBS4 (pin 38) 100: CVBS5 (pin 41) 101: CVBS6 (pin 61) 110: Cr3 (as CVBS) (pin 51) 111: Cr4 (as CVBS) (pin 71) Switches the frequency of bandwidth limit filters for Cb/Cr fc HALF1(2) The cutoff frequency of bandwidth limit filters for Cb/Cr is 1/2 to Y. (0) 0: OFF (same for 3 outputs) 1: ON (1/2 fc for Cb/Cr) Selects the output from Y/Cb/Cr OUT1(2) (pins 6, 8, 10 (19, 21, 23)). (Y OUT, Cb OUT, Cr OUT) = 0000: Mute (mute, mute, mute) 0001: SY1 (pin 57), SC1 (pin 59), mute 0010: SY2 (pin 77), SC2 (pin 79), mute 0011: CVBS3 (pin 36), mute, mute 0100: CVBS4 (pin 38), mute, mute 0101: CVBS5 (pin 41), mute (Cr1; pin 45, when CbCr PIN1 = 1), mute 0110: CVBS6 (pin 61), mute (Cr2; pin 65, when CbCr PIN2 = 1), mute 0111: Y1 (pin 49), Cb1 (pin 47), Cr1; pin 45 (mute, when CbCr PIN1 = 1) 1000: Y2 (pin 69), Cb2 (pin 67), Cr2; pin 65 (mute, when CbCr PIN2 = 1) 1001: Y3 (pin 55), Cb3 (pin 53), Cr3; pin 51 (mute, when CbCr PIN3 = 1) 1010: Y4 (pin 75), Cb4 (pin 73), Cr4; pin 71 (mute, when CbCr PIN4 = 1) 1011: Cr3 (as CVBS) (pin 51), mute, mute 1100: Cr4 (as CVBS) (pin 71), mute, mute 1101 to 1111: Not available Refer also to Function Descriptions. FILPASS1(2) Switches the bandwidth limit filter 1 (2). 0: OFF (filters active) YC MIX 1: ON (bypass) OFF (0) OFF (0) Mute (000) Preset Value
OFF
Mute (0000)
YCbCr1(2)OUT
Mixes Y with C for MONITOR OUT (pin 2). 0: OFF (for CVBS) 1: MIX (Y+C)
Selects the output from MONITOR OUT (pin 2). When YC MIX = 1, a mixed signal is output. 0000: Mute 0001: SY1 (pin 57) (+SC1 (pin 59)) 0010: SY2 (pin 77) (+SC2 (pin 79)) 0011: CVBS3 (pin 36) 0100: CVBS4 (pin 38) 0101: CVBS5 (pin 41) (+Cr1 (pin 45), when CbCr PIN1 = 1) 0110: CVBS6 (pin 61) (+Cr2 (pin 65), when CbCr PIN2 = 1) 0111: Y1 (pin 49) (+Cb1 (pin 47)) 1000: Y2 (pin 69) (+Cb2 (pin 67)) 1001: Y3 (pin 55) (+Cb3 (pin 53)) 1010: Y4 (pin 75) (+Cb4 (pin 73)) 1011: Cr3 (CVBS) (pin 51)) 1100: Cr4 (CVBS) (pin 71)) 1101 to 1111: Not available Refer also to Function Descriptions. Switches the f0 of the bandwidth limit filter for YCbCr(RGB) f0 SW1(2) 0: LOW 1: HIGH LOW (0)
Mute (0000)
MON OUT
Note: This function is not valid for the filter for CVBS. For the CVBS filter, this data is fixed to 0: LOW. Switches the f0 of the bandwidth limit filter for YCbCr(RGB) and CVBS BANDWIDTH1(2) 0000000: MIN (low) 1111111: MAX (high)
MIN （0000000）
Note: While HD, VD or FB-out is output, according as the f0 is set to lower, the crosstalk from HD, VD, FB or SYNC-in to video-outs becomes bigger.
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Register Name Switches output gain. CVBS1(2) GAIN Gain of CVBS1(2)-OUT output (pin 4 (17)) is controlled. 00: 0 dB Switches output gain. Gain of YCbCr1(2)-OUT outputs (pins 6,8,10 (19, 21, 23)) are controlled. YCbCr1(2) GAIN 00: 0 dB 01: -3 dB 10: +3 dB 11: Not available 0 dB (00) 01: -3 dB 10: +3 dB 11: Not available Function Preset Value 0 dB (00)
Remark: GAIN = 01 (-3 dB) is recommended for the 1125/50p/60p format since this offers superior frequency characteristics to those of other modes. Changes CbCr1-IN pins function. CbCr PIN1 0: Component Cb/Cr input (pin 49: Y/G, pin 47: Cb/B, pin 45: Cr/R, pin 41: CVBS) 1: Separated C input (pin 49: Y, pin 47: C, pin 41: Y, pin 45: C) Changes CbCr2-IN pins function. CbCr PIN2 0: Component Cb/Cr input (pin 69: Y/G, pin 67: Cb/B, pin 65: Cr/R, pin 61: CVBS) 1: Separated C input (pin 69: Y, pin 67: C, pin 61: Y, pin 65: C) Changes CbCr3-IN pins function. CbCr PIN3 0: Component Cb/Cr input (pin 55: Y/G, pin 53: Cb/B, pin 51: Cr/R) 1: Separated C input (pin 55: Y, pin 53: C, pin 51: CVBS) Changes CbCr4-IN pins function. CbCr PIN4 0: Component Cb/Cr input (pin 75: Y/G, pin 73: Cb/B, pin 71: Cr/R) 1: Separated C input (pin 75: Y, pin 73: C, pin 71: CVBS) Switches Y1 (2, 3, 4) clamping mode. CLAMP1(2,3,4) The clamping mode for pin 49 (69, 55, 75) is set. 0: SYNC TIP CLAMP (for Y/G with sync) 1: BIAS (for RGB without sync) FB1(2) DL Turns on the delay to FB1 (2)-OUT (pin 9 (22)). 0: OFF Mutes FB1 (2)-OUT (pin 9 (22)). FB1(2) MUTE 0: OFF 1: MUTE (0) FB1 (00) Switches the output from FB1(2)-OUT (pin 9 (22)). FB1(2) OUT 00: FB1 (pin 44) 10: FB3 (pin 50) 01: FB2 (pin 64) 11: FB4 (pin 70) 1: ON (+30 ns) SYNC TIP (0) Cb/Cr input (0) Cb/Cr input (0) Cb/Cr input (0) Cb/Cr input (0)
OFF (0) OFF
Switches audio outputs from AL/AR1 (2,3)-OUT (pins 5/7 (18/20, 1/3)). 0000: MUTE 0010: AL/AR2 (pins 43/42) 0100: AL/AR4 (pins 58/56) 0110: AL/AR6 (pins 74/72) 1000: AL/AR8 (pins 40/39) 1010: AL/AR10 (pins 68/66) 0001: AL/AR1 (pins 37/35) 0011: AL/AR3 (pins 54/52) 0101: AL/AR5 (pins 63/62) 0111: AL/AR7 (pins 78/76) 1001: AL/AR9 (pins 48/46) 1011 to 1111: Not available AL/AR1 (0001)
AU1(2,3) OUT
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Register Name Function Sets audio volume to AL/AR1 (2)-OUT (pin 5/7 (18/20)) fixed. 0: Fixed gain (0 dB) AU1(2) FIX 1: OFF (Attenuated by AU1(2) ATT) Fixed (0) Preset Value
Note: The DC offset on audio outputs occurs when this function is turned on or off. While audio outputs are valid, switching of this function is not available. Remark: The gain is defined where the series-connected resistor is 5.6 kΩ. Attenuates audio volume to AL/AR1(2)-OUT (pins 5/7 (18/20)).
MIN （0000000） DC (0) DC (0) DC (0)
AU1(2) ATT 0000000: MIN Changes the AL/AR8-IN pin function. AU8 PIN 0: DC input for S-pin (pin 39: DC1(S3), pin 40: DC2(S4)) 1: Audio-IN8 (pin 39: AR8, pin 40: AL8) Changes the AL/AR9-IN pin function. AU9 PIN 0: DC input for D-pin (pin 46: DC4(LINE2), pin 48: DC5(LINE1)) 1: Audio-IN9 (pin 46: AR9, pin 48: AL9) Changes the AL/AR10-IN pin function. AU10 PIN 0: DC input for D-pin (pin 66: DC9(LINE2), pin 68: DC10(LINE1)) 1: Audio-IN10 (pin 66: AR10, pin 68: AL10) Switches the separation level. The H/V sync separation level to SYNC1(2)-IN (pin 33 (15)) is switched. HV-SEP1(2) 00: LOW 11: HIGH 1111111: MAX
LOW (00)
Remark: The separation level is changed according to a ratio of negative sync width per 1H period. Turns on the LPF for the sync-tip clamp. SYNC LPF1(2) SYNC LPF1(2) for SYNC1(2)-IN pin changes the speed of the sync-tip clamp response. Turn this function on for no-input detection. 0: OFF Automatic sync processing mode. Sync processing mode is changed in accordance with the results obtained by the internal format detection circuits. Format detection is performed for SYNC2-IN or HD/VD-IN signal selected by HV DET. The result of detection is returned to H FORMAT, V FORMAT, H FM2 and V FM2. HV FREQ setting is invalid when this mode is active. 0: OFF (Manual switching mode by HV FREQ2 setting) 1: ON Remark: SYNC1-IN (pin 33) is not available when A-SYNC = 1 (ON). Format detection and H/V separation are then executed for SYNC2-IN (pin 15). Turns on the LPF for the sync input pin (pin 33; SYNC1-IN). SIG LPF When no-input detection for weak strength signals is required, turn this function on to reduce noise on the input. Turn this function off for detections such as H FORMAT, V FORMAT, H FREQ DET and V FREQ DET. 0: OFF 1: ON OFF (0) 1: ON OFF (0)
A-SYNC
OFF (0)
Switches the output from Yvi-OUT (pin 34). 0000: MUTE 0010: SY2 (pin 77) 0100: CVBS4 (pin 38) 0110: CVBS6 (pin 61) 1000: Y2 (pin 69) 1010: Y4 (pin 75) 1100: Cr4 (as CVBS) (pin 71) 1101 to 1111: Not available 0001: SY1 (pin 57) 0011: CVBS3 (pin 36) 0101: CVBS5 (pin 41) 0111: Y1 (pin 49) 1001: Y3 (pin 55) 1011: Cr3 (as CVBS) (pin 51)
MUTE (0000)
Yvi OUT
Switches the mask mode for pseudo-sync. PS MASK 0: ON (Normal) 1: OFF (for “Sync on G”)
ON (0)
(1) OFF mode is used for “Sync on G” input.
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Register Name V-DET Function Switches the V format detection mode. 0: 50/60Hz only 1: Full detection Preset Value 50/60 only (0)
Switches the width of HD-OUT (pin 12) from SYNC2-IN (pin 15). 0: WIDE HD WIDTH 1: NARROW WIDE (0)
Remark: HD WIDTH = 1 (NARROW) is recommended for the 1125/50p/60p format owing to crosstalk from HD-OUT to video signals so that spike noises on video signals will occur. Switches the polarity of HD/VD output.
Positive (0) 1: Negative
HV-POL
The polarity of HD/VD OUT (pin 12, 13) is set. 0: Positive Selects the input for format detection.
HV DET
When A-SYNC = 0 (Manual Mode) 0: SYNC1-IN (pin 33) 1: HD/VD-IN (pins 31/30) When A-SYNC = 1 (Automatic Mode) This function is invalid. The input is selected by HV OUT.
SYNC (0)
HV OUT
Switches the outputs from HD/VD-OUT (pin 12/13). 0: SYNC2-IN (pin 15) Outputs the dummy HD at no input. The frequency of the dummy HD output depends on the HV FREQ2 setting (when A-SYNC = OFF) or HV-OUT FORMAT (when A-SYNC = ON). No-input detection is based on H IN result. 0: OFF 1: ON (Dummy HD output at no input) 1: HD/VD-IN (pins 31/30)
SYNC2-IN (0)
OFF (0)
H DMY
Note: The HD output does not synchronize with input sync, when A-SYNC = OFF and when a sync is input. Outputs the dummy VD at no input. The frequency of the dummy VD output depends on HV FREQ2 setting (when A-SYNC = OFF) or HV-OUT FORMAT (when A-SYNC = ON). No-input detection is based on the V IN result. 0: OFF 1: ON (Dummy VD output at no input)
OFF (0)
V DMY
Note: The VD output does not synchronize with input sync, when A-SYNC = OFF and when a sync is input. Changes FB2-OUT pin (pin 22) function. In FB2 PIN-M/L = ON, the level of pin 22 becomes HIGH when the Read registers below change. The level of pin 22 becomes LOW after the I2CBUS reading. The pin voltage is used for a sign to detect input signal changes for a microprocessor. For FB2 PIN-M/L = ON, set A-SYNC = 1 (ON) and FB2 MUTE = 1 (MUTE). FB2 PIN-M 0 FB2 PIN-M, L 0 1 1 FB2 PIN-L 0 1 0 1 Mode OFF (FB2-OUT) Mode 1 for no-input detection Mode 2 for format detection Not available OFF (00)
Referential Read registers for FB2 PIN-M/L = Mode 1: FB-DET1, SIG-DET Referential Read registers for FB2 PIN-M/L = Mode 2: H-FM2, V-FM2, H-IN, V-IN, HV-OUT FORMAT
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Register Name Input format setting. Set the horizontal and vertical mode according to the format that is input. When A-SYNC = ON mode, this setting is invalid. 00000: 15.625 kHz, 50 Hz (625i) 00001: 15.75 kHz, 60 Hz (525i) 00010: 31.25 kHz, 50 Hz (625p) 00011: 31.5 kHz, 60 Hz (525p, VGA @60 Hz) 00100: 28.125 kHz, 50 Hz (1125/50i) 00101: 33.75 kHz, 60 Hz (1125/60i) 00110: 37.5 kHz, 50 Hz (750/50p) 00111: 45 kHz, 60 Hz (750/60p, XGA @60 Hz) 01000: 31.25 kHz, 50 Hz (1250i) 01001: 37.9 kHz, 60 Hz (SVGA @60 Hz) 01010: 64 kHz, 60 Hz (1125/60p, SXGA @60 Hz) 01011: 75 kHz, 60 Hz (UXGA @60 Hz) 01100: 56.25 kHz, 50 Hz (1125/50p) 01101 to 01111: Not available 10000: 15.734 kHz, 30 Hz (525/30p) 10001: 27 kHz, 24 Hz (1125/24p) 10010: 28.125 kHz, 25 Hz (1125/25p) 10011: 33.75 kHz, 30 Hz (1125/30p) 10100: 27 kHz, 48 Hz (1125/24sf) 10101 to 11111: Not available Selects the H-sync count number for the higher threshold for the no-input detection. 0000: 32 counts H COUNT MIN 1111: 62 counts (2 counts / step) Function Preset Value
15.625 kHz, 50 Hz (00000)
HV FREQ2
H COUNT MAX
32 counts (0000) 16 counts (000) 1 count (0000)
Selects the H-sync count number for the lower threshold for the no-input detection. 000: 16 counts 111: 30 counts (2 counts / step)
SIG DET N
Selects the number of signal detections for the input existence threshold of the no-input detection. 0000: 1 count 0001: 2 counts to 1111: 30 counts (2 counts / step)
Selects the number of signal detection for input non-existence threshold of the no-input detection. SIG RESET N 0000: 1 count 0001: 2 counts to 1111: 30 counts (2 counts / step)
1 count (0000)
Resets the counter for no-input detection. Normal SIG RESET When 1 is sent, the counter for no-input detection is cleared at that time. 0: Normal SIG SW 1: Reset SYNC2-IN (0) (0)
Selects the input to the counter for no-input detection. 0: SYNC2-IN (pin 15) 1: SYNC1-IN (pin 33)
Changes the internal impedance for no-input detection. SIG DET IMPE The time constant of LPF for no-input detection is changed by this function and the capacitor value of SYNC FILTER (pin 14). 00: 20 kΩ 10: 10 kΩ 01: 15 kΩ 11: 6 kΩ 20 kΩ (00)
Changes the threshold for no-input detection. SIG DET LVL 00: 0.55 V 10: 1.05 V 01: 0.80 V 11: 1.30 V
0.55 V (00) all 0
TEST1,2,3
Test modes for shipping test. Set all zero.
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Read Mode
Register Name Power On Reset POR 0: Normal 1: Register preset Function
After power on, 1 is returned at first read. 0 is returned at second and subsequent reads. Horizontal format detection 2 H FM2 0: Known 1: Unknown
Detects whether an input is in one of the defined formats or not. This is based on H FORMAT data. Vertical format detection 2 V FM2 0: Known 1: Unknown
Detects whether an input is in one of the defined formats or not. This is based on V FORMAT data. Input detection to horizontal syncs H IN 0: No input V IN Input detection to vertical syncs 0: No input V-SYNC width detection 0: Wide V-SYNC-W 1: Narrow 1: Signal detected 1: Signal detected
Detects V-SYNC width for detecting 1250i format. Under A-SYNC = 1 (ON), V-SYNC-W shows 1 when VD width from VD-IN pin is narrower than approx 69 µs, or when V-SYNC width from SYNC-IN pin is narrower than approx 54 µs. Polarity detection to HD-IN
HD-POL
0: Positive
1: Negative
Detects the width from the HD-IN pin to determine whether it is negative or not. When the High level of the input is wider than approx 13.5 us, HD-POL shows 1. Polarity detection to VD-IN VD-POL 0: Positive 1: Negative
Detects the width from the VD-IN pin to determine whether it is negative or not. When the High level of the input is wider than approx 4.5 ms, VD-POL shows 1. Horizontal format detection H FORMAT 0000: 15.625/15.75 kHz 0001: 28.125 kHz 0010: 31.25/31.5 kHz 0100: 37.5/37.9 kHz 0101: 45/48 kHz 0110: 56.25 kHz 1000: 75 kHz 1001 to 1111: Undefined Detects a horizontal format (horizontal frequency). Vertical format detection V FORMAT 000: 50 Hz 100: 25 Hz 001: 60 Hz 101: 24 Hz 010: 48 Hz 110 to 111: Undefined 011: 30 Hz 0011: 33.75 kHz 0111: 64/67.5 kHz
Detects a vertical format (horizontal frequency) according to V FREQ DET data. Voltage detection of FB pin for SCART connector FB DET1(2) 0: Not always high 1: Always high
Detects the voltage of FB-IN pin, selected by FB1(2) OUT (to pin 9 (22)) to determine whether the voltage is always high or not. No-input detection. 0: No input SIG DET 1: A signal detected
The signal to the no-input detection circuit is selected by SIG SW. Refer to the relevant functions for H COUNT MAX, H COUNT MIN, SIG DET N, SIG RESET N, SIG RESET, SIG DET IMPE and SIG DET LVL.
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Register Name Function Format detection result. H and V dummy output frequencies depend on this result. 00000: 15.625 kHz, 50 Hz (625i) 00010: 31.25 kHz, 50 Hz (625p) 00100: 28.125 kHz, 50 Hz (1125/50i) 00110: 37.5 kHz, 50 Hz (750/50p) 01000: 31.25 kHz, 50 Hz (1250i) 01010: 64 kHz, 60 Hz (1125/60p, SXGA @60 Hz) 01100: 56.25 kHz, 50 Hz (1125/50p) 01101 to 01111: Not available 10000: 15.734 kHz, 30 Hz (525/30p) 10010: 28.125 kHz, 25 Hz (1125/25p) 10100: 27 kHz, 48 Hz (1125/24sf) 10101 to 11111: Not available DC voltage detection for D-pin or S-pin 00: Low (0 V) 01: Mid (2.2 V) 10: Undefined 11: High (5 V) 00001: 15.75 kHz, 60 Hz (525i) 00011: 31.5 kHz, 60 Hz (525p, VGA @60 Hz) 00101: 33.75 kHz, 60 Hz (1125/60i) 00111: 45 kHz, 60 Hz (750/60p, XGA @60 Hz) 01001: 37.9 kHz, 60 Hz (SVGA @60 Hz) 01011: 75 kHz, 60 Hz (UXGA @60 Hz) 10001: 27 kHz, 24 Hz (1125/24p) 10011: 33.75 kHz, 30 Hz (1125/30p)
HV-OUT FORMAT
Remark 1: See below for the relationship between this function number and the pin number. DC1 - pin 39, DC2 - pin 40, DC3 - pin 44, DC4 - pin 46, DC5 - pin 48, DC6 - pin 50, DC7 - pin 60, DC8 - pin 64, DC9 - pin 66, DC10 - pin 68, DC11 - pin 70, DC12 - pin 80 DC1 to 12 Remark 2; D-pin SW LINE: LINE1: LINE2: LINE3: 00: Connected 00: 525 (480) 00: Interlace 00: 4:3 01: ---01: 750 (720) 01: ---01: 4:3 letter box 01: 4:3 letter box 10: ---10: ---10: ---10: ---10: ---11: Not connected 11: 1125 (1080) 11: Progressive 11: 16:9 11: 16:9
Remark 3; about S-pin 00: 4:3
Detects whether S-pin is connected or not. 0: Low (not connected) S1 to 8 1: Open (connected)
Remark 1: An external circuit is necessary to use this function. Refer to the Function description. Remark 2: See below for the relationship between this function number and the pin number. S1 - pin 45, S2 - pin 47, S3 - pin 53, S4 - pin 59, S5 - pin 65, S6 - pin 67, S7 - pin 73, S8 - pin 79 Counts the vertical frequency of an input selected by SYNC SW. When V-DET = 0: 00000000: over 3.5 kHz 01001111: 44 Hz or less 01010000 to 11111111: No input When V-DET = 1: 00000000: over 3.5 kHz 10011001: 23 Hz or less 10011010 to 11111111: No input How to calculate a vertical frequency (Y): Convert data read from V FREQ DET into a decimal value and call it X. Vertical frequency (Y) = 1 ÷ (X × 2.8607 × 10-4) The error range of X is −1 to +1. Counts the horizontal frequency of an input selected by SYNC SW. When for SYNC-IN; 00000001: No input When for HD/VD-IN; 00000000: No input 11111111: over 85 kHz 11111111: over 85 kHz [Hz]
V FREQ DET
H FREQ DET
How to calculate a horizontal frequency (Y): Convert data read from H FREQ DET into a decimal value and call it X. Horizontal frequency (Y) = 1 ÷ (0.003 ÷ X) The error range of X is −1 to +1. [Hz]
Note 1: In determining the decision algorithms (detection range, detection times, and so on) for H/V frequency detection, it is necessary to take into account both previously mentioned cautions and other factors such as 2 signal conditions and I CBUS data transmission in the course of prototype TV set evaluation. Note 2: The READ BUS flags indicate that a certain signal is detected at a given moment. However, the detection result will not be very reliable if only one flag is checked. To obtain accuracy, it is recommended that a judgment should be made on the basis of confirming several times and verifying agreement among the majority of flags read in a sequence and/or at the same time.
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Function Descriptions
Output selections
Outputs are switched by I2CBUS registers, as in the following tables. YCbCr1 OUT
Register Settings YCbCr1 OUT CbCr PIN4CbCr PIN3 CbCr PIN2 CbCr PIN1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 to 1111 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 1 ∗ ∗ 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 1 ∗ ∗ 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ Y1/G1 OUT (Pin 6) Mute SY1 (pin 57) SY2 (pin 77) CVBS3 (pin 36) CVBS4 (pin 38) CVBS5 (pin 41) CVBS5 (pin 41) CVBS6 (pin 61) CVBS6 (pin 61) Y1 (pin 49) Y1 (pin 49) Y2 (pin 69) Y2 (pin 69) Y3 (pin 55) Y3 (pin 55) Y4 (pin 75) Y4 (pin 75) Cr3 (pin 51) Cr4 (pin 71) Outputs Cb1/B1 OUT (Pin 8) Mute SC1 (pin 59) SC2 (pin 79) Mute Mute Mute Cr1 (pin 45) Mute Cr2 (pin 65) Cb1 (pin 47) Cb1 (pin 47) Cb2 (pin 67) Cb2 (pin 67) Cb3 (pin 53) Cb3 (pin 53) Cb4 (pin 73) Cb4 (pin 73) Mute Mute Not available Cr1/R1 OUT (Pin 10) Mute Mute Mute Mute Mute Mute Mute Mute Mute Cr1 (pin 45) Mute Cr2 (pin 65) Mute Cr3 (pin 51) Mute Cr4 (pin 71) Mute Mute Mute y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y Available Input YCbCr CVBS YC RGB
∗: Don’t care YCbCr2 OUT
Register Settings YCbCr1 OUT CbCr PIN4 CbCr PIN3CbCr PIN2 CbCr PIN1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 to 1111 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 1 ∗ ∗ 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 1 ∗ ∗ 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ Y2/G2 OUT (Pin 19) Mute SY1 (pin 57) SY2 (pin 77) CVBS3 (pin 36) CVBS4 (pin 38) CVBS5 (pin 41) CVBS5 (pin 41) CVBS6 (pin 61) CVBS6 (pin 61) Y1 (pin 49) Y1 (pin 49) Y2 (pin 69) Y2 (pin 69) Y3 (pin 55) Y3 (pin 55) Y4 (pin 75) Y4 (pin 75) Cr3 (pin 51) Cr4 (pin 71) Outputs Cb2/B2 OUT (Pin 21) Mute SC1 (pin 59) SC2 (pin 79) Mute Mute Mute Cr1 (pin 45) Mute Cr2 (pin 65) Cb1 (pin 47) Cb1 (pin 47) Cb2 (pin 67) Cb2 (pin 67) Cb3 (pin 53) Cb3 (pin 53) Cb4 (pin 73) Cb4 (pin 73) Mute Mute Not available Cr2/R2 OUT (Pin 23) Mute Mute Mute Mute Mute Mute Mute Mute Mute Cr1 (pin 45) Mute Cr2 (pin 65) Mute Cr3 (pin 51) Mute Cr4 (pin 71) Mute Mute Mute y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y Available Input YCbCr CVBS YC RGB
∗: Don’t care
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MONITOR OUT
Register Settings MON OUT 0000 0001 0010 0011 0100 0101 YC MIX CbCr PIN4 CbCr PIN3 CbCr PIN2 CbCr PIN1 ∗ 0 1 0 1 ∗ ∗ ∗ 0 1 ∗ 0110 0 1 0111 1000 1001 1010 1011 1100 1101 to 1111 0 1 0 1 0 1 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 0 1 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ Outputs MONITOR OUT (Pin 2) Mute SY1 (pin 57) SY1 (pin 57) + SC1 (pin 59) SY2 (pin 77) SY2 (pin 77) + SC2 (pin 79) CVBS3 (pin 36) CVBS4 (pin 38) CVBS5 (pin 41) CVBS5 (pin 41) CVBS5 (pin 41) + Cr1 (pin 45) CVBS6 (pin 61) CVBS6 (pin 61) CVBS6 (pin 61) + Cr2 (pin 65) Y1 (pin 49) Y1 (pin 49) + Cb1 (pin 47) Y2 (pin 69) Y2 (pin 69) + Cb2 (pin 67) Y3 (pin 55) Y3 (pin 55) + Cb3 (pin 53) Y4 (pin 75) Y4 (pin 75) + Cb4 (pin 73) Cr3 (pin 51) Cr4 (pin 71) Not available Available Input CVBS YC
y y y y y y y y y y y y y y y y y y y y y y
∗: Don’t care
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TB1311AFG
Vertical sync separation for 1250i/50
When HV FREQ2 = 01000, the vertical sync separation for the 1250i/50 is accomplished through the use of a special circuit. The phase of the VD-out (pin 13) depends on the H-SYNC timing shown in the figure below. There is no VD-out when there is no H-SYNC input. In the manual sync processing mode (A-SYNC = OFF), use READ BUS functions, V-SYNC-W and H, V FORMAT (or H, V FREQ DET) to detect the 1250i/50. Note: The tailing edge of the VD-OUT has a jitter. Use the leading edge only.
HD width
HD-OUT width is selectable by HD WIDTH as below. A setting in which HD WIDTH = 1 (NARROW) is recommended for the 1125/50p/60p format owing to crosstalk from HD-OUT to video signals causing spike noise on video signals.
1125/60p signal SYNC-IN (Y-IN)
HD-OUT (HD WIDTH = 1)
0.7 s (typ.)
HD-OUT (HD WIDTH =0 ) 1.7 s (typ.)
HD/VD input amplitude
When a 5.6 kΩ is added before the input pin like the following figure, 5.0 Vp-p pulse input is allowed. However, the acceptable minimum amplitude then becomes 2.0 Vp-p.
Normal application
For large-input application
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Automatic sync processing mode (A-SYNC)
Counted horizontal and vertical frequency data to input signal are returned to READ BUS functions, H, V FREQ DET. Also, the detected format is returned to H, V FORMAT and H, V FM2 when the H/V frequencies are in internal defined ranges. Input detection results for H, V-SYNC or HD,VD, which indicate whether or not input exists, are returned to H,V IN. HV-OUT FORMAT indicates the active mode. In automatic sync processing mode (when A-SYNC = ON), this device operates as indicated in the following table according to these READ data. Then, the SYNC1-IN pin is not used for format detection. Input Condition Standard format Nonstandard format HV-OUT FORMAT, H, V FORMAT Status The format as input H, V FM2 Status Known H, V IN Status Signal HD, VD Outputs The separated sync as input
The status indicates not The separated sync as the current condition Unknown Signal input but the last detected format. Dummy HD and VD, of Known: The status indicates not which the frequency The status indicates not the current condition No input No input depends on the HV-OUT the current condition but but the last detected FORMAT status the last detected format. format. Note 3: Dummy HD and VD may become unstable while the mode is changing from one format to another.
Manual sync processing mode (A-SYNC = OFF)
In this mode, the SYNC1-IN pin is used only for detecting the input format and the SYNC2-IN pin is used only for separating H and V syncs for HD and VD outputs. It is possible to detect some input formats by means of time-sharing while separating syncs to another input. The following is an example of how to detect H/V frequency when A-SYNC = OFF. 1. Input the signal from Yvi-OUT pin into the SYNC1-IN pin. 2. Read data such as H, V FREQ DET and H, V FORMAT. 3. Detect the H/V frequency by microprocessor or similar means, depending on the data obtained. 4. Input the detected signal into the SYNC2-IN pin and set HV FREQ2 and so on for the SYNC2-IN pin to the detected mode. 5. Continue to monitor the obtained data for the SYNC1-IN pin, such as H, V FREQ DET and H, V FORMAT. When any alterations are recognized, re-set HV FREQ2 and so on for the SYNC2-IN pin. Decision algorithms (for detection range, detection times and so on) for H/V frequency detection should be determined taking into account the above-mentioned errors in measuring H/V frequencies and other factors such as signal conditions and I2CBUS data transmission in the course of prototype TV set evaluation. By the way, in A-SYNC = OFF and H, V DMY = ON mode, dummy HD and VD are output according to the HV FREQ2 setting when there is no input.
I2CBUS
Fig. Signal route when A-SYNC = ON
Fig. Signal route when A-SYNC = OFF
I2CBUS
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Sync separation level
The sync separation level is changed according to the ratio of H-sync width to one line. Typical sync separation levels for each format are as follows. HV-SEP data 625/50i 525/60i 625/50p 525/60p 1125/50i 1125/60i 750/50p 750/60p 1250/50i 1125/50p 1125/60p 525/30p 1125/24p 1125/25p 1125/30p 1125/24sf VGA/60 SVGA/60 XGA/60 SXGA/60 00 18 18 19 19 27 25 25 24 22 28 27 18 27 27 26 28 20 20 20 22 01 26 26 27 27 34 33 32 31 30 36 34 26 34 34 32 34 26 27 27 29 10 31 31 32 32 40 38 38 36 36 41 39 31 40 40 38 40 32 33 33 34 11 43 43 44 44 52 50 50 49 48 52 52 43 52 52 50 52 43 44 44 45
Expressed as percentages, where 286 mVp-p sync applies to 525/60i and 300 mVp-p sync applies otherwise The format detection and sync separation performances are changed due to the separation level set by HV-SEP setting and the connected coupling capacitor value. The careful evaluations are required to set the separation level under consideration of expected input conditions such as a suppressed sync input, an input with V-sag, and APL (Average Picture Level) fluctuations. For “Sync on G” signal, HD-OUT is not output during the V-sync period because there is no H-sync during the V-sync period.
(Note) Cross-talk from HD, VD, FB or SYNC-in to Video-outs
The edges of HD/VD/FB-out leaks into video-outs when HD-out, VD-out and/or FB-out is output. If the video-out is not synchronized with the HD/VD/FB-out, (e.g. desynchronized videos between main- and sub-picture like PinP or Double window), the edges looks as desynchronized noise. The crosstalk level will be improved when the BANDWIDTH frequency will be set to higher. Please use this device under consideration of the cross-talk.
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No-input detection
This function detects whether there is input or not. It is useful for detecting no-input of 525i or 625i even if which is a weakened signal strength. (1)0 (no-input) 1 (detected) When Nmin ≦ N1 ≦ Nmax, and when N2 ≧ Ndet, SIG DET returns 1. Where, Nmin: the number set by H COUNT MIN Nmax: the number set by H COUNT MAX Ndet: the number set by SIG DET N N1: the number of the H-sync count in the counter during an internal window (approx. 2 ms) N2: the number of conditions that “Nmin ≦ N1 ≦ Nmax” is detected (2) 1 (detected) 0 (no-input) When N1 ≦ Nmin, N1 ≧ Nmax, and when N3 ≧ Nreset, SIG DET returns 0. Where, Nreset: the number set by SIG RESET N N3: the number of conditions that “N1 ≦ Nmin and N1 ≧ Nmax” is detected
Fig. Block diagram for no-input detection Decide how to use no-input detection after making a thorough evaluation using a prototype TV set.
Ext. Cap.
SYNC FILTER pin
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S-pin insertion detection
C-IN pins detect the DC level to determine whether the S-pin is inserted or not.
Fig. Application of S-pin insertion detection
Audio gain
Audio gain is controlled by AU1(2) ATT. The following figure shows the typical characteristic, where the series-connected resistor is 5.6 kΩ.
20 0 Attenuation [dB] -20 -40 -60 -80 - 100 0 20 40 60 AU1(2) ATT data 80 100 120 127
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Typical characteristics
100 Fixed mode (AU FIX = 0) ATT mode (AU FIX = 1, AU ATT = max) Total harmonic distortion [%] 10
1
0 0.1
0.01 0 0.0 0.5 1.0 1.5 Input [Vrms] 2.0 2.5 3.0
Fig. Audio total harmonic distortion (input resistance: 5.6 kΩ)
10 0 -10 -20 -30 -40 -50 0.1 1 Frequency [MHz] 10 100
Gain [dB]
f0 SW = low, BANDWIDTH = min, fc HALF = on f0 SW = low, BANDWIDTH = min f0 SW = high, BANDWIDTH = min f0 SW = high, BANDWIDTH = max
Fig. Typical prefilter frequency characteristics
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50
Cutoff frequency (-3 dB point) [MHz]
40
fo fo fo fo
SW SW SW SW
= = = =
high low high, fc HALF = on low, fc HALF = on
30
20
10
0 0 20 40 60 BANDWIDTH data 80 100 120 127
Fig. Typical cutoff frequency (-3 dB point) characteristics of prefilter
250 fo fo fo fo SW SW SW SW = = = = high low high, fc HALF = on low, fc HALF = on
200 Delay time [ns]
150
100
50
0 0 20 40 60 BANDWIDTH data 80 100 120 127
Fig. Typical delay-time (group delay @ 1 MHz) characteristics of prefilter
Recommended crystal oscillator
When a connected crystal oscillator is used for the XO, the following oscillation specifications are required. Oscillation frequency (fundamental): 3.579545 MHz (for NTSC decoding) Frequency tolerance: +/- 50 ppm
External CW input into crystal oscillator pin
Instead of connecting a crystal oscillator, it is possible to input an external CW (Continual Wave) into pin 28 through a capacitor as below. The required specs on the CW are as follows. Input frequency (fundamental): 3.579545 MHz +/- 50 ppm Input amplitude: 1.0Vp-p +/- 0.5Vp-p
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How to deal with unused pins
Unused pins should be dealt with as below. Pins not mentioned below should be connected properly.
Pin No. 1 2 3 4 5 6 7 8 9 10 12 13 14 15 17 18 19 20 21 22 23 30 31 33 34 35 36 37 38 39 40 41 42 43 44 45 Pin Name AL3 OUT MONITOR OUT AR3 OUT CVBS1 OUT AL1 OUT Y1/G1 OUT AR1 OUT Cb1/B1 OUT FB1 OUT Cr1/R1 OUT HD OUT VD OUT SYNC FILTER SYNC2 IN CVBS2 OUT AL2 OUT Y2/G2 OUT AR2 OUT Cb2/B2 OUT FB2 OUT Cr2/R2 OUT VD IN HD IN SYNC1 IN Yvi OUT AR1 IN CVBS3 IN AL1 IN CVBS4 IN AR8 IN/DC1 AL8 IN/DC2 CVBS5 IN AR2 IN AL2 IN FB1 IN/DC3 Cr1/R1 IN Procedure Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 1 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 3 Procedure 4 Procedure 4 Procedure 1 Procedure 3 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 2 Procedure 1 Pin No. 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 ⎯ Pin Name AR9 IN/DC4 Cb1/B1 IN AL9 IN/DC5 Y1/G1 IN FB3 IN/DC6 Cr3/R3 IN AR3 IN Cb3/B3-IN AL3 IN Y3/G3 IN AR4 IN SY1 IN AL4 IN SC1 IN DC7 CVBS6 IN AR5 IN AL5 IN FB2 IN/DC8 Cr2/R2 IN AR10 IN/DC9 Cb2/B2 IN AL10 IN/DC10 Y2/G2 IN FB4 IN/DC11 Cr4/R4 IN AR6 IN Cb4/B4-IN AL6 IN Y4/G4 IN AR7 IN SY2 IN AL7 IN SC2 IN DC12 ⎯ Procedure Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 2 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 2 Procedure 1 Procedure 1 Procedure 1 Procedure 2 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 2 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 1 Procedure 2 ⎯
Procedure 1: Connect a 0.01 µF capacitor between this pin and GND. Procedure 2: Connect to GND. Procedure 3: Leave open. Procedure 4: Connect a 10 kΩ resistor between this pin and GND.
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How to start the I CBUS
After power on, send bus data as follows. Use software to handle the procedure. 1. Turn on the power. 2. Transmit all the write data.
2
How to transmit/receive via the I CBUS
Slave Address: DEH / DFH
A6 1 A5 1 A4 0 A3 1 A2 1 A1 1 A0 1 W/R 0/1
2
Start and Stop Conditions
SDA
SCL S Start condition P Stop condition
Bit Transmission
SDA
SCL
SDA must not be changed
SDA may be changed
Acknowledgement
SDA from transmitter SDA from receiver Low impedance at bit 9 only SCL from master S Clock pulse for acknowledgement 1 8 9
High impedance at bit 9
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Data Transmit Format 1
S Slave address 7-bit 0A Sub-address 8-bit A Transmit data 8-bit MSB P: End condition AP
MSB S: Start condition
MSB A: Acknowledgement
Data Transmit Format 2
S Slave address 0A Sub-address ･･････ A Transmit data 1 A A ･･････ AP
Sub-address
Transmit data n
Data Receive Format
S Slave address 7-bit MSB 1A Receive data 1 8-bit MSB ･････････ Receive data n AP
MSB
To receive data, the master transmitter changes to a receiver immediately after the first acknowledgement. The slave receiver changes to a transmitter. The end condition is always created by the master.
Optional Data Transmit Format (Automatic Increment Mode)
S Slave address 7-bit MSB 0A1 Sub-address 7-bit A Transmit data 1 8-bit MSB ････ Transmit data n 8-bit MSB AP
MSB
In this way, sub-addresses are automatically incremented from the specified sub-address and data are set.
I2CBUS Conditions
Parameter Low level input voltage High level input voltage Hysteresis of Schmitt trigger inputs Low level output voltage at 3 mA sink current Input current each I/O pin with an input voltage between 0.1 VDD and 0.9 VDD Capacitance for each I/O pin SCL clock frequency Hold time START condition Low period of SCL clock High period of SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Set-up time for STOP condition Bus free time between a STOP and START condition Symbol VIL VIH Vhys VOL1 Ii Ci fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Min 0 2.4 − 0 -10 − 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 Typ. − − 0.7 − − − − − − − − − − − − Max 1.1 V/S-Vcc − 0.4 10 10 400 − − − − − − − − Unit V V V V µA pF kHz µs µs µs µs ns ns µs µs
Note: This parameter is not tested during production and is provided only as information to assist the design of applications.
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TB1311AFG
Absolute Maximum Ratings (Ta = 25°C)
Characteristic 9 V Vcc Supply voltage 5 V Vcc 3.3 V Vcc Input pin voltage Y or Sync input amplitude (pin 15, 33, 36, 38, 41, 49, 51, 55, 57, 61, 69, 71, 75, 77) Power dissipation Power dissipation reduction rate Operating temperature Storage temperature Symbol VCCmax9 VCCmax5 VCCmax3 Vin Yin PD(Note 4) 1/θja Topr Tstg Rating 12.0 6.0 6.0 GND − 0.3 to Vcc + 0.3 2.0 2451 19.6 −20 to 75 −55 to 150 V Vp-p mW mW/°C °C °C V Unit
Note 4: Refer to the figure below. Note, however, that the condition applies only where the device is mounted on a board 114.3 x 76.2 x t:1.6 mm, Cu 20%. Mount the devive on a board which is larger than it.
2451
Power consumption reduction ratio PD (mW)
1471
0 0
25
75
150
Ambient temperature
Ta
(°C)
Figure PD - Ta Curve
Note 5: Install the product correctly. Otherwise, it may result in break down, damage and/or degration to the product or equipment. The absolute maximum ratings of a semiconductor device are a set of specified parameter values, which must not be exceeded during operation, even for an instant. If any of these rating would be exceeded during operation, the device electrical characteristics may be irreparably altered and the reliability and lifetime of the device can no longer be guaranteed. Moreover, these operations with exceeded ratings may cause break down, damage and/or degradation to any other equipment. Applications using the device should be designed such that each maximum rating will never be exceeded in any operating conditions. Before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in this documents.
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Operating conditions
Characteristic Pin 24 Supply voltage (VCC) Pin 11 Pin 29; Supply power from V/S Vcc (pin 11) via a resistor. Y/G signal input amplitude CVBS/SY input amplitude Y/G signal input frequency CVBS/SY input frequency SC (Chroma) signal input amplitude Cb, Cr, Pb, Pr signal input amplitude Cb, Cr, Pb, Pr signal input frequency R, G, B signal input amplitude R, G, B signal input frequency HD, VD signal input amplitude HD input frequency VD input frequency FB input level FB input width Pins 49, 55, 69, 75; with sync Pins 36, 38, 41, 49, 55, 57, 61, 69, 75, 77 (51, 71); with sync Pins 49, 55, 69, 75 Pins 36, 38, 41, 49, 55, 57, 61, 69, 75, 77 (51, 71) Pin 59, 79 (45, 47, 53, 65, 67, 73) Pins 45, 47, 51, 53, 65, 67, 71, 73; 100% color bar signal Pins 45, 47, 51, 53, 65, 67, 71, 73 Pins 45, 47, 49, 51, 53, 55, 65, 67, 69, 71, 73, 75; 100% white signal without sync Pins 45, 47, 49, 51, 53, 55, 65, 67, 69, 71, 73, 75 Pins 30, 31 Pins 31 for freq counter Pins 30 for freq counter Pins 44, 50, 64, 70 Pins 44, 50, 64, 70 H DC detection input voltage DC1 to 12 Pins 39, 40, 44, 46, 48, 50, 60, 64, 66, 68, 70, 80 M L S1 to 8 SDA input current Pins 45, 47, 53, 59, 65, 67, 73, 79 Pins 25 L H L Description Min 8.5 4.7 3.1 ⎯ ⎯ 0 0 ⎯ ⎯ 0 ⎯ 0 1.0 0 23 1.0 GND 80 3.5 1.4 GND GND ⎯ Typ. 9.0 5.0 3.3 1.0 1.0 ⎯ ⎯ ⎯ 0.7 ⎯ 0.7 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2.2 ⎯ ⎯ ⎯ Max 9.5 5.3 3.5 ⎯ ⎯ 60 8 2 ⎯ 60 ⎯ 60 2.0 85 3500 3.0 0.4 ⎯ V/S Vcc 2.4 0.6 0.6 3 V mA V ns Vp-p Vp-p MHz MHz Vp-p Vp-p MHz Vp-p MHz Vp-p kHz Hz V V Unit
Remark: Supply power to all Vcc pins (pin 11, 24, 29).
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TB1311AFG
Electrical Characteristics
(Unless otherwise specified, AU VCC = 9 V, V/S VCC = 5 V, Vdd = 3.3 V, Ta = 25°C, I2CBUS data: preset values)
Current Consumption (AU8/9/10 PIN = 1, f0 SW1/2 = 1, BANDWIDTH1/2 = max)
Pin Name AU VCC (pin 24) V/S VCC (pin 11) Vdd (pin 29) Symbol ICCAU ICCVS ICCD Test Conditions ⎯ ⎯ Resistance to 5 V; R = 180 Ω Min 7.5 100 6.3 Typ. 9.5 125 9.4 Max 12.5 165 12.8 mA Unit
Pin Voltage (test condition: no signal input)
Pin No. 1 2 3 4 5 6 7 8 10 14 15 17 18 19 20 21 23 28 30 31 33 34 35 36 37 38 39 40 Pin Name AL3 OUT MONITOR OUT AR3 OUT CVBS1 OUT AL1 OUT Y1/G1 OUT AR1 OUT Cb1/B1 OUT Cr1/R1 OUT SYNC FILTER SYNC2 IN CVBS2 OUT AL2 OUT Y2/G2 OUT AR2 OUT Cb2/B2 OUT Cr2/R2 OUT XTAL VD IN HD IN SYNC1 IN Yvi OUT AR1 IN CVBS3 IN AL1 IN CVBS4 IN AR8 IN/DC1 AL8 IN/DC2 Symbol V1 V2 V3 V4 V5 V6 V7 V8 V10 V14 V15 V17 V18 V19 V20 V21 V23 V28 V30 V31 V33 V34 V35 V36 V37 V38 V39 V40 Test Conditions − − − − − − − − − − − − − − − − − − − − − − − − − − − − Min 3.8 0.9 3.8 1.0 3.8 1.0 3.8 1.0 1.0 3.0 1.5 1.0 3.8 1.0 3.8 1.0 1.0 3.8 1.2 1.2 1.5 1.9 4.2 2.0 4.2 2.0 4.2 4.2 Typ. 4.1 1.2 4.1 1.3 4.1 1.3 4.1 1.3 1.3 3.3 1.8 1.3 4.1 1.3 4.1 1.3 1.3 4.05 1.45 1.45 1.8 2.2 4.4 2.3 4.4 2.3 4.4 4.4 Max 4.4 1.5 4.4 1.6 4.4 1.6 4.4 1.6 1.6 3.6 2.1 1.6 4.4 1.6 4.4 1.6 1.6 4.3 1.7 1.7 2.1 2.5 4.6 2.6 4.6 2.6 4.6 4.6 V Unit
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TB1311AFG
Pin No. 41 42 43 45 46 47 48 49 51 52 53 54 55 56 57 58 59 61 62 63 65 66 67 68 69 71 72 73 74 75 76 77 78 79
Pin Name CVBS5 IN AR2 IN AL2 IN Cr1/R1 IN AR9 IN/DC4 Cb1/B1 IN AL9 IN/DC5 Y1/G1 IN Cr3/R3 IN AR3 IN Cb3/B3 IN AL3 IN Y3/G3 IN AR4 IN SY1 IN AL4 IN SC1 IN CVBS6 IN AR5 IN AL5 IN Cr2/R2 IN AR10 IN/DC9 Cb2/B2 IN AL10 IN/DC10 Y2/G2 IN Cr4/R4 IN AR6 IN Cb4/B4 IN AL6 IN Y4/G4 IN AR7 IN SY2 IN AL7 IN SC2 IN
Symbol V41 V42 V43 V45 V46 V47 V48 V49 V51 V52 V53 V54 V55 V56 V57 V58 V59 V61 V62 V63 V65 V66 V67 V68 V69 V71 V72 V73 V74 V75 V76 V77 V78 V79
Test Conditions − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − − −
Min 2.0 4.2 4.2 2.6 4.2 2.6 4.2 2.0 2.6 4.2 2.6 4.2 2.0 4.2 2.0 4.2 2.6 2.0 4.2 4.2 2.6 4.2 2.6 4.2 2.0 2.6 4.2 2.6 4.2 2.0 4.2 2.0 4.2 2.6
Typ. 2.3 4.4 4.4 2.9 4.4 2.9 4.4 2.3 2.9 4.4 2.9 4.4 2.3 4.4 2.3 4.4 2.9 2.3 4.4 4.4 2.9 4.4 2.9 4.4 2.3 2.9 4.4 2.9 4.4 2.3 4.4 2.3 4.4 2.9
Max 2.6 4.6 4.6 3.2 4.6 3.2 4.6 2.6 3.2 4.6 3.2 4.6 2.6 4.6 2.6 4.6 3.2 2.6 4.6 4.6 3.2 4.6 3.2 4.6 2.6 3.2 4.6 3.2 4.6 2.6 4.6 2.6 4.6 3.2
Unit
V
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TB1311AFG
Audio Block
Characteristic I/O gain for Fixed mode (AL/AR1, AL/AR2, AL/AR3) I/O gain for ATT mode (AL/AR1, AL/AR2) AU ATT = min AU ATT = max Symbol Gauf Gaumin Gaumax fau thdf input = 2.8 Vp-p 1 kHz, Note A AU ATT = max thdmax Vdyau Vauswof Vattof Vrrr Gaumute Gaucrs Gausn Imau1 Input impedance of input pins Imau2 Imaudc Note A, Note B Offset on AU1(2,3) OUT between AU1(2,3) OUT = 0000 to 1010 Offset on AU1(2) OUT between AU1(2) ATT = max to min 100 Hz and 100 mVp-p ripple is added to AU Vcc, Note A Input = 2.8Vp-p, 1 kHz, Note A Input = 2.8Vp-p, 1 kHz, Note A Input = 2.8Vp-p, 1 kHz, Note A Pins 35, 37, 42, 43, 52, 54, 56, 58, 62, 63, 72, 74, 76, 78 AU8/9/10 = 1 (Audio input mode), Pins 39, 40, 46, 48, 66, 68 AU8/9/10 = 0 (DC input mode), Pins 39, 40, 46, 48, 66, 68 ⎯ 5.6 -30 -100 30 75 75 80 65 65 122 0.1 6.5 0 0 45 85 85 90 87 87 163 0.3 ⎯ 30 100 ⎯ ⎯ ⎯ ⎯ 109 109 204 kΩ Vp-p mV mV dB dB dB dB -3 dB point, Note A Input = 2.8 Vp-p, 1 kHz, input resistance 5.6 kΩ Test Conditions Min -1.0 ⎯ 0 100 ⎯ Typ 0 -90 1.0 ⎯ 0.02 Max 1.0 -80 2.0 ⎯ 0.05 % kHz dB Unit
I/O frequency characteristic Total harmonic distortion Fixed mode (AL/AR1, AL/AR2, AL/AR3) Total harmonic distortion for ATT mode (AL/AR1, AL/AR2) Input dynamic range Output offset voltage ATT Control offset Ripple rejection ratio Mute mode attenuation Crosstalk among inputs S/N ratio
Note A: This parameter is not tested during production and is provided only as information to assist the design of applications. Note B: Input = 1 kHz. The amplitude when the total harmonic distortion becomes 1%.
Video Block
Characteristic Sync-tip clamp mode Input dynamic range Bias mode Monitor out GAIN = -3 dB GAIN = 0 dB I/O gain GAIN = +3 dB GAIN = +6 dB Yvi-OUT Symbol Vdsync Vdbias Vdmoni G-3 G0 G+3 G+6 Gyvi Gycmy YC MIX gain Gycmc Test Conditions FILPASS = 0, BANDWIDTH = max, Sine wave input for Bias mode, Y with sync for others. Min 1.5 1.4 1.35 -3.5 -0.5 2.5 5.5 -0.5 5.5 5.5 Typ. 1.7 2.1 1.5 -3.0 0 3.0 6.0 0 6.0 6.0 Max ⎯ ⎯ ⎯ -2.5 0.5 3.5 6.5 0.5 6.5 dB 6.5 dB Vp-p Unit
CVBS-OUT, YCbCr-OUT FILPASS = 0/1, input = 0.2Vp-p 10 kHz, BANDWIDTH = cnt, f0 SW = 1 MONITOR OUT Yvi-OUT SY-IN to MONITOR-OUT, no input into SC-IN, YC MIX = 1 SC-IN to MONITOR-OUT, no input into SY-IN, YC MIX = 1
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Characteristic I/O frequency characteristic 1-1 (YCbCr) I/O frequency characteristic 1-2 (YCbCr) I/O frequency characteristic 1-3 (YCbCr) I/O frequency characteristic 1-4 (CbCr) I/O frequency characteristic 1-5 (CbCr) Differential 1-1 of frequency characteristic among YCbCr outputs Differential 1-2 of frequency characteristic among YCbCr outputs Differential 1-3 of frequency characteristic among YCbCr outputs I/O delay time 1-1 (YCbCr)
YCbCr GAIN = 0 dB YCbCr GAIN = +3 dB YCbCr GAIN = -3 dB YCbCr GAIN = 0 dB YCbCr GAIN = +3 dB
Symbol fg-3 fg0 fg+3 fLmax fLcnt fLmin fHmax fHcnt fHmin fhfLmax fhfLcnt fhfLmin fhfHmax fhfHcnt fhfHmin fdg-3 fdg0 fdg+3 fdHmax fdLcnt fdHmin fdHmax fdHcnt fdHmin TdL-3 TdL0 TdL+3 TdLmax TdLcnt TdLmin TdHmax TdHcnt TdHmin
Test Conditions
Min 80
Typ. 100 100 100 16.5 10.5 4.7 46 30.3 13.4 8.3 5.2 2.4 24.1 15.7 6.8 0 0 0 0 0 0 0 0 0 4 4 4 33 48 107 16 20 39
Max ⎯ ⎯ ⎯ 18.0 11.5 5.2 51 34 15 9.1 5.8 2.6 27 18 8.0 ⎯ ⎯ ⎯ 0.90 0.5 0.23 3.2 1.05 0.70 10 10 10 38 55 120 20 25 45
Unit
FILPASS = 1, 0.2 Vp-p input, -3 dB point, Note A
80 80 14.0
MHz
BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min
YCbCr GAIN = -3 dB YCbCr GAIN = 0 dB YCbCr GAIN = +3 dB
FILPASS = 0, GAIN = 00, f0 SW = 0, 0.2 Vp-p input, -3 dB point, Note A
9.5 4.2 41
MHz
FILPASS = 0, GAIN = 00, f0 SW = 1, 0.2 Vp-p input, -3 dB point, Note A
27 12 7.4
MHz
FILPASS = 0, GAIN = 00, f0 SW = 0, fc HALF = 1, -3 dB point, Note A
4.6 2.1
MHz
FILPASS = 0, GAIN = 00, f0 SW = 1, fc HALF = 1, 0.2 Vp-p input, -3 dB point, Note A
21 14 6.0 ⎯
MHz
FILPASS = 1, 0.2 Vp-p input, -3 dB point, Note A
⎯ ⎯ -0.90
MHz
BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min
YCbCr GAIN = -3 dB
FILPASS = 0, f0 SW = 0, 0.2 Vp-p input, -3 dB point, Note A
-0.5 -0.23 -3.2
MHz
FILPASS = 0, f0 SW = 1, 0.2 Vp-p input, -3 dB point, Note A
-1.05 -0.70 ⎯
MHz
FILPASS = 1, 1 MHz, Note A
⎯ ⎯ 28
ns
BANDWIDTH = max I/O delay time 1-2 (YCbCr) BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max I/O delay time 1-3 (YCbCr) BANDWIDTH = cnt BANDWIDTH = min
FILPASS = 0, GAIN = 00, f0 SW = 0, 1 MHz, Note A
45 96 10
ns
FILPASS = 0, GAIN = 00, f0 SW = 1, 1 MHz, Note A
15 35
ns
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TB1311AFG
Characteristic I/O delay time 1-4 (CbCr)
Symbol
Test Conditions
Min 55
Typ. 60 91 220 24 34 72 0 0 0 0 0 0 8 14 33 0 0 0 80 80 80 16.4 10.6 4.6 5 5 5 34 49 108 80 100 -70 -70 -60 3
Max 65 100 260 30 39 80 10 10 10 10 10 10 20 20 45 10 10 20 ⎯ ⎯ ⎯ 18.0 11.5 4.9 10 10 10 40 55 120 ⎯ ⎯ -60 -60
Unit
BANDWIDTH = max TdhfLmax BANDWIDTH = cnt BANDWIDTH = min TdhfLcnt TdhfLmin FILPASS = 0, GAIN = 00, f0 SW = 1, fc HALF = 1, 1 MHz, Note A FILPASS = 0, GAIN = 00, f0 SW = 0, fc HALF = 1, 1 MHz, Note A
80 190 20 29 66 -10
ns
BANDWIDTH = max TdhfHmax I/O delay time 1-5 (CbCr) BANDWIDTH = cnt BANDWIDTH = min Differential 1-1 of delay time among YCbCr outputs
YCbCr GAIN = -3 dB YCbCr GAIN = 0 dB YCbCr GAIN = +3 dB
TdhfHcnt TdhfHmin Tddg-3 Tddg0 Tddg+3 TddHmax TddHcnt TddHmin TddHmax TddHcnt TddHmin TddHmax TddHcnt TddHmin fg-3c fg0c fg+3c fmaxc fcntc fminc TdL-3 TdL0 TdL+3 Tdmaxc Tdcntc Tdminc fgm
ns
FILPASS = 1, 1 MHz, Note A
-10 -10 -10
ns
Differential 1-2 of delay time among YCbCr outputs Differential 1-3 of delay time between Y and Cb/Cr outputs Differential 1-4 of delay time between Cb and Cr outputs I/O frequency characteristic 2-1 (CVBS) I/O frequency characteristic 2-2 (CVBS)
BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min
CVBS GAIN = -3 dB CVBS GAIN = 0 dB CVBS GAIN = +3 dB
FILPASS = 0, f0 SW = 0, 1 MHz, Note A
-10 -10 0
ns
FILPASS = 0, f0 SW = 1, fc HALF = 1, 1 MHz, Note A
5 25 -10
ns
FILPASS = 0, f0 SW = 0, fc HALF = 1, 1 MHz, Note A
-10 -20 60
ns
FILPASS = 1, 0.2 Vp-p input, -3 dB point, Note A
60 60 14.0
MHz
BANDWIDTH = max BANDWIDTH = cnt BANDWIDTH = min
CVBS GAIN = -3 dB
FILPASS = 0, GAIN = 00, 0.2 Vp-p input, -3 dB point, Note A
9.5 4.1 ⎯
MHz
I/O delay time 2-1 (CVBS)
CVBS GAIN = 0 dB CVBS GAIN = +3 dB
FILPASS = 1, 1 MHz, Note A
⎯ ⎯ 30
ns
BANDWIDTH = max I/O delay time 2-2 (CVBS) BANDWIDTH = cnt BANDWIDTH = min I/O frequency characteristic 3 (MONITOR) I/O frequency characteristic 4 Mute mode attenuation Among input channels Crosstalk Among inputs in a channel HD, VD, FB or SYNC-in to Video-outs (Yvi)
FILPASS = 0, GAIN = 00, 1 MHz, Note A
45 100
ns
0.2 Vp-p input, -3 dB point, Note A 0.2 Vp-p input, -3 dB point, Note A 5 MHz sin wave input, Note A 5 MHz sin wave input, Note A
60 80 ⎯ ⎯ ⎯ ⎯
MHz MHz dB dB
fgm Gmute Gcrschs Gcrsins Gcrsync
-55 ⎯ mV
While HD, VD or FB-out is output. BANDWIDTH=min, NOTE A
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Synchronization Block (Test Condition: A-SYNC = 1 (ON))
Characteristic Symbol Vsep100 525/60i Vsep101 Vsep110 Vsep111 Vsep200 H/V-sync separation level Vsep201 1125/60i Vsep210 Vsep211 Vsep300 Vsep301 SVGA/60 Vsep310 Vsep311 Threshold amplitude for HD input Threshold amplitude for VD input HD-OUT voltage VthHD VthVDn VhdH VhdL HD-OUT width Thdw0 Thdw1 H sync-in to HD-out HD-OUT phase HD-in to HD-out VD-OUT voltage Sync sep 1250i ODD VD-OUT width 1250i EVEN Free-run 1 Free-run 2 V sync-in to VD-out VD-OUT phase H sync-in to VD-out VD-in to VD-out Thdp2 VvdH VvdL Tvdws Tvdwodd When 1250i input Tvdweven Tvdwfi Tvdwfp Tvdp Tvdp1250 Tvdphv Free-run VD-OUT in interlace mode Free-run VD-OUT in progressive mode Except 1250/50i input, Note D 1250/50i input, H sync-in to VD-out, Note D HV OUT = 1, Note A Thdp1 HV-SEP = 10, Note A, Note C HV-SEP = 11, Note A, Note C HV OUT = 1 HV OUT = 1 High level Low level HD WIDTH = 0 HD WIDTH = 1 HV OUT = 0, 1125/60p input, Note D HV OUT = 1, Note A High level Low level Separated VD-OUT 27 38 0.8 0.9 1.0 ⎯ 1.6 0.6 70 25 1.0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0.15 310 25 33 44 ⎯ ⎯ 1.2 0.1 1.7 0.7 90 34 1.2 0.1 290 285 270 4 8 0.20 320 34 39 50 ⎯ ⎯ 1.4 0.4 1.8 0.8 110 40 1.4 0.4 ⎯ ⎯ ⎯ ⎯ ⎯ 0.25 330 40 H µs µs ns ns V µs Vp-p Vp-p V HV-SEP = 10, Note A, Note C HV-SEP = 11, Note A, Note C HV-SEP = 00, Note A, Note C HV-SEP = 01, Note A, Note C 33 45 14 21 38 50 20 27 43 55 26 33 % Test Conditions HV-SEP = 00, Note A, Note C HV-SEP = 01, Note A, Note C HV-SEP = 10, Note A, Note C HV-SEP = 11, Note A, Note C HV-SEP = 00, Note A, Note C HV-SEP = 01, Note A, Note C Min 12 20 26 38 20 28 Typ 18 26 31 43 25 33 Max 24 32 38 50 30 38 % % Unit
H ns ns
Note C: 286 mVp-p sync input for 525/60i, 0.3 Vp-p sync input for 1125/60i and SVGA/60. Note D: See the figures below.
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TB1311AFG
Characteristic
Symbol fh156 fh157/60i fh312 fh315 fh281/50i fh337/60i fh375 fh450
Test Conditions HV FREQ2 = 00000, H DMY = 1 HV FREQ2 = 00001, H DMY = 1 HV FREQ2 = 00010, H DMY = 1 HV FREQ2 = 00011, H DMY = 1 HV FREQ2 = 00100, H DMY = 1 HV FREQ2 = 00101, H DMY = 1 HV FREQ2 = 00110, H DMY = 1 HV FREQ2 = 00111, H DMY = 1 HV FREQ2 = 01000, H DMY = 1 HV FREQ2 = 01001, H DMY = 1 HV FREQ2 = 01010, H DMY = 1 HV FREQ2 = 01011, H DMY = 1 HV FREQ2 = 01100, H DMY = 1
Min ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Typ. 15.564 15.701 31.401 31.401 27.966 33.771 37.288 44.746 31.401 37.288 66.288 74.577 55.932 15.700 27.117 27.965 33.769 27.117 312.5 262.5 625 525 562.5 562.5 750 750 624.5 625.5 628 1066 1250 1125 525 1125 1125 1125 562.5
Max ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Unit
Dummy HD-OUT frequency
fh1250 fh379 fh640 fh750 fh562
kHz
fh157/30p HV FREQ2 = 10000, H DMY = 1 fh270 HV FREQ2 = 10001, H DMY = 1
⎯ ⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ H
⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
fh281/25p HV FREQ2 = 10010, H DMY = 1 fh337/30p HV FREQ2 = 10011, H DMY = 1 fh270/48sf HV FREQ2 = 10100, H DMY = 1 fv625i fv525i fv625p fv525p fv1125i50 fv1125i60 fv750p50 fv750p60 fv1250iO Dummy VD-OUT frequency fv1250iE fvsvga fvsxga fvuxga HV FREQ2 = 00000, V DMY = 1 HV FREQ2 = 00001, V DMY = 1 HV FREQ2 = 00010, V DMY = 1 HV FREQ2 = 00011, V DMY = 1 HV FREQ2 = 00100, V DMY = 1 HV FREQ2 = 00101, V DMY = 1 HV FREQ2 = 00110, V DMY = 1 HV FREQ2 = 00111, V DMY = 1 HV FREQ2 = 01000, V DMY = 1, ODD HV FREQ2 = 01000, V DMY = 1, EVEN HV FREQ2 = 01001, V DMY = 1 HV FREQ2 = 01010, V DMY = 1 HV FREQ2 = 01011, V DMY = 1
fv1125p50 HV FREQ2 = 01100, V DMY = 1 fv525p30 HV FREQ2 = 10000, V DMY = 1
fv1125p24 HV FREQ2 = 10001, V DMY = 1 fv1125p25 HV FREQ2 = 10010, V DMY = 1 fv1125p30 HV FREQ2 = 10011, V DMY = 1 fv1125s24 HV FREQ2 = 10100, V DMY = 1
⎯ ⎯ ⎯ ⎯
⎯ ⎯ ⎯ ⎯
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TB1311AFG
Other Blocks
Characteristic XTAL oscillation amplitude FB input threshold voltage FB-OUT voltage VfbL I/O delay time for FB No signal detection filter DL OFF DL ON Tfbdoff Tfbdon tnsfil1 Low level FB DL = 0 FB DL = 1 SIG LPF = 1, Note F, Note A Symbol Vosc VthFB VfbH Test Conditions Note A, Note E Pins 44, 50, 64, 70 High level Min ⎯ 0.6 1.0 ⎯ 20 50 0.5 14 11 7 4.2 0.45 0.70 0.95 1.20 0.8 2.8 0.8 Typ. 0.4 0.75 1.2 0.1 40 70 1.3 20 15 10 6.0 0.55 0.80 1.05 1.30 1.0 3.0 1.0 Max ⎯ 0.9 1.4 V 0.4 60 90 1.8 26 19 13 7.8 0.65 0.90 V Vthns10 Vthns11 DC detection threshold (DC) DC detection threshold (S) L⇔M M⇔H VdcthLM VdcthMH VdcthS SIG DET LVL = 10, Note H SIG DET LVL = 11, Note H Pins 39, 40, 44, 46, 48, 50, 60, 64, 66, 68, 70, 80 Pins 45, 47, 53, 59, 65, 67, 73, 79 1.15 1.40 1.2 3.2 1.2 V V kΩ µs ns Unit Vp-p V
Imnsfil200 SIG DET IMPE = 00, Note G Imnsfil201 SIG DET IMPE = 01, Note G Impedance for no-signal detection filter Imnsfil210 SIG DET IMPE = 10, Note G Imnsfil211 SIG DET IMPE = 11, Note G Vthns00 Vthns01 No signal detection threshold voltage SIG DET LVL = 00, Note H SIG DET LVL = 01, Note H
Note E: This is the amplitude of the oscillation wave at the point between the crystal and the series capacitor. Note F: Remove the external capacitor connected with the SYNC FILTER pin (pin 14), HV SEP1 = 00, SIG DET IMPE = 11. The delay time from SYNC1-IN input (525/60i) to the SYNC FILTER waveform. Note G: Remove the external capacitor connected with the SYNC FILTER pin (pin 14). Connect 10 kΩ resistor between the SYNC FILTER pin and GND. No input into SYNC1-IN. Measure the current (Ir) on the resistor. Imnsfil2xx = 3.3 / Ir – 10 kΩ. Note H: Remove the external capacitor connected with the SYNC FILTER pin (pin 14). Input a 0 V - Vthnsxx [V] pulse of 15.7 kHz into the SYNC FILTER pin. The pulse voltage during SIG DET status changes.
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TB1311AFG
Test Circuit
47μF 0.01μF 75Ω
100μF 0.01μF
A
B
A
B
+
47μF 0.01μF
75Ω
CVBS5 IN AR2 IN AL2 IN FB1/DC3 Cr1/R1 IN
5.6kΩ
1μF 100pF 1μF 5.6kΩ 100pF 5.6kΩ
CVBS5 IN AR2 IN AL2 IN FB1 IN/DC3(SW LINE1) Cr1/R1 IN AR9 IN/DC4(LINE3-1) Cb1/B1 IN AL9 IN/DC5(LINE2-1)
AU Vcc (9V)
#23
Cr2/R2 OUT FB2 OUT Cb2/B2 OUT AR2 OUT Y2/G2 OUT AL2 OUT
510Ω 10Ω
Cr2/R2 OUT FB2 OUT
#21 510Ω 10Ω
Cb2/B2 OUT AR2 OUT
1μF 75Ω
SW46
#19 510Ω 10Ω
DC4
1μF 100pF 100pF
Y2/G2 OUT AL2 OUT
AR9 IN AL9 IN
5.6kΩ
Cb1/B1 IN
SW48
1μF
1μF
#17
CVBS2 OUT V/S GND SYNC2 IN SYNC FILTER VD OUT HD OUT V/S Vcc (5V)
#10
CVBS2 OUT
DC5 Y1/G1 IN
75Ω 1μF
Y1/G1 IN FB3 IN/DC6(LINE1-1)
#15
FB3/DC6 Cr3/R3 IN AR3 IN Cb3/B3 IN AL3 IN Y3/G3 IN AR4 IN SY1 IN AL4 IN SC1 IN DC7 CVBS6 IN AR5 IN AL5 IN FB2 /DC8
75Ω 1μF 100pF 5.6kΩ 1μF 75Ω 1μF 100pF 5.6kΩ 1μF 75Ω 1μF 100pF 5.6kΩ 1μF 75Ω 1μF 100pF 5.6kΩ 1μF 100pF 75Ω
#14 0.1μF 180pF
Cr3/R3 IN AR3 IN Cb3/B3 IN AL3 IN Y3/G3 IN AR4 IN SY1 IN AL4 IN SC1 IN DC7(S1) CVBS6 IN AR5 IN AL5 IN FB2 IN/ DC8(SW LINE2)
VD OUT HD OUT
0.01μF
+
#11
Cr1/R1 OUT FB1 OUT
#8
47μF 10Ω 510Ω
Cr1/R1 OUT FB1 OUT Cb1/B1 OUT AR1 OUT Y1/G1 OUT
Cb1/B1 OUT AR1 OUT Y1/G1 OUT AL1 OUT CVBS1 OUT AR3 OUT MONITOR OUT AL3 OUT
10Ω 510Ω
#6 10Ω 510Ω
75Ω 1μF
AL1 OUT CVBS1 OUT AR3 OUT MONITOR OUT AL3 OUT
100pF 5.6kΩ 1μF 100pF 5.6kΩ 1μF
A
B
A
B
Components in test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure in the application equipment.
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2006-05-29
+
+
TB1311AFG
Application Circuit 1 (Typical Values)
for S-pin 4 for S-pin 3 HD/VD(PC) Power Supply I2CBUS Vcc 9V Vcc 5V
+ + +
CVBS 4
CVBS 3
Audio 8
changed by “AU8 PIN”
DC2(S4)
DC1(S3)
Audio 1
CVBS4 IN
CVBS3 IN
AR8 IN
AR1 IN
AL8 IN
AL1 IN
HD IN
0.1μF
0.1μF
10kΩ
10kΩ
VD IN
1/2W 180Ω
100Ω
100Ω
1μF 5.6kΩ
1μF 5.6kΩ
1μF 5.6kΩ
1μF 5.6kΩ
40
39
47μF
0.01μF
10pF
4.7μF
100pF
100pF
100pF
100pF
470Ω
40
39
CVBS4 IN 38
37
CVBS3 IN 36
35
34
SYNC1 IN 33
AU GND 32
HD IN 31
VD IN 30
Vdd (3.3V) 29
XTAL 28
Vss 27
SCL 26
Audio 2
AR2 IN AL2 IN
AL8 IN/ DC2(S4)
AR8 IN/ DC1(S3)
AR1 IN
AL1 IN
Yvi OUT
SDA 25
470Ω
1μF
1μF
1μF
0.1μF
3.579545MHz
SDA
SCL
+
0.01μF
41
SCART 1
42
B1 IN G1 IN FB1 IN
5.6kΩ 1μF 100pF 5.6kΩ 1μF 0Ω 100kΩ 1μF
23
R1 IN
24
CVBS5 IN
1μF
CVBS5 IN AR2 IN AL2 IN FB1 IN/DC3(SW LINE1) Cr1/R1 IN AR9 IN/DC4(LINE3-1) Cb1/B1 IN AL9 IN/DC5(LINE2-1) Y1/G1 IN changed by “CbCr PIN1”
AU Vcc (9V) Cr2/R2 OUT FB2 OUT Cb2/B2 OUT AR2 OUT Y2/G2 OUT AL2 OUT CVBS2 OUT V/S GND
100μF
+
100pF
510Ω 10Ω
FB2 OUT Cr2/R2 OUT Cb2/B2 OUT
43
22
44
21
510Ω 10Ω
Y2/G2 OUT CVBS2 OUT Sub out DC11(LINE1-2)
1kΩ
45
20
46
19
100pF 5.6kΩ 1μF 1μF
510Ω 10Ω
AR2 OUT AL2 OUT VD OUT HD OUT
47
Audio 9
AR9 IN AL9 IN
100pF 5.6kΩ 1μF 1μF
48
17
18
The function of pins 46 and 48 are changed by “AU9 PIN”
TB1311AFG
50
0Ω 1μF
15
FB3 IN
100kΩ
FB3 IN/DC6(LINE1-1) changed by “CbCr PIN3” Cr3/R3 IN AR3 IN Cb3/B3 IN AL3 IN Y3/G3 IN AR4 IN SY1 IN AL4 IN SC1 IN changed by “CbCr PIN2” DC7(S1) CVBS6 IN AR5 IN AL5 IN FB2 IN/ DC8(SW LINE2) AL10 IN/ DC10(LINE2-2) FB4 IN/ 70 DC11(LINE1-2) AR10 IN/ DC9(LINE3-2)
SYNC2 IN SYNC FILTER VD OUT HD OUT V/S Vcc (5V) Cr1/R1 OUT FB1 OUT Cb1/B1 OUT AR1 OUT Y1/G1 OUT AL1 OUT CVBS1 OUT
51
Audio 3
AR3 IN AL3 IN
100pF 5.6kΩ 1μF 1μF
52
53
Component Video 3
Cr3 IN Cb3 IN Y3 IN
54
5.6kΩ 1μF 1μF
11
100pF
12
13
14
180pF
0.01μF
+
55
10
10Ω 47μF
0.1μF
AMP or ATT
49
16
+
56
100pF 5.6kΩ 1μF
510Ω
9
FB1 OUT
10Ω 510Ω
Audio 4
AR4 IN AL4 IN
57
1μF
Cr1/R1 OUT Main out
70
0.1μF
8
58
100pF 5.6kΩ 1μF 100pF
Cb1/B1 OUT
7
10Ω
Y1/G1 OUT CVBS1 OUT
510Ω
59
S-pin 1
SY1 IN SC1 IN
10kΩ 0.1μF 1μF
6
60
AR1 OUT AL1 OUT
61
62
Audio 5
63
AL5 IN
100pF 5.6kΩ 1μF 0Ω 100kΩ
MONITOR OUT AL3 OUT
MONITOR OUT AL3 OUT
64
5V
Cb2/B2 IN
Cb4/B4 IN
Cr2/R2 IN
Cr4/R4 IN
1kΩ 1μF
44
DC3(SW LINE1) Cr1 IN DC4(LINE3-1) Cb1 IN DC5(LINE2-1) Y1 IN < D-pin 1 > DC6(LINE1-1)
0.1μF
65
66
67
68
69
71
72
73
74
75
76
77
78
79
45
100kΩ
100pF
100pF
100pF
100pF
100pF
100pF
5.6kΩ 1μF
5.6kΩ 1μF
5.6kΩ 1μF
5.6kΩ 1μF
5.6kΩ 1μF
1kΩ 1μF
0.1μF
10kΩ
46
0.1μF
5.6kΩ 1μF
100pF
1μF
1μF
1μF
1μF
1μF
1μF
1μF
0Ω
80
DC12(S2)
Y2/G2 IN
Y4/G4 IN
150kΩ
SC2 IN
AR6 IN
AR7 IN
AL6 IN
AL7 IN
SY2 IN
1
47
64
0.1μF
65
66
67
68
48
0.1μF 1kΩ 1μF
5V
150kΩ 1kΩ
0.1μF
0.1μF
1μF
1μF
Cb4 IN
B2 IN
Cr4 IN
CVBS6 IN
Y4 IN
R2 IN
G2 IN
AL10 IN
AR10 IN
AR6 IN
AL6 IN
AR7 IN
Cb2 IN
Cr2 IN
DC9(LINE3-2)
1kΩ
The function of pins 66 and 68 are changed by “AU10 PIN”
Input video signals driven with low impedance. The application circuits shown in this document are examples provided for reference purposes only. Thorough evaluation is required in the mass production design phase. By furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights.
< D-pin 2 >
SCART 2
Audio 10
Component Video 4
Audio 6
Audio 7
S-pin 2
DC8(SW LINE2)
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2006-05-29
DC10(LINE2-2)
Y2 IN
50
0.1μF
FB2 IN
SC2 IN
AL7 IN
SY2 IN
FB4 IN
49
1μF
1kΩ
1kΩ
69
Monitor out
AR5 IN
100pF 5.6kΩ 1μF
changed by “CbCr PIN4”
AR3 OUT
3
4
5
AR3 OUT
2
TB1311AFG
Application Circuit 2 (Examples of Connectors)
20 21 19
18 17
16 15
14 13
12 11
10 9
8 7
6 5
4 3
2 1
SCART
AR-out AL-out V-out
50
49
48
47
46
45
44
43
42
41
SCART connector
D
11 6 1 7 2 12 8 3 13 9 4 14 10 5 15
8 1
9 2
10 3
11 4
12 5
13 6
14 7
D-SUB15
Z2.0V Z2.0V
5V 100Ω 1μF 100Ω 4.7μF
75Ω
75Ω
0.1μF
1μF
1μF
1μF
50
49
48
47
46
45
44
50
49
48
47
46
45
44
31
30
AL9 IN/DC5(LINE2-1)
AR9 IN/DC4(LINE3-1)
Cr1/R1 IN
FB3 IN/DC6(LINE1-1)
Y1/G1 IN
Cb1/B1 IN
FB1 IN/DC3(SW LINE1)
HD IN
VD IN
D-pin
D-SUB15
The application circuits shown in this document are examples provided for reference purposes only. Thorough evaluation is required in the mass production design phase. By furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights.
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2006-05-29
TB1311AFG
Application Circuit 3 (System Configuration)
(1) For nonstandard signals such as CVBS, YC (S-video), 525i, 625i or so.
TB1311
Video SW Video block Video-in
Color decoder / IP converter / ...
PAL/NTSC/SECAM Color decoder Sync processor
ADC PLL
Sync-in
Sync block
Freq counting block HD/VD-in I/P converter Scaler
Sync SW
The TB1311AFG does not support weak signals, ghost signals or other nonstandard signals. Therefore, these signals should be dealt with through the use of another device capable of handling these signals, such as a color-decoder. In these cases, the signal switcher and the video circuits of the TB1311AFG can be used. In some cases, “no-input detection” can be also used for these signals. The TB1311AFG cannot distinguish between component and RGB video. The different kinds of input signal should be separated through the use of different signal-specific input pins; for example, specific-purpose pins for RGB video input only or component video input only.
(2) For standard component video (SMPTE STANDARD) and standard RGB video (VESA STANDARD)
TB1311
Video SW Video block Video-in
Color decoder / IP converter / ...
PAL/NTSC/SECAM Color decoder Sync processor
ADC PLL
Sync-in
Sync block
Freq counting block HD/VD-in I/P converter Scaler
Sync SW
The TB1311AFG can detect a format type for standard signal inputs.
The application circuits shown in this document are examples provided for reference purposes only. Thorough evaluation is required in the mass production design phase. By furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights.
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TB1311AFG
Package Dimensions
P-QFP80-1420-0.80C Unit: mm
Weight: 1.6 g (typ.)
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TB1311AFG
About solderability, following conditions were confirmed • Solderability (1) Use of Sn-37Pb solder Bath · solder bath temperature = 230°C · dipping time = 5 seconds · the number of times = once · use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath · solder bath temperature = 245°C · dipping time = 5 seconds · the number of times = once · use of R-type flux
RESTRICTIONS ON PRODUCT USE
• The information contained herein is subject to change without notice. 021023_D
060116EBA
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E
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