TB62218AFG/AFTG
TOSHIBA BiCD Integrated Circuit
Silicon Monolithic
TB62218AFG, TB62218AFTG
BiCD Constant-Current Two-Phase Bipolar Stepping Motor Driver IC
The TB62218AFG/AFTG is a two-phase bipolar stepping motor
driver using a PWM chopper.
Fabricated with the BiCD process, the TB62218AFG/AFTG is
rated at 40 V/2.0 A.
The on-chip voltage regulator allows control of a stepping motor
with a single VM power supply.
TB62218AFG
Features
•
Bipolar stepping motor driver
•
PWM constant-current drive
•
Allows two-phase, 1-2-phase and W1-2 phase excitations.
•
BiCD process: Uses DMOS FETs as output power transistors.
•
High voltage and current: 40 V/2.0 A (absolute maximum
ratings)
•
Thermal shutdown (TSD), overcurrent shutdown (ISD), and
power-on resets (PORs)
•
Packages: HSOP28-P-0450-0.8
QFN48-P-0707-0.50
HSOP28-P-450-0.80
TB62218AFTG
QFN48-P-0707-0.50
Weight
HSOP28-P-0450-0.80: 0.79 g (typ.)
QFN48-P-0707-0.50: 0.14 g (typ.)
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2012-03-12
TB62218AFG/AFTG
Pin Assignment
TB62218AFG (HSOP28)
IN_A1
1
28
OSCM
IN_A2
2
27
Vref_A
PHASE_A
3
26
Vref_B
PHASE_B
4
25
NC
IN_B1
5
24
NC
IN_B2
6
23
Vcc
STANDBY
7
22
VM
FIN(GND)
FIN(GND)
RS_A
8
21
RS_B
NC
9
20
NC
OUT_A
10
19
OUT_B
NC
11
18
NC
GND
12
17
GND
OUT_A
13
16
OUT_B
GND
14
15
GND
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2012-03-12
TB62218AFG/AFTG
Pin Assignment
NC
VCC
NC
VM
NC
RS_B1
RS_B2
NC
OUT_B1
OUT_B2
NC
*
NC
TB62218AFTG (QFN48)
36
35
34
33
32
31
30
29
28
27
26
25
*
NC 37
24 NC
NC 38
23 NC
NC 39
22 GND
GND 40
21 OUT_B1
Vref_B 41
20 OUT_B2
Vref_A 42
19 GND
OSCM 43
18 GND
IN_A1 44
17 OUT_A2
IN_A2 45
16 OUT_A1
6
7
8
9
10
11
12
NC
5
OUT_A2
4
OUT_A1
3
NC
2
RS_A2
1
RS_A1
*
NC
13 NC
GND
NC 48
STANDBY
14 NC
IN_B2
PHASE_B 47
IN_B1
15 GND
NC
PHASE_A 46
*
*Mark PAD: It must be connected to GND
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2012-03-12
TB62218AFG/AFTG
Block Diagram
In the block diagram, part of the functional blocks or constants may be omitted or simplified for explanatory
purposes.
STANDBY
VM
PHASE_A
VMR
Detect
IN_A1
Vcc Voltage
Regulator
Input Logic
IN_A2
Vcc
PHASE_B
Chopper OSC
IN_B1
OSCM
IN_B2
OSC
VM
CR-CLK
Current Level Set
Vref
Converter
Current Feedback (×2)
VRS
Output Control
(Mixed Decay Control)
RS COMP
RS
ISD
STANDBY
TSD
Output
VMR
(H-Bridge×2)
VM
Detect
Detection Circuit
Stepping
Motor
Note: All the grounding wires of the TB62218AFG/AFTG must run on the solder mask on the PCB and be externally
terminated at only one point. Also, a grounding method should be considered for efficient heat dissipation.
Careful attention should be paid to the layout of the output, VDD (VM) and GND traces, to avoid short-circuits
across output pins or to the power supply or ground. If such a short-circuit occurs, the TB62218AFG/AFTG may be
permanently damaged.
Also, utmost care should be taken for pattern designing and implementation of the TB62218AFG/AFTG since it has
the power supply pins (VM, RS_A, RS_B, OUT_A, OUT_A , OUT_B, OUT_B , GND) particularly a large current can
run through. If these pins are wired incorrectly, an operation error or even worse a destruction of the
TB62218AFG/AFTG may occur.
The logic input pins must be correctly wired, too; otherwise, the TB62218AFG/AFTG may be damaged due to a
current larger than the specified current running through the IC.
Please note the avbove when designing and implementing IC patterns.
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2012-03-12
TB62218AFG/AFTG
Pin Function
TB62218AFG (HSOP28)
Pin No.
Pin Name
1
IN_A1
2
IN_A2
3
PHASE_A
Current direction signal input for A phase
4
PHASE_B
Current direction signal input for B phase
5
IN_B1
6
IN_B2
7
STAND BY
8
RS_A
9
NC
10
OUT_A
11
NC
12
GND
13
OUT_A
14
GND
15
GND
16
OUT_B
17
GND
18
NC
19
OUT_B
20
NC
21
RS_B
Function
A-phase excitation control input
A-phase excitation control input
B-phase excitation control input
B-phase excitation control input
Output; Wait for power saving by disabling OSCM
The sink current sensing of A-phase motor coil
No-connect
A-phase positive driver output
No-connect
Motor power ground
A-phase negative driver output
Motor power ground
Motor power ground
B-phase negative driver output
Motor power ground
No-connect
B-phase positive driver output
No-connect
The sink current sensing of B-phase motor coil
22
VM
Power supply
23
VCC
Smoothing filter for logic power supply
24
NC
No-connect
25
NC
No-connect
26
Vref_B
Tunes the current level for B-phase motor drive.
27
Vref_A
Tunes the current level for A-phase motor drive.
28
OSCM
Oscillator pin for PWM choppers
Pin Interfaces (HSOP28)
8 21
150Ω
1
2
3
4
5
6
7
22
100kΩ
8kΩ
3kΩ
3kΩ
FIN
23
26
1kΩ
10
13
19
16
12
14
17
15
1kΩ
28
500Ω
27
FIN
FIN
The equivalent circuit diagrams may be simplified or some parts of them may be omitted fo
explanatory purposes. Absolute precision of the chip internal resistance is +/-30%.
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2012-03-12
TB62218AFG/AFTG
TB62218AFTG (QFN48)
Pin
Pin Name
No.
Pin
No.
Pin Name
No-connect
25
NC
Function
1
NC
2
IN_B1
B-phase excitation control input
26
OUT_B2
3
IN_B2
B-phase excitation control input
27
OUT_B1
28
NC
4
STAND BY High: Normal operation mode
Low: Standby mode
5
GND
6
NC
7
RS_A1
8
RS_A2
9
NC
10
OUT_A1
11
OUT_A2
12
NC
13
14
15
GND
16
OUT_A1
17
OUT_A2
18
GND
Motor power ground
19
GND
Motor power ground
20
OUT_B2
21
OUT_B1
22
GND
23
24
Function
No-connect
B-phase positive driver output
No-connect
Logic ground
29
RS_B2
No-connect
30
RS_B1
Power supply pin of A-phase motor coil and
the sink current sensing of A-phase motor coil
31
NC
32
VM
Power supply
No-connect
33
NC
No-connect
Power supply pin of B-phase motor coil and
the sink current sensing of B-phase motor coil
No-connect
34
VCC
Smoothing filter for logic power supply
35
NC
No-connect
No-connect
36
NC
No-connect
NC
No-connect
37
NC
No-connect
NC
No-connect
38
NC
No-connect
Motor power ground
39
NC
40
GND
Logic ground
41
Vref_B
Tunes the current level for B-phase motor
drive.
42
Vref_A
Tunes the current level for A-phase motor
drive.
43
OSCM
Oscillator pin for PWM choppers
44
IN_A1
A-phase excitation control input
A-phase positive driver output
A-phase negative driver output
B-phase negative driver output
No-connect
45
IN_A2
Motor power ground
46
PHASE_A
Current direction signal input for A phase
A-phase excitation control input
NC
No-connect
47
PHASE_B
Current direction signal input for B phase
NC
No-connect
48
NC
No-connect
Pin Interfaces (QFN48)
150Ω
8 29
2
3
32
4
44 45
46 47
100kΩ
8kΩ
3kΩ
3kΩ
7
40
30
27
21
10
16
11
17
26
20
15
18
22
19
34
41
1kΩ
43
1kΩ
500Ω
42
40
40
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
Absolute precision of the chip internal resistance is +/-30%.
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2012-03-12
TB62218AFG/AFTG
Output Function Table
Output
Input signal
PHASE_A
PHASE_B
H
L
IN_A1
IN_B1
IN_A2
IN_B2
OUT_X
OUT _ X
IOUT
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
H
H
H
Outputs disabled
L
L
L
Outputs disabled
L
L
L
Outputs disabled
H
H
H
Outputs disabled
100%
71%
38%
0%
-100%
-71%
-38%
0%
IOUT: The current which flows OUT_X to OUT _ X is defined plus current. The current which flows OUT _ X to OUT_X
is defined as minus current.
Input signals to IN_X and PHASE_X after the voltage range of the motor being used is attained.
(*X: A1, A2, B1. B2)
Other Functions
Pin Name
H
L
Notes
STAND BY
Normal operation
mode
Standby mode
When STAND BY is Low, both the oscillator and output drivers
are disabled. The TB62218AFG/AFTG can not drive a motor.
Detection Features
(1)
Thermal shutdown (TSD)
The thermal shutdown circuit turns off all the outputs when the junction temperature (Tj) exceeds 150°C
(typ.). The outputs retain the current states.
The TB62218AFG/AFTG exits TSD mode and resume normal operation when the TB62218AFG/AFTG is
rebooted or the STAND BY pin is changed from High to Low and then to High.
(2)
Power-ON-resets (PORs) for VMR and VCCR (VM and VCC voltage monitor)
The outputs are forced off until VM and VCC reach the rated voltages.
(3)
Overcurrent shutdown (ISD)
Each phase has an overcurrent shutdown circuit, which turns off the corresponding outputs when the output
current exceeds the shutdown trip threshold (above the maximum current rating: 2.0A minimum).
The TB62218AFG/AFTG exits ISD mode and resume normal operation when the STAND BY pin is changed
from High to Low and then to High.
This circuit provides protection against a short-circuit by temporarily disabling the device. Important notes
on this feature will be provided later.
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2012-03-12
TB62218AFG/AFTG
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Symbol
Rating
Unit
Remarks
Motor power supply
VM
40
V
⎯
Motor output voltage
VOUT
40
V
⎯
Motor output current
IOUT
2.0
A per phase
(Note 1)
Logic input voltage
VIN
-0.5 to 6.0
V
⎯
Vref
5.0
V
⎯
QFN48
PD
1.3
W
(Note 2)
HSOP28
PD
1.3
W
(Note 2)
Vref standard voltage
Power dissipation
Operating temperature
Topr
−20 to 85
°C
⎯
Storage temperature
Tstg
−55 to 150
°C
⎯
Junction temperature
Tj (MAX)
150
°C
⎯
Note 1: As a guide, the maximum output current should be kept below 1.4 A per phase. The maximum output current
may be further limited by thermal considerations, depending on ambient temperature and board conditions.
Note 2: Stand-alone (Ta = 25°C)
If Ta is over 25°C, derating is required at 10.4 mW/°C.
Ta: Ambient temperature
Topr: Ambient temperature while the TB62218AFG/AFTG is active
Tj:
Junction temperature while the TB62218AFG/AFTG is active. The maximum junction temperature is
limited
by the thermal shutdown (TSD) circuitry.
It is advisable to keep the maximum current below a certain level so that the maximum junction
temperature, Tj (max), will not exceed 120°C.
Note: The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even
for a moment. Do not exceed any of these ratings.
Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by
explosion or combustion.
The value of even one parameter of the absolute maximum ratings should not be exceeded under any
circumstances. The TB62218AFG/AFTG does not have overvoltage protection. Therefore, the device is
damaged if a voltage exceeding its rated maximum is applied.
All voltage ratings including supply voltages must always be followed. The other notes and considerations
described later should also be referred to.
Operating Ranges (Ta = 0 to 85°C)
Characteristics
Motor power supply
Motor output voltage
Logic input voltage
Symbol
Min
Typ.
Max
Unit
Remarks
VM
10.0
24.0
38.0
V
⎯
IOUT
⎯
1.4
2.0
A
Per phase (Note 1)
VIN(H)
2.0
⎯
5.5
V
Logic high level
VIN(L)
-0.4
⎯
1.0
V
Logic low level
Chopper frequency
fchop
40
100
150
kHz
⎯
Vref reference voltage
Vref
GND
⎯
3.6
V
⎯
VRS
0.0
±1.0
±1.5
V
Voltage across the current-sensing
resistor pins
Referenced to the VM pin (Note 2)
Note 1: The actual maximum current may be limited by the operating environment (operating conditions such as
excitation mode or operating duration, or by the surrounding temperature or board heat dissipation). Determine
a realistic maximum current by calculating the heat generated under the operating environment.
Note 2: The maximum VRS voltage should not exceed the maximum rated voltage.
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2012-03-12
TB62218AFG/AFTG
Electrical Characteristics 1 (Ta = 25°C, VM = 24 V, unless otherwise specified)
Characteristics
Symbol
Test
Circuit
Input hysteresis voltage
VIN (HIS)
DC
High
IIN (H)
Digital input current
DC
Low
IIN (L)
IM1
Power consumption
IM2
DC
IM3
Output leakage
current
High-side
IOH
Low-side
IOL
DC
Test Condition
Min
Typ.
Max
Unit
(Note)
100
200
300
mV
VIN = 5 V at the digital input pins under
test
35
50
75
μA
VIN = 0 V at the digital input pins under
test
⎯
⎯
1
μA
Outputs open, STAND BY = Low
⎯
2
3
mA
Outputs open, STAND BY = High
⎯
3.5
5
mA
Outputs open (two-phase excitation)
⎯
5
7
mA
VRS = VM = 40 V: VOUT = 0 V
⎯
⎯
1
μA
VRS = VM = VOUT = 40 V
1
⎯
⎯
μA
Digital input pins
Chanel-to-channel current
differential
ΔIOUT1
DC
Channel-to-channel error
−5
0
5
%
Output current error relative to
the predetermined value
ΔIOUT2
DC
IOUT = 1 A
−5
0
5
%
IRS
DC
VRS = VM = 24 V
0
⎯
10
μA
RON (D-S)
DC
IOUT = 2.0 A, Tj = 25°C
⎯
1.0
1.5
Ω
RS pin current
Drain-source ON-resistance of
the output transistors (upper
and lower sum)
Note: VIN (L → H) is defined as the VIN voltage that causes the outputs (OUT_A1, OUT_A2, OUT_B1and OUT_B2
pins) to change when a pin under test is gradually raised from 0 V. VIN (H → L) is defined as the VIN voltage that
causes the outputs (OUT_A1, OUT_A2, OUT_B1and OUT_B2 pins) to change when the pin is then gradually
lowered.
The difference between VIN (L → H) and VIN (H → L) is defined as the input hysteresis.
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2012-03-12
TB62218AFG/AFTG
Electrical Characteristics 2 (Ta = 25°C, VM = 24 V, unless otherwise specified)
Characteristics
Vref input current
Vref decay rate
TSD threshold
(Note 1)
VM recovery voltage
Overcurrent trip threshold
(Note 2)
Supply voltage for internal circuitry
Symbol
Test
Circuit
Iref
DC
Vref (GAIN)
DC
TjTSD
DC
VMR
ISD
VCC
DC
Test Condition
Min
Typ.
Max
Unit
Vref = 3.0 V
-
0
1
μA
Vref = 2.0 V
1/4.8
1/5.0
1/5.2
⎯
⎯
140
150
170
°C
DC
⎯
7.0
8.0
9.0
V
DC
⎯
2.0
3.0
4.0
A
4.75
5.00
5.25
V
ICC = 5.0 mA
Note 1: Thermal shutdown (TSD) circuitry
When the junction temperature of the device has reached the threshold, the TSD circuitry is tripped, causing
the internal reset circuitry to turn off the output transistors.
The TSD circuitry is tripped at a temperature between 140°C (min) and 170°C (max). Once tripped, the TSD
circuitry keeps the output transistors off until STANDBY is deasserted High or the IC is restarted. The thermal
shutdown circuit is provided to turn off all the outputs when the IC is overheated. For this reason, please avoid
using TSD for other purposes.
Note 2: Overcurrent shutdown (ISD) circuitry
When the output current has reached the threshold, the ISD circuitry is tripped, causing the internal reset
circuitry to turn off the output transistors.
To prevent the ISD circuitry from being tripped due to switching noise, it has a masking time of four CR
oscillator cycles. Once tripped, it takes a maximum of four cycles to exit ISD mode and resume normal
operation.
The ISD circuitry remains active until the STANDBY pin is changed from Low to High again or the IC is
restarted.
The TB62218AFG/AFTG remains in Standby mode while in ISD mode.
Note 3: If the supply voltage for internal circuitry (VCC) is split with an external resistor and used as Vref input supply
voltage, the accuracy of the output current setting will be at ±8% when the Vcc output voltage accuracy and the
Vref damping ratio accuracy are combined.
Note 4: The circuit design has been designed so that electromotive force or leak current from signal input does not
occur when VM voltage is not supplied, even if the logic input signal is input. Even so, regulate logic input
signals before resupply of VM voltage so that the motor does not operate when voltage is reapplied.
Back-EMF
While a motor is rotating, there is a timing at which power is fed back to the power supply. At that timing, the
motor current recirculates back to the power supply due to the effect of the motor back-EMF.
If the power supply does not have enough sink capability, the power supply and output pins of the device might rise
above the rated voltages. The magnitude of the motor back-EMF varies with usage conditions and motor
characteristics. It must be fully verified that there is no risk that the TB62218AFG/AFTG or other components will be
damaged or fail due to the motor back-EMF.
Cautions on Overcurrent Shutdown (ISD) and Thermal Shutdown (TSD)
•
The ISD and TSD circuits are only intended to provide temporary protection against irregular conditions such as
an output short-circuit; they do not necessarily guarantee the complete IC safety.
•
If the device is used beyond the specified operating ranges, these circuits may not operate properly: then the
device may be damaged due to an output short-circuit.
•
The ISD circuit is only intended to provide a temporary protection against an output short-circuit. If such a
condition persists for a long time, the device may be damaged due to overstress. Overcurrent conditions must be
removed immediately by external hardware.
IC Mounting
Do not insert devices incorrectly or in the wrong orientation. Otherwise, it may cause the breakdown, damage
and/or deterioration of the device.
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2012-03-12
TB62218AFG/AFTG
AC Electrical Characteristics (Ta = 25°C, VM = 24 V, 6.8 mH/5.7 Ω)
Characteristics
Symbol
Test
Circuit
fPHASE
AC
tPHASE
AC
twp
Min
Typ.
Max
Unit
⎯
⎯
400
kHz
⎯
100
⎯
⎯
ns
AC
⎯
50
⎯
⎯
ns
twn
AC
⎯
50
⎯
⎯
ns
tr
AC
⎯
100
150
200
ns
tf
AC
⎯
100
150
200
ns
tpLH (P) MAX
AC
PHASE to OUT
500
850
1200
ns
tpHL (P) MAX
AC
PHASE to OUT
500
850
1200
ns
tpLH (P) MIN
AC
PHASE to OUT
250
600
950
ns
tpHL (P) MIN
AC
PHASE to OUT
250
600
950
ns
tBLANK
AC
IOUT = 1.0 A
200
300
500
ns
OSC oscillation reference
frequency
fCR
AC
COSC = 270 pF, ROSC = 3.6 kΩ
1200
1600
2000
kHz
Chopper frequency range
fchop (RANGE)
AC
VM = 24 V, outputs enabled ACTIVE
(IOUT = 1.0 A)
40
100
150
kHz
fchop
AC
Outputs enabled (IOUT = 1.0 A),
CR = 1600 kHz
⎯
100
⎯
kHz
TlSD (Mask)
AC
After ISD threshold is exceeded due to
an output short-circuit to power or
ground
⎯
4
⎯
CR-CLK
tlSD
AC
After ISD threshold is exceeded due to
an output short-circuit to power or
ground
4
⎯
8
CR-CLK
Phase frequency
Minimum phase pulse width
Output transistor switching
characteristics
Blanking time for current spike
prevention
Predefined chopper frequency
ISD masking time
ISD on-time
Test Condition
fOSC = 1600 kHz
Timing Charts of Output Transistors Switching
twp
twn
90%
PHASE
90%
tphase
10%
10%
tpLH
tpHL
VM
90%
Output voltage
GND
50%
50%
90%
50%
50%
10%
10%
tr
tf
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2012-03-12
TB62218AFG/AFTG
z Current Waveform in Mixed Decay Mode
Mixed-Decay mode, the purpose of which is constant-current control, starts out in Fast-Decay mode for 37.5% of
the whole period and then is followed by Slow-Decay mode for the remainder of the period.
fchop
fchop
Internal
CR CLK
IOUT
Predefined
current level
MDT
MDT
Predefined current level
NF
NF
37.5%
Mixed-decay
MDT (mixed decay timing) Point: 37.5% (6/16) Fixed
Timing charts may be simplified for explanatory purposes.
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2012-03-12
TB62218AFG/AFTG
z Current Waveform in Mixed (Slow + Fast) Decay Mode
Timing charts may be simplified for explanatory purposes.
•
When a current value increases (Mixed-Decay point is fixed to 37.5%)
fchop
fchop
fchop
fchop
Internal
OSCM CLK
Predefined
current level
NF
NF
Slow
Fast
Predefined
current level
•
NF
NF
Slow
Charge
Fast
Charge
Slow
Charge
Fast
Charge
Slow
Fast
When a current value decreases (Mixed-Decay point is fixed to 37.5%)
fchop
fchop
fchop
fchop
Internal
OSCM CLK
The IC enters Charge mode for a moment at which the internal RS
comparator compares the values. The IC immediately enters Slow-Decay
mode because of the current value exceeding the predefined current level.
Predefined
current level
NF
NF
Slow
Charge
Fast
Slow
Charge
Fast
Predefined
current level
NF
Charge
Slow
Fast
NF
Charge
NF
Slow
Fast
Charge
The Charge period starts as the internal oscillator clock starts counting. When the output current reaches the
predefined current level, the internal RS comparator detects the predefined current level (NF); as a result, the IC
enters Slow-Decay mode.
The TB62218AFG/AFTG transits from Slow-Decay mode to Fast-Decay mode at the point 37.5 of a PWM
frequency (one chopping frequency) remains in a whole PWM frequency period (on the rising edge of the 11th clock
of the OSCM clock).
When the OSCM pin clock counter clocks 16 times, the Fast-Decay mode ends; and at the same time, the
counter is reset, which brings the TB62218AFG/AFTG into Charge mode again.
Note: These figures are intended for illustrative purposes only. If designed more realistically, they would show transient
response curves.
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2012-03-12
TB62218AFG/AFTG
z Output Transistor Operating Modes
VM
VM
VM
RRS
RRS
RS Pin
RRS
RS Pin
RS Pin
U1
U2
U1
U2
U1
U2
ON
OFF
OFF
OFF
OFF
ON
Load
Load
Load
L1
L2
L1
L2
L1
L2
OFF
ON
ON
ON
ON
OFF
PGND
PGND
PGND
Slow-Decay Mode
A current circulates
around the motor coil
and this device.
Charge Mode
A current flows into
the motor coil.
Fast-Decay Mode
The energy of the
motor coil is fed back
to the power supply.
Output Transistor Operating Modes
CLK
U1
U2
L1
L2
Charge
ON
OFF
OFF
ON
Slow-Decay Mode
OFF
OFF
ON
ON
Fast-Decay Mode
OFF
ON
ON
OFF
Note: This table shows an example of when the current flows as indicated by the arrows in the figures shown above. If
the current flows in the opposite direction, refer to the following table.
CLK
U1
U2
L1
L2
Charge
OFF
ON
ON
OFF
Slow-Decay Mode
OFF
OFF
ON
ON
Fast-Decay Mode
ON
OFF
OFF
ON
The TB62218AFG/AFGT switches among Charge, Slow-Decay and Fast-Decay modes automatically for
constant-current control.
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory
purposes.
Calculation of the Predefined Output Current
For PWM constant-current control, the TB62218AFG/AFTG uses a clock generated by the CR oscillator. The peak
output current can be set via the current-sensing resistor (RRS) and the reference voltage (Vref), as follows:
IOUT = Vref/5 ÷ RRS (Ω)
where, 1/5 is the Vref decay rate, Vref (GAIN). For the value of Vref (GAIN), see the Electrical Characteristics table.
For example, when Vref = 3 V, to generate an output current (IOUT) of 0.8 A, RRS is calculated as:
RRS = (Vref /5) ÷ IOUT = (3/5) ÷ 0.8 = 0.75 Ω. (≥ 0.5 W)
14
2012-03-12
TB62218AFG/AFTG
IC Power Consumption
The power consumed by the TB62218AFG/AFTG is approximately the sum of the following two: 1) the power
consumed by the output transistors, and 2) the power consumed by the digital logic and pre-drivers.
• The power consumed by the output transistors is calculated, using the RON (D-S) value of 1.0 Ω.
•
Whether in Charge, Fast Decay or Slow Decay mode, two of the four transistors comprising each H-bridge
contribute to its power consumption at a given time.
Thus the power consumed by each H-bridge is given by:
P (out) = IOUT (A) × VDS (V) = 2 × IOUT2 × RON ......................................... (1)
In two-phase excitation mode (in which two phases have a phase difference of 90°), the average
power consumption in the output transistors is calculated as follows:
RON = 1.0 Ω (@2.0 A)
IOUT (Peak) = 1.0 A
VM = 24 V
P (out) = 2Hsw × 1.02 (A) × 1.0 (Ω) = 2.0 (W)................................................ (2)
The power consumption in the IM domain is calculated separately for normal operation and standby
modes:
Normal operation mode: I (IM3) = 5.0 mA (typ.)
Standby mode: I (IM1) = 2.0 mA (typ.)
The current consumed in the digital logic portion of the TB62218AFG/AFTG is indicated as IMx. The
digital logic operates off a voltage regulator that is internally connected to the VM power supply. It
consists of the digital logic connected to VM (24 V) and the network affected by the switching of the
output transistors. The total power consumed by IMx can be estimated as:
P (IM) = 24 (V) × 0.005 (A) = 0.12 (W)........................................................... (3)
Hence, the total power consumption of the TB62218AFG/AFTG is:
P = P (out) + P (IM) = 2.12 (W)
The standby power consumption is given by:
P (Standby) , P (out) = 24 (V) × 0.002 (A) = 0.048 (W)
Board design should be fully verified, taking thermal dissipation into consideration.
15
2012-03-12
TB62218AFG/AFTG
z OSC-Charge Delay
Since the rising level of the OSC waveform is referenced to convert it into the internal CR CLK waveform, about
up to1 us (when CR = 1600 kHz) of a delay occurs between the OSC waveform and internal CR CLK waveform.
OSC charge delay
Internal
CR CLK
OSC fast delay
H
OSC (CR)
L
tchop
Output
voltage
OUT_A
Output
voltage
OUT _ A
H
50%
L
H
50%
50%
L
Predefined
current level
Output
current
L
Charge
Slow
Fast
Timing charts may be simplified for explanatory purposes.
16
2012-03-12
TB62218AFG/AFTG
Phase Sequences
Two-Phase Excitation Mode
Timing charts may be simplified for explanatory purposes.
150
B
A
100
A
B
C
D
B PHASE
50
PHASE A
H
L
L
H
A PHASE
Input
IN A1
IN A2
H
H
H
H
H
H
H
H
Output
IOUT(A) PHASE B
100%
H
-100%
H
-100%
L
100%
L
B PHASE
Input
IN B1
IN B2
H
H
H
H
H
H
H
H
Output
IOUT(B)
100%
100%
-100%
-100%
0
-150
-100
-50
0
50
100
150
-50
C
-100
D
-150
A PHASE
A
B
C
D
A
B
C
D
A
B
C
D
A
B
100%
IOUT(A)
0%
-100%
100%
0%
IOUT(B)
PHASE_A
IN_A1
IN_A2
PHASE_B
IN_B1
IN_B2
-100%
H
L
H
L
H
L
H
L
H
L
H
L
17
2012-03-12
TB62218AFG/AFTG
1-2-Phase Excitation
Timing charts may be simplified for explanatory purposes.
150
C
B
A
A
B
C
D
E
F
G
H
100
B PHASE
50
H
D
0
-150
-100
-50
0
50
100
PHASE A
H
X
L
L
L
X
H
H
A PHASE
Input
IN A1
IN A2
H
H
L
L
H
H
H
H
H
H
L
L
H
H
H
H
Output
IOUT(A) PHASE B
100%
H
0%
H
-100%
H
-100%
X
-100%
L
0%
L
100%
L
100%
X
BPHASE
Input
IN B1
IN B2
H
H
H
H
H
H
L
L
H
H
H
H
H
H
L
L
Output
IOUT(B)
100%
100%
100%
0%
-100%
-100%
-100%
0%
150
-50
F
E
G
-100
-150
A PHASE
G
H
A
B
C
D
E
F
G
H
A
B
C
D
E
100%
IOUT(A)
0%
-100%
100%
IOUT(B)
0%
-100%
PHASE_A
IN_A1
IN_A2
PHASE_B
IN_B1
IN_B2
H
L
H
L
H
L
H
L
H
L
H
L
18
2012-03-12
TB62218AFG/AFTG
W1-2-Phase Excitation
Timing charts may be simplified for explanatory purposes.
150
D
B
100
E
F
B PHASE
C
A
P
50
O
G
0
-150
H
-100
-50
0
50
100
-50
I
J
-100
K
M
L
N
150
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
PHASE A
H
H
X
L
L
L
L
L
L
L
X
H
H
H
H
H
A PHASE
Input
IN A1
IN A2
H
L
L
H
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
H
L
L
L
H
H
L
H
H
H
H
H
H
Output
IOUT(A) PHASE B
71%
H
38%
H
0%
H
-38%
H
-71%
H
-100%
H
-100%
X
-100%
L
-71%
L
-38%
L
0%
L
38%
L
71%
L
100%
L
100%
X
100%
H
B PHASE
Input
IN B1
IN B2
H
L
H
H
H
H
H
H
H
L
L
H
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
H
L
L
L
H
Output
IOUT(B)
71%
100%
100%
100%
71%
38%
0%
-38%
-71%
-100%
-100%
-100%
-71%
-38%
0%
38%
-150
A PHASE
N O P A BCD E F G H I J K L MN O P A BCD E F G H I J K L MN O P A
IOUT_A
IOUT_B
PHASE_A
IN_A1
100%
71%
38%
0%
-38%
-71%
71%
38%
0%
-38%
-71%
-100%
H
H
L
IN_A2
H
L
PHASE_B
IN_B1
H
L
H
L
IN_B2
H
L
19
2012-03-12
TB62218AFG/AFTG
Overcurrent Shutdown (ISD) Circuitry
ISD Masking Time and ISD On-Time
OSC_M oscillation
(chopper waveform)
min
min
ISD masking time
max
Disabled (reset state)
max
ISD on-time
1 chopping cycle
An overcurrent starts flowing into the output transistors
The overcurrent shutdown (ISD) circuitry has a masking time to prevent current spikes during Irr and
switching from erroneously tripping the ISD circuitry. The masking time is a function of the chopper frequency
obtained by CR:
masking_time = 4 × CR_frequency
The minimum and maximum times taken to turn off the output transistors since an overcurrent flows into
them are:
Min: 4 × CR_frequency
Max: 8 × CR_frequency
It should be noted that these values assume a case in which an overcurrent condition is detected in an ideal
manner. The ISD circuitry might not work, depending on the control timing of the output transistors.
Therefore, a protection fuse must always be added to the VM power supply as a safety precaution. The
optimal fuse capacitance varies with usage conditions, and one that does not adversely affect the motor
operation or exceed the power dissipation rating of the TB62218AFG/AFTG should be selected.
Calculating OSCM Oscillating Frequency
The OSCM oscillating frequency can be approximated using the following equation:
f OSCM =
1
0.56 × C × (R 1 + 500 )
Where:
C = Capacitor capacity
R1= Resistance
−12
Assigning C = 270 × 10 [F], R1= 3600 [Ω] to get:
6
fOSCM = 1.61 × 10 ⇒ 1.6 MHz
20
2012-03-12
TB62218AFG/AFTG
Example Application Circuits
TB62218AFG
0.1 μF
18
17
16
GND
19
OUT_B
20
GND
21
NC
Fin(GND)
OUT_B
0.51 Ω
0.1 μF
22
NC
23
RS_B
24
Vcc
25
NC
26
NC
0.1 μF
27
Vref_B
Vref_A
OSCM
28
24 V
100 μF
3.6 kΩ
VM
270 pF
The values shown in the following figure are typical values. For input conditions, see Operating Ranges.
15
13
GND
12
OUT_A
11
GND
10
NC
9
OUT_A
8
NC
Fin(GND)
RS_A
7
14
0.51 Ω
6
STANDBY
5
IN_B2
4
IN_B1
3
PHASE_B
2
PHASE_A
1
IN_A2
IN_A1
M
5V
5V
5V
5V
5V
5V
5V
3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
0V
0V
0V
0V
0V
0V
0V
Note: Bypass capacitors should be added as necessary.
It is recommended to use a single ground plane for the entire board whenever possible, and a grounding method
should be considered for efficient heat dissipation.
In cases where mode setting pins are controlled via switches, either pull-down or pull-up resistors should be
added to them to avoid floating states.
For a description of the input values, see the output function tables.
The above application circuit example is presented only as a guide and should be fully evaluated prior to
production. Also, no intellectual property right is ceded in any way whatsoever in regard to its use.
The external components in the above diagram are used to test the electrical characteristics of the device: it is
not guaranteed that no system malfunction or failure will occur.
Careful attention should be paid to the layout of the output, VDD (VM) and GND traces to avoid short-circuits across output pins or to
the power supply or ground. If such a short-circuit occurs, the TB62218AFG/AFTG may be permanently damaged. Also, if the device is
installed in a wrong orientation, a high voltage might be applied to components with lower voltage ratings, causing them to be
damaged. The TB62218AFG/AFTG does not have an overvoltage protection circuit. Thus, if a voltage exceeding the rated maximum
voltage is applied, the TB62218AFG/AFTG will be damaged; it should be ensured that it is used within the specified operating
conditions.
21
2012-03-12
TB62218AFG/AFTG
TB62218AFTG
32
31
30
29
28
27
26
NC
OUT_B
OUT_B
NC
RS_B2
0.51 Ω
RS_B1
0.1 μF
NC
VM
NC
100 μF
VCC
NC
33
25
23 NC
NC 39
22
GND
40
21 OUT_B1
41
20
Vref_A 42
19
0.1 μF
OUT_B2
GND
GND
18
44
17
45
16
5V
46
3.3 V PHASE_A
15
5V
47
3.3 V PHASE_B
14 NC
NC 48
13 NC
9
10
11
M
OUT_A2
OUT_A1
GND
12
NC
8
OUT_A2
7
OUT_A1
6
RS_A2
5
0.51 Ω
4
RS_A1
3
NC
2
IN_B1
NC
1
GND
IN_A2
STAND BY
5V
3.3 V
IN_A1
IN_B2
5V
3.3 V
270 pF
43
3.6 kΩ
0V
34
NC 38
OSCM
0V
35
24 NC
Vref_B
0V
36
24 V
NC 37
GND
0V
NC
0.1 μF
The values shown in the following figure are typical values. For input conditions, see Operating Ranges.
5V
5V
5V
3.3 V 3.3 V 3.3 V
0V
0V
0V
Note: Bypass capacitors should be added as necessary.
It is recommended to use a single ground plane for the entire board whenever possible, and a grounding method
should be considered for efficient heat dissipation.
In cases where mode setting pins are controlled via switches, either pull-down or pull-up resistors should be
added to them to avoid floating states.
For a description of the input values, see the output function tables.
The above application circuit example is presented only as a guide and should be fully evaluated prior to
production. Also, no intellectual property right is ceded in any way whatsoever in regard to its use.
The external components in the above diagram are used to test the electrical characteristics of the device: it is
not guaranteed that no system malfunction or failure will occur.
Careful attention should be paid to the layout of the output, VDD (VM) and GND traces to avoid short-circuits across output pins or to
the power supply or ground. If such a short-circuit occurs, the TB62218AFG/AFTG may be permanently damaged. Also, if the device is
installed in a wrong orientation, a high voltage might be applied to components with lower voltage ratings, causing them to be
damaged. The TB62218AFG/AFTG does not have an overvoltage protection circuit. Thus, if a voltage exceeding the rated maximum
voltage is applied, the TB62218AFG/AFTG will be damaged; it should be ensured that it is used within the specified operating
conditions.
22
2012-03-12
TB62218AFG/AFTG
Package Dimensions
Weight: 0.79 g (typ.)
23
2012-03-12
TB62218AFG/AFTG
QFN48-P-0707-0.5
Unit: mm
Pin#1 Index Mark Area
Backside heatsink: 5.4 mm × 5.4 mm
Corner chamfers: C0.5
Chamfer radius: 3-R0.2
Weight: 0.14 g (typ.)
Foot Pattern Example (double- sided board)
Surface
Bottom
Black dots: 0.2 mm through holes
24
2012-03-12
TB62218AFG/AFTG
Notes on Contents
1. Block Diagrams
Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for
explanatory purposes.
2. Equivalent Circuits
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory
purposes.
3. Timing Charts
Timing charts may be simplified for explanatory purposes.
4. Example Application Circuits
The example application circuits shown in this document are provided for reference only. Thorough
evaluation and testing should be implemented when designing your application's mass production design.
In providing these example application circuits, Toshiba does not grant the use of any industrial property
rights.
5. Test Circuits
Components in the test circuits are used only to obtain and confirm the device characteristics. These
components and circuits are not guaranteed to prevent malfunction or failure from occurring in the
application equipment.
IC Usage Considerations
Notes on handling of ICs
(1)
The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded,
even for a moment. Do not exceed any of these ratings.
Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result
injury by explosion or combustion.
(2)
Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case
of over current and/or IC failure. The IC will fully break down when used under conditions that exceed
its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise
occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead
smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown,
appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required.
(3)
If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the
design to prevent device malfunction or breakdown caused by the current resulting from the inrush
current at power ON or the negative current resulting from the back electromotive force at power OFF.
IC breakdown may cause injury, smoke or ignition.
Use a stable power supply with ICs with built-in protection functions. If the power supply is unstable,
the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke
or ignition.
(4)
Do not insert devices incorrectly or in the wrong orientation.
Make sure that the positive and negative terminals of power supplies are connected properly.
Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding
the rating(s) may cause breakdown, damage or deterioration of the device, and may result in injury by
explosion or combustion.
In addition, do not use any device that has had current applied to it while inserted incorrectly or in the
wrong orientation even once.
(5)
Carefully select power amp, regulator, or other external components (such as inputs and negative
feedback capacitors) and load components (such as speakers).
If there is a large amount of leakage current such as input or negative feedback capacitors, the IC
output DC voltage will increase. If this output voltage is connected to a speaker with low input
withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause
smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied Load
(BTL) connection type IC that inputs output DC voltage to a speaker directly.
25
2012-03-12
TB62218AFG/AFTG
Points to remember on handling of ICs
Over current Protection Circuit
Over current protection circuits (referred to as current limiter circuits) do not necessarily protect ICs
under all circumstances. If the Over current protection circuits operate against the over current, clear
the over current status immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can
cause the over current protection circuit to not operate properly or IC breakdown before operation. In
addition, depending on the method of use and usage conditions, if over current continues to flow for a
long time after operation, the IC may generate heat resulting in breakdown.
Thermal Shutdown Circuit
Thermal shutdown circuits do not necessarily protect ICs under all circumstances. If the thermal
shutdown circuits operate against the over temperature, clear the heat generation status immediately.
Depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can
cause the thermal shutdown circuit to not operate properly or IC breakdown before operation.
Heat Dissipation Design
In using an IC with large current flow such as a power amp, regulator or driver, please design the device
so that heat is appropriately dissipated, not to exceed the specified junction temperature (Tj) at any
time or under any condition. These ICs generate heat even during normal use. An inadequate IC heat
dissipation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In
addition, please design the device taking into consideration the effect of IC heat dissipation on
peripheral components..
Back-EMF
When a motor rotates in the reverse direction, stops or slows down abruptly, a current flow back to the
motor’s power supply due to the effect of back-EMF. If the current sink capability of the power supply is
small, the device’s motor power supply and output pins might be exposed to conditions beyond absolute
maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in your system
design.
26
2012-03-12
TB62218AFG/AFTG
RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information in
this document, and related hardware, software and systems (collectively “Product”) without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with
TOSHIBA’s written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product’s quality and reliability, Product can malfunction or fail. Customers are
responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product,
or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant
TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product
and the precautions and conditions set forth in the “TOSHIBA Semiconductor Reliability Handbook” and (b) the instructions for the
application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design
or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications;
(b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs,
algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs
and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS’ PRODUCT DESIGN OR APPLICATIONS.
• Product is intended for use in general electronics applications (e.g., computers, personal equipment, office equipment, measuring
equipment, industrial robots and home electronics appliances) or for specific applications as expressly stated in this document. Product
is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability
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• ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE
FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY WHATSOEVER,
INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS,
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DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE
OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A
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• Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation,
for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology
products (mass destruction weapons). Product and related software and technology may be controlled under the Japanese Foreign
Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software
or technology are strictly prohibited except in compliance with all applicable export laws and regulations.
• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product.
Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances,
including without limitation, the EU RoHS Directive. TOSHIBA assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
27
2012-03-12
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