MX26C1000APC-70

INDEX MX26C1000A 1M-BIT [128K x 8] CMOS MULTIPLE-TIME-PROGRAMMABLE-EPROM FEATURES • • • • • • • 128K x 8 organization +5V operating power supply +12.75V program/erase voltage Electric erase instead of UV light erase Fast access time: 70/90/100/120/150 ns Totally static operation Completely TTL compatible • • • • Operating current: 30mA Standby current: 100uA 100 minimum erase/program cycles Package type: - 32 pin PDIP Y - 32 pin SOP LOG - 32 pin PLCC NO - 32 pin TSOP(I) ECH GENERAL DESCRIPTION The MX26C1000A is a 12.75V/5V, 1M-bit MTP EPROMTM (Multiple Time Programmable Read Only Memory). It is organized as 128K words by 8 bits per word, operates from a + 5 volt supply, has a static standby mode, and features fast address location programming. It is designed to be reprogrammed and erased by an EPROM programmer or on-board. All programming/erasing signals are TTL levels, requiring a NTE ATE P DT single pulse. The MX26C1000A supports an intelligent quick pulse programming algorithm which can result in a programming time of less than 30 seconds. This MTP EPROMTM is packaged in industry standard 32 pin dual-in-line packages, 32 pinPLCC packages or 32 pin TSOP packages and 32 pin SOP packages. PIN CONFIGURATIONS PGM BLOCK DIAGRAM CE CONTROL LOGIC OUTPUT BUFFERS PDIP/SOP VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC PGM NC A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3 PLCC VCC VPP A12 A15 A16 NC Q0~Q7 OE A7 A6 A5 A4 A3 A2 A1 A0 Q0 5 4 1 32 30 29 A14 A13 A8 A9 A0~A16 ADDRESS INPUTS . . . . . . . . Y-DECODER . . . . . . . . Y-SELECT MX26C1000A 9 MX26C1000A 25 A11 OE A10 CE X-DECODER 1M BIT CELL MAXTRIX 13 14 Q1 Q2 GND 17 Q3 Q4 Q5 21 20 Q6 Q7 VCC GND VPP TSOP A3 A2 A1 A0 Q0 Q1 Q2 GND Q3 Q4 Q5 Q6 Q7 CE A10 OE 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A4 A5 A6 A7 A12 A15 A16 VPP VCC PGM NC A14 A13 A8 A9 A11 PIN DESCRIPTION SYMBOL A0~A16 Q0~Q7 CE OE VPP NC VCC GND PIN NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Program Supply Voltage No Internal Connection Power Supply Pin (+5V) Ground Pin MX261000A P/N: PM0454 Patent#: US#5,526,307 1 REV.1.5, FEB 10, 1998 INDEX MX26C1000A FUNCTIONAL DESCRIPTION When the MX26C1000A is delivered, or it is erased, the chip has all 1000K bits in the "ONE", or HIGH state. "ZEROs" are loaded into the MX26C1000 through the procedure of programming. ERASE MODE The MX26C1000A is erased by an EPROM programmer or in-system. The device is set up in erase mode when the A9 = VPP = 12.75V are applied, with VCC = 5V and PGM = VIL.(Algorithm shown in Figure 3). Erase time is around 1sec. If the erase is not verified, an additional erase processes will be repeated for a maximum of 200 times. PROGRAMMING MODE PROGRAMMING ALGORITHM The MX26C1000A is programmed by an EPROM programmer or on-board. The device is set up in the programming mode when the programming voltage VPP = 12.75V is applied, with VCC = 5 V and PGM = VIH (Algorithm shown in Figure 1). Programming is achieved by applying a single TTL low level 25us pulse to the PGM input after addresses and data lines are stable. If the data is not verified, additional pulses are applied for a maximum of 20 pulses. After the data is verified, one 25us pulse is applied to overprogram the byte so that program margin is assured. This process is repeated while sequencing through each address of the device. When programming is completed, the data at all the address is verified at VCC = VPP = 5V ± 10%. The VCC supply of the MXIC On-Board Programming Algorithm is designed to be 5V ± 10% particularly to faciliate the programming operation under the on-board application environment. But it can also be implemented in an industrial-standard EPROM programmer. PROGRAM INHIBIT MODE Programming of multiple MX26C1000s in parallel with different data is also easily accomplished by using the Program Inhibit Mode. Except for CE and OE, all like inputs of the parallel MX26C1000 may be common. A TTL low-level program pulse applied to an MX26C1000A CE input with VPP = 12.75 ± 0.25 V and PGM LOW will program that MX26C1000A. A high-level CE input inhibits the other MX26C1000A from being programmed. PROGRAM VERIFY MODE Verification should be performed on the programmed bits to determine that they were correctly programmed. Verification should be performed with OE and CE, at VIL, PGM at VIH, and VPP at its programming voltage. ERASE VERIFY MODE COMPATIBILITY WITH MX27C1000 FAST PROGRAMMING ALGORITHM Besides the On-Board Programming Algorithm, the Fast Programming Algorithm of MX27C1000 also applies to MX26C1000A. MXIC Fast Algorithm is the conventional EPROM programming algorithm and is available in industrial-standard EPROM programmers. A user of industrial-standard EPROM programmer can choose either of the algorithms base on his preference. The device is set up in the fast programming mode when the programming voltage VPP = 12.75V is applted, with VCC = 6.25V and PGM = VIL(or OE = VIH)(Algorithm is shown in Figure 2). The programming is achieved by applying a single TTL low level 25~100us pulse is applied for a maximum of 25 pulses. This process is repeated while sequencing through each address of the device. When the programming mode is completed, the data in all address is verified at VCC = VPP = 5V ± 10%. Verification should be performed on the erased chip to determine that the whole chip(all bits) was correctly erased. Verification should be performed with OE and CE at VIL, PGM at VIH, and VCC = 5V, VPP = 12.5V AUTO IDENTIFY MODE The auto identify mode allows the reading out of a binary code from an MTP that will identify its manufacturer and device type. This mode is intended for use by the programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25° ± 5°C ambient temperature range C that is required when programming the MX26C1000A. To activate this mode, the programming equipment must force 12.75V on address line A9 of the device. Two P/N: PM0454 Patent#: US#5,526,307 2 REV.1.5, FEB 10, 1998 INDEX MX26C1000A identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at VIL during auto identify mode. Byte 0 ( A0 = VIL) represents the manufacturer code, and byte 1 (A0 = VIH), the device identifier code. For the MX26C1000A, these two identifier bytes are given in the Mode Select Table. All identifiers for the manufacturer and device codes will possess odd parity, with the MSB (DQ7) defined as the parity bit. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. SYSTEM CONSIDERATIONS During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. At a minimum, a 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between VCC and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EPROM arrays, a 4.7 uF bulk electrolytic capacitor should be used between VCC and GND for each of the eight devices. The location of the capacitor should be close to where the power supply is connected to the array. READ MODE The MX26C1000A has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tACC - tOE. STANDBY MODE The MX26C1000A has a CMOS standby mode which reduces the maximum VCC current to 100 uA. It is placed in CMOS standby when CE is at VCC ± 0.3 V. The MX26C1000A also has a TTL-standby mode which reduces the maximum VCC current to 1.5 mA. It is placed in TTL-standby when CE is at VIH. When in standby mode, the outputs are in a high-impedance state, independent of the OE input. TWO-LINE OUTPUT CONTROL FUNCTION To accommodate multiple memory connections, a twoline control function is provided to allow for: 1. Low memory power dissipation, 2. Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. P/N: PM0454 Patent#: US#5,526,307 3 REV.1.5, FEB 10, 1998 INDEX MX26C1000A MODE SELECT TABLE PINS MODE Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Erase Erase Verify Program Inhibit Manufacturer Code Device Code(26C1000) CE VIL VIL VIH VCC VIL VIL VIL VIL VIH VIL VIL OE VIL VIH X X VIH VIL VIH VIL X VIL VIL PGM X X X X VIL VIH VIL VIH X X X A0 X X X X X X X X X VIL VIH A9 X X X X X X VPP X X VH VH VPP VCC VCC VCC VCC VPP VPP VPP VPP VPP VCC VCC OUTPUTS DOUT High Z High Z High Z DIN DOUT HIGH Z DOUT High Z C2H D2H NOTES: 1. VH = 12.0 V ± 0.5 V 2. X = Either VIH or VIL(For auto select) 3. A1 - A8 = A10 - A16 = VIL(For auto select) 4. See DC Programming Characteristics for VPP voltage during programming. FIGURE 1. PROGRAMMING FLOW CHART START ADDRESS = FIRST LOCATION VCC = 5V VPP = 12.75V X=0 PROGRAM ONE 25us PULSE INTERACTIVE SECTION INCREMENT X YES X = 20 ? NO FAIL VERIFY BYTE ? PROGRAM ONE 25us PULSE PASS NO INCREMENT ADDRESS LAST ADDRESS FAIL PROGRAM ONE 25us PULSE YES VERIFY SECTION VCC = VPP = 5V VERIFY ALL BYTES ? FAIL DEVICE FAILED PASS DEVICE PASSED P/N: PM0454 Patent#: US#5,526,307 4 REV.1.5, FEB 10, 1998 INDEX MX26C1000A FIGURE 2. COMPATIBILITY WITH MX27C1000 FAST PROGRAMMING FLOW CHART START ADDRESS = FIRST LOCATION VCC = 6.25V VPP = 12.75V X=0 PROGRAM ONE 25~100us PULSE INTERACTIVE SECTION INCREMENT X YES X = 25? NO FAIL VERIFY BYTE ? PASS NO INCREMENT ADDRESS LAST ADDRESS FAIL YES VCC = VPP = 5.25V VERIFY SECTION VERIFY ALL BYTES ? FAIL DEVICE FAILED PASS DEVICE PASSED P/N: PM0454 Patent#: US#5,526,307 5 REV.1.5, FEB 10, 1998 INDEX MX26C1000A FIGURE 3. ERASING MODE FLOW CHART START X=0 PROGRAM ALL "0" A9 = 12.75V VCC = 5V VPP = 12.75V CHIP ERASE (0.5s) A9 = VIL or VIH VCC = 5V VPP = 12.75V All Bits Verify NO FAIL ERASE VERIFY ? INCREMENT X X = 200 ? YES PASS CHIP ERASE (0.5s) DEVICE FAILED DEVICE PASSED P/N: PM0454 Patent#: US#5,526,307 6 REV.1.5, FEB 10, 1998 INDEX MX26C1000A SWITCHING TEST CIRCUITS DEVICE UNDER TEST 1.8K ohm +5V CL 6.2K ohm DIODES = IN3064 OR EQUIVALENT CL = 100 pF including jig capacitance(30pF for 70 ns parts) SWITCHING TEST WAVEFORMS 3.0V 1.5V 0V TEST POINTS INPUT OUTPUT 1.5V AC TESTING: (1) Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0". Input pulse rise and fall times are < 10ns. (2) For MX26C1000A P/N: PM0454 Patent#: US#5,526,307 7 REV.1.5, FEB 10, 1998 INDEX MX26C1000A ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 & Vpp VALUE 0oC to 70oC -65oC to 125oC -0.5V to 7.0V -0.5V to VCC + 0.5V -0.5V to 7.0V -0.5V to 13.5V NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. NOTICE: Specifications contained within the following tables are subject to change. DC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ± 10% SYMBOL VOH VOL VIH VIL ILI ILO ICC3 ICC2 ICC1 IPP PARAMETER Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VCC Power-Down Current VCC Standby Current VCC Active Current VPP Supply Current Read 2.0 -0.3 -10 -10 MIN. 2.4 0.4 VCC + 0.5 0.8 10 10 100 1.5 30 100 MAX. UNIT V V V V uA uA uA mA mA uA VIN = 0 to 5.5V VOUT = 0 to 5.5V CE = VCC ± 0.3V CE = VIH CE = VIL, f=5MHz, Iout = 0mA CE = OE = VIL, VPP = 5.5V CONDITIONS IOH = -0.4mA IOL = 2.1mA CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only) SYMBOL CIN COUT CVPP PARAMETER Input Capacitance Output Capacitance VPP Capacitance TYP. 8 8 18 MAX. 8 12 25 UNIT pF pF pF CONDITIONS VIN = 0V VOUT = 0V VPP = 0V P/N: PM0454 Patent#: US#5,526,307 8 REV.1.5, FEB 10, 1998 INDEX MX26C1000A AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V± 10% 26C1000A -70 SYMBOL tACC tCE tOE tDF tOH PARAMETER Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay OE High to Output Float, or CE High to Output Float Output Hold from Address, CE or OE which ever occurred firs MIN. MAX. 70 70 35 20 MIN. 26C1000A -90 MAX. 90 90 40 25 UNIT ns ns ns ns ns CONDITIONS CE = OE = VIL OE = VIL CE = VIL 0 0 0 0 26C1000A -10 SYMBOL tACC tCE tOE tDF tOH PARAMETER Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay OE High to Output Float, MIN. MAX. 100 100 45 30 26C1000A -12 MIN. MAX. 120 120 50 35 26C1000A -15 MIN. MAX. 150 150 65 50 UNIT ns ns ns ns ns CONDITIONS CE = OE = VIL OE = VIL CE = VIL 0 0 0 0 0 or CE High to Output Float Output Hold from Address, 0 CE or OE which ever occurred first DC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5°C SYMBOL VOH VOL VIH VIL ILI VH ICC3 IPP2 PARAMETER Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current A9 Auto Select Voltage VCC Supply Current (Program/Erase & Verify) VPP Supply Current(Program)/Erase 2.0 -0.3 -10 11.5 MIN. 2.4 0.4 VCC + 0.5 0.8 10 12.5 50 50 MAX. UNIT V V V V uA V mA mA CE = PGM = VIL, OE = VIH VCC2 VPP2 IPP A9 Programming & Erase Supply Voltage Programming & Erase Voltage A9 Auto Select Current /Erase 4.5 12.5 6.5 13.0 1 V V mA CE = PGM = VIL, OE = VIH VIN = 0 to 5.5V CONDITIONS IOH = -0.40mA IOL = 2.1mA P/N: PM0454 Patent#: US#5,526,307 9 REV.1.5, FEB 10, 1998 INDEX MX26C1000A AC PROGRAMMING CHARACTERISTICS TA = 25oC ± 5oC SYMBOL tAS tOES tDS tAH tDH tDFP tVPS tPW tVCS tDV tCES tOE tER tPR tEW tEV tPV tA9S tPVS tEVS PARAMETER Address Setup Time OE Setup Time Data Setup Time Address Hold Time Data Hold Time CE to Output Float Delay VPP Setup Time Program Pulse Width VCC Setup Time Data Valid from CE CE Setup Time Data valid from OE Erase Recovery Time Program Recovery Time Erase Pulse Width Erase Verify Time Program Verify Time A9 Setup Time Program Verify Setup Erase Verify Setup 2.0 2 0.5 0.5 2 0.5 200 200 2.0 150 MIN. 2.0 2.0 2.0 0 2.0 0 2.0 20 2.0 250 105 130 MAX. UNIT us us us us us ns us us us ns us ns s us s ns ns us us s CONDITIONS WAVEFORMS READ CYCLE ADDRESS INPUTS tACC DATA ADDRESS CE tCE OE tDF DATA OUT tOE VALID DATA tOH P/N: PM0454 Patent#: US#5,526,307 10 REV.1.5, FEB 10, 1998 INDEX MX26C1000A PROGRAMMING WAVEFORMS PROGRAM PROGRAM VERIFY ADDRESS INPUTS VIH VALID ADDRESS VIL tAS DATA OUT tDS VPP DATA IN STABLE tDH DATA OUT VALID VPP VCC tVPS VCC+1 VCC VCC tVCS tPVS tPV VIH CE VIL tCES VIH PGM VIL tPW VIH tPR OE VIL ERASE WAVEFORMS Erase VPP A9 Erase Verify ADDRESS INPUTS VIH Others Not Care VIL DATA OUT VPP OUT VPP VCC VIH tVPS tEVS OE VIL tEV VIH CE VIL tCES tER PGM VIH VIL tEW P/N: PM0454 Patent#: US#5,526,307 11 REV.1.5, FEB 10, 1998 INDEX MX26C1000A ORDERING INFORMATION PLASTIC PACKAGE PART NO. ACCESS TIME(ns) OPERATING CURRENT MAX.(mA) 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 STANDBY CURRENT MAX.(uA) 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 PACKAGE 32 Pin DIP 32 Pin SOP 32 Pin PLCC 32 Pin TSOP 32 Pin DIP 32 Pin SOP 32 Pin PLCC 32 Pin TSOP 32 Pin DIP 32 Pin SOP 32 Pin PLCC 32 Pin TSOP 32 Pin DIP 32 Pin SOP 32 Pin PLCC 32 Pin TSOP 32 Pin DIP 32 Pin SOP 32 Pin PLCC 32 Pin TSOP MX26C1000APC-70 70 MX26C1000AMC-70 70 MX26C1000AQC-70 70 MX26C1000ATC-70 70 MX26C1000APC-90 90 MX26C1000AMC-90 90 MX26C1000AQC-90 90 MX26C1000ATC-90 90 MX26C1000APC-10 100 MX26C1000AMC-10 100 MX26C1000AQC-10 100 MX26C1000ATC-10 100 MX26C1000APC-12 120 MX26C1000AMC-12 120 MX26C1000AQC-12 120 MX26C1000ATC-12 120 MX26C1000APC-15 150 MX26C1000AMC-15 150 MX26C1000AQC-15 150 MX26C1000ATC-15 150 P/N: PM0454 Patent#: US#5,526,307 12 REV.1.5, FEB 10, 1998 INDEX MX26C1000A PACKAGE INFORMATION 32-PIN PLASTIC DIP(600 mil) ITEM A B C D E F G H I J K L M NOTE: MILLIMETERS 42.13 max. 1.90 [REF] 2.54 [TP] .46 [Typ.] 38.07 1.27 [Typ.] 3.30 ± .25 .51 [REF] 3.94 ± .25 5.33 max. 15.22 ± .25 13.97 ± .25 .25 [Typ.] INCHES 1.660 max. .075 [REF] .100 [TP] .018 [Typ.] 1.500 .050 [Typ.] .130 ± .010 .020 [REF] .155 ± .010 .210 max. .600 ± .010 .550 ± .010 .010 [Typ.] 32 17 1 A 16 K L I H F D E J G C B M 0~15¡ Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition. 32-PIN PLASTIC LEADED CHIP CARRIER (PLCC) A B 1 ITEM A B C D E F G H I J K L M N NOTE: MILLIMETERS 12.44 ± .13 11.50 ± .13 14.04 ± .13 14.98 ± .13 1.93 3.30 ± .25 2.03 ± .13 .51 ± .13 1.27 [Typ.] .71[REF] .46 [REF] 10.40/12.94 (W) (L) .89 R .25 (TYP.) INCHES .490 ± .005 .453 ± .005 .553 ± .005 .590 ± .005 .076 .130 ± .010 .080 ± .005 .020 ± .005 .050 [Typ.] .028[REF] .018 [REF] .410/.510 (W) (L) .035 R .010 (TYP.) F G 13 9 5 4 32 30 29 25 C D 21 14 20 E N 17 H I K L M J Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition. P/N: PM0454 Patent#: US#5,526,307 13 REV.1.5, FEB 10, 1998 INDEX MX26C1000A PACKAGE INFORMATION 32-PIN PLASTIC TSOP ITEM A B C D E F G H I J K L M N O NOTE: MILLIMETERS 20.0 ± .20 18.40 ± .10 8.20 max. 0.15 [Typ.] .80 [Typ.] .20 ± .10 .30 ± .10 .50 [Typ.] .45 max. 0 ~ .20 1.00 ± .10 1.27 max. .50 19.00 0~5 INCHES .078 ± .006 .724 ± .004 .323 max. .006 [Typ.] .031 [Typ.] .008 ± .004 .012 ± .004 .020 [Typ.] .018 max. 0 ~ .008 .039 ± .004 .050 max. .020 .748 .500 K D E F G H I J L O M N C A B Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at a maximum material condition. 32-PIN PLASTIC SOP (450 mil) ITEM A B C D E F G H I J K L NOTE: MILLIMETERS 20.95 max. 1.00 [REF] 1.27 [TP] .40 [Typ.] .05 min. 3.05 max. 2.69 ± .13 14.12 ± .25 11.30 ± .13 1.42 .20 [Typ.] .79 INCHES .825 max. .039 [REF] .050 [TP] .016 [Typ.] .002 min. .120 max. .106 ± .005 .556 ± .010 .445 ± .005 .056 .008 [Typ.] .031 32 17 1 A 16 H I J G F K E Each lead centerline is located within .25 mm[.01 inch] of its true position [TP] at maximum material condition. D C B L P/N: PM0454 Patent#: US#5,526,307 14 REV.1.5, FEB 10, 1998 INDEX MX26C1000A Revision History Revision # 1.1 1.2 Description Eraseing mode flow chart: Chip erase(5s)---> (1s). Programming waveforms: CE changed. MTP ROM----> MTP EPROM Chip erase(1s)---->0.5s. X = 60?--->200? Switching Test Waveforms revise. tEW Erase Pulse Width 1 sec---> 0.5sec Programming/erase waveforms modifiction. VPP: from 12.0~13V to 12.5~13V. Erase Verify Time: 60---->200. Change Part Name: 26C1000 ---> 26C1000A Change tPW:Min. 95us --> Min. 20us Programming flow chart revised. Date 4/10/1997 5/30/1997 ` 1.3 1.4 1.5 7/25/1997 11/05/1997 2/10/1998 Mode Select Table, Erase Mode A9=VH-->A9=VPP. Erase flow chart revised. P/N: PM0454 Patent#: US#5,526,307 15 REV.1.5, FEB 10, 1998 INDEX MX26C1000A MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-8888 FAX:+886-3-578-8887 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-747-2309 FAX:+65-748-4090 TAIPEI OFFICE: TEL:+886-3-509-3300 FAX:+886-3-509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. 16