ML2722

ML2722 900MHz Low-IF 1.5Mbps FSK Transceiver Final Datasheet GENERAL DESCRIPTION The ML2722 is a fully integrated 1.5Mbps frequency shift keyed (FSK) transceiver that operates in the unlicensed 900MHz ISM frequency band. The device has been optimized for digital cordless telephone applications and includes all the frequency generation, receive and transmit functions. Automatically adjusted filters eliminate mechanical tuning. The transmitter generates a -1dBm FSK output signal. The single conversion Low-IF receiver has all the sensitivity and selectively advantages of a traditional superheterodyne without requiring costly, bulky external filters, while providing the integration advantages of direct conversion. The phase locked loop (PLL) synthesizer is completely integrated, including the voltage controlled oscillator (VCO), tuning circuits, and VCO resonator. This allows the ML2722 to be used in frequency hopped spread spectrum (FHSS) applications. The ML2722 contains internal voltage regulation. It also contains PLL and transmitter configuration registers. The device can be placed in a low power standby mode for current sensitive applications. It is packaged in a “Green” Pb-Free 32TQFP. FEATURES Single chip ISM band 900MHz Radio Transceiver with -1dBm transmit output power 1.5Mbps maximum data rate Typical receiver sensitivity: -95dBm at 12.5% CER Fully integrated frequency synthesizer with internal VCO resonator Automatic filter calibration: Requires no mechanical tuning adjustments during manufacturing Low IF Receiver: No external IF filters required Control outputs correctly sequence and control external PA 3-wire control interface Analog RSSI output APPLICATIONS 900MHz FSK Data Transceivers Digital Cordless Phones Wireless Streaming Media Wireless PC Peripherals PIN CONFIGURATION RSSI/TPI RVCC7 RVCC6 DOUT GND VBG VDD DIN BLOCK DIAGRAM XCEN RXON PAON EN DATA CLK TPC/TPQ VSS 32 31 30 29 28 27 26 25 1 24 2 3 4 5 6 7 8 9 23 22 21 20 19 18 17 10 11 12 13 14 15 16 VCC5 TRFO RVCC4 RRFI GND GND GND GND REF RVCC1 RVCC3 VTUNE VCC2 QPO GND ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE ML2722DH ML2722DH-T -10 C to +60 C -10oC to +60 oC o o PACKAGE 32TQFP 7x7x1mm 32TQFP 7x7x1mm GND PACK (QTY) Antistatic Tray (250) Tape & Reel (2500) DS2722-F-06 DECEMBER 2005 ML2722 TABLE OF CONTENTS GENERAL DESCRIPTION ........................................................................................................................................... 1 PIN CONFIGURATION ................................................................................................................................................. 1 ORDERING INFORMATION ........................................................................................................................................ 1 FEATURES ................................................................................................................................................................... 1 APPLICATIONS ............................................................................................................................................................ 1 BLOCK DIAGRAM ........................................................................................................................................................ 1 TABLE OF CONTENTS ................................................................................................................................................ 2 SIMPLIFIED APPLICATIONS DIAGRAM ..................................................................................................................... 3 ELECTRICAL CHARACTERISTICS............................................................................................................................. 4 PIN DESCRIPTIONS.................................................................................................................................................... 7 FUNCTIONAL DESCRIPTION ................................................................................................................................... 13 MODES OF OPERATION........................................................................................................................................... 15 CONTROL INTERFACES........................................................................................................................................... 18 CONTROL INTERFACES AND REGISTER DESCRIPTIONS................................................................................... 20 PHYSICAL DIMENSIONS (INCHES/MILLIMETERS) ................................................................................................ 27 WARRANTY................................................................................................................................................................ 28 DS2722-F-06 FINAL DATASHEET DECEMBER 2005 2 ML2722 SIMPLIFIED APPLICATIONS DIAGRAM ML2722 DOUT IF DEMOD CIRCUITS RSSI REF ANTENNA LNA MATCHING NETWORK RRFI IMAGE REJECT MIXER PLL CLK, DATA, 3 EN BASEBAND IC RF PIN DIODE SWITCH SWITCH DRIVERS PAON, TPC 2 CONTROL LOGIC XCEN, 2 RXON PA FILTER TRFO QUADRATURE DIVIDE BY 2 TX DATA FILTER DIN VCC5 TX RF BUFFER 1.83GHz VCO BATTERY AND PROTECTION CIRCUITS VTUNE QPO LOOP FILTER Figure 1. Simplified Application Diagram DS2722-F-06 FINAL DATASHEET DECEMBER 2005 3 ML2722 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VDD, VCC5 ................................................................................................................................................................. 6.0V VSS, GND ............................................................................................................................................................. 0 ± 0.3V Junction Temperature............................................................................................................................................... 150°C Storage Temperature Range ...................................................................................................................... -65°C to 150°C Lead Temperature (Soldering, 10s).......................................................................................................................... 260°C OPERATING CONDITIONS Normal Temperature Range ......................................................................................................................... -10°C to 60°C VCC5 Range ...................................................................................................................................................2.7V to 4.5V Thermal Resistance (θJA)..................................................................................................................................... 100°C/W VDD Range (VCC5 ≥ VDD).............................................................................................................................2.7V to 4.5V Unless otherwise specified, VCC5 & VDD = 2.7V to 3.8V, TA = Operating Temperature Range (Note 1) 6.144 or 12.288MHz reference frequency input PARAMETER POWER CONSUMPTION ISTBY IRX, ITX IRX, ITX All Circuits, Standby Mode Receive or Transmit Mode Receive or Transmit Mode TA = 25°C, VCC5 & VDD = 3.3V TA = Operating Temperature Range 30 20 10 50 50 100 63.5 70 μA mA mA CONDITIONS MIN TYP MAX UNITS SYNTHESIZER fC ΦN LO output frequency Phase noise at driver output 1.2MHz 3MHz >7MHz LO PLL reference frequency at phase detector LO division range integer LO charge pump sink/source current LO lock up time for Transmit/Receive frequency change LO lock up time for channel switch LO lock up time from sleep Reference signal input level From RXON asserted In 512kHz steps VCO phase locked, loop bandwidth 50kHz. Discontinuities, other than reference spurs, not allowed. PLL main divider input is at 1.83GHz PLL divider limits 1024 5.5 50 902 -100 -120 -125 1.024 4093 928 MHz dBc/Hz MHz Count mA μs fREF N IP tTX2RX tFH tWAKE VFREF From EN asserted, any channel change in 902 to 928MHz band From XCEN, PLL dividers programmed 6.144 or 12.288MHz sine wave, capacitively coupled 2.0 100 240 3.0 μs μs Vp-p DS2722-F-06 FINAL DATASHEET DECEMBER 2005 4 ML2722 RECEIVER ZIN NF DRRX S BWRX PIMAX IIP3 IRR Receiver RF impedance Receiver RF noise figure Data Rate Input Sensitivity Bandwidth Maximum RX RF input Receiver input IP3 LO Leakage at RXI Receive RF mixer image rejection Adjacent channel rejection Measured at 3.5MHz offset -80dBm wanted signal 15 >15 >15 >15 tF tS tH tR tCK tD tSE CLK MSB DATA DB13 DB12 DB11 DB0 ADR1 LSB ADR0 tW REGISTER DATA (14 BITS) ADDRESS DATA (2 BITS) EN Figure 4. Serial Bus Timing for Address and Data Programming DS2722-F-06 FINAL DATASHEET DECEMBER 2005 19 ML2722 CONTROL INTERFACES AND REGISTER DESCRIPTIONS REGISTER INFORMATION A unidirectional 3-wire serial bus sets the ML2722’s transceiver parameters and programs the PLL circuits. Programming is performed by entering 16-bit words into the ML2722 serial interface. Three 16-bit registers are partitioned such that 14 bits are dedicated for data to program the operation and two bits identify the register address. The three registers are: Register 0: Register 1: Register 2: PLL Configuration Channel Frequency Data Internal Test Access Figure 5 shows a register map. Table 4 through Table 6 provide detailed diagrams of the register organization: Table 4 and Table 5 outline the PLL configuration and channel frequency registers, and Table 6 displays the filter tuning and test mode register. M SB D B13 Res. B15 D B12 Res. B14 D B11 R es. D B10 R es. D B9 R es. D B8 R es. B10 14-bit Data D B7 R es. DB6 Res. DB5 TPC B8 DB4 DB3 TXCL LOL B7 B6 DB2 D B1 RXCL RD0 B5 B4 D B0 QPP B3 2-bit Address ADR1 0 B2 ADR0 0 B1 B0 B13 B12 B11 B9 M SB D B13 Res. B15 D B12 D B11 D B10 D B9 D B8 14-bit Data D B7 DB6 DB5 DB4 DB3 DB2 D B1 D B0 2-bit Address ADR1 0 B1 ADR0 1 B0 Res. C HQ11 C HQ10 C HQ9 C HQ8 C HQ7 CHQ6 CHQ5 CHQ4 CHQ3 CHQ2 CHQ1 C HQ0 B14 B13 B12 B11 B10 B3 B2 B9 B8 B7 B6 B5 B4 M SB D B13 Res. B15 D B12 Res. B14 D B11 R es. D B10 R es. D B9 R es. D B8 R es. B10 14-bit Data D B7 R es. DB6 Res. DB5 DTM2 DB4 DTM1 DB3 DTM0 DB2 ATM2 D B1 ATM1 2-bit Address D B0 ADR1 ATM0 1 B2 ADR0 0 B1 B0 B13 B12 B11 B9 B8 B7 B6 B5 B4 B3 Figure 5. Register Organization DS2722-F-06 FINAL DATASHEET DECEMBER 2005 20 ML2722 DATA BIT B15 (MSB) / DB13 B14 / DB12 B13 / DB11 B12 / DB10 B11 / DB9 B10 / DB8 B9 / DB7 B8 / DB6 B7 / DB5 B6 / DB4 B5 / DB3 B4 / DB2 B3 / DB1 B2 / DB0 B1 / ADB1 B0 (LSB) / ADB0 NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TPC TXCL LOL RXCL RD0 QPP ADR1 ADR0 DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Transmit Power Control Transmit Test Mode PLL Frequency Shift PLL Mode in Normal Receive Operation Reference Frequency Select PLL Charge Pump Polarity MSB Address Bit LSB Address Bit 0: TPC pin high impedance 1: TPC pin pulled to ground 0: FSK modulation in Transmit mode 1: CW (no modulation in Transmit mode) 0: LO shift is 0 Hz for Transmit, 1.024MHz for Receive 1: LO shift is 1.024MHz for Transmit, 0Hz for Receive 0: PLL open loop during Receive 1: PLL closed loop during Receive 0: 6.144MHz nominal reference frequency 1: 12.288MHz nominal reference frequency 0: Freq. sig. < freq. ref.; Charge pump sources current 1: Freq. sig. < freq. ref.; Charge pump sinks current ADR1 = 0 ADR0 = 0 Set all bits to 0 (zero) USE Table 4. Register 0 -- PLL Configuration Register DATA BIT B15 (MSB) / DB13 B14 / DB12 B13 / DB11 B12 / DB10 B11 / DB9 B10 / DB8 B9 / DB7 B8 / DB6 B7 / DB5 B6 / DB4 B5 / DB3 B4 / DB2 B3 / DB1 B2 / DB0 B1 / ADB1 B0 (LSB) / ADB0 NAME Reserved Reserved CHQ11 CHQ10 CHQ9 CHQ8 CHQ7 CHQ6 CHQ5 CHQ4 CHQ3 CHQ2 CHQ1 CHQ0 ADR1 ADR0 MSB Address Bit LSB Address Bit ADR1 = 0 ADR0 = 1 Channel Frequency select bits Divide ratio = fc / 0.512 DESCRIPTION USE Set all bits to 0 (zero) Table 5. Register 1 – Channel Frequency Register DS2722-F-06 FINAL DATASHEET DECEMBER 2005 21 ML2722 DATA BIT B15 (MSB) / DB13 B14 / DB12 B13 / DB11 B12 / DB10 B11 / DB9 B10 / DB8 B9 / DB7 B8 / DB6 B7 / DB5 B6 / DB4 B5 / DB3 B4 / DB2 B3 / DB1 B2 / DB0 B1 / ADB1 B0 (LSB) / ADB0 NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DTM2 DTM1 DTM0 ATM2 ATM 1 ATM 0 ADR1 ADR0 MSB Address Bit LSB Address Bit ADR1 = 1 ADR0 = 0 Analog Test Control Bits See Table 14 Digital Test Control Bits See Table 15 Reserved Set all bits to 0 (zero) DESCRIPTION USE Table 6. Register 2 – Test Mode Register CONTROL REGISTER DESCRIPTIONS Power-On State All register values are set to 0 (zero) on Power Up. Power up is defined as occurring when VDD (pin 31) ≥ 2.0V (typical). The register default values are valid after power up. The PLL divide ratio and PLL configuration registers must be programmed before XCEN is asserted for the first time. Address and Data Bits (ADR) Each of the three registers are identically configured. Each is divided into a fourteen (14) bit data field and a two (2) bit address field. The 16 bits are input serially (see Figure 5) with the 14 data bits, most significant bit (DB13) first followed by the two address bits, most significant bit (ADR1) first. The last 16 bits clocked into the ML2722 will be loaded into the specified register. Loading less than 16 bits into any register will cause unpredictable device functionality. RES Bit Locations (Reserved) Bits identified as reserved must always have a logic 0 (zero) value for correct device operation. Power-on reset clears all reserved bits to zero. Each reserved bit must be programmed to logic zero whenever any of the three registers are reprogrammed. DS2722-F-06 FINAL DATASHEET DECEMBER 2005 22 ML2722 REGISTER #0, PLL CONFIGURATION PLL Charge Pump Polarity (QPP): DB0 This bit sets the charge pump polarity to sink or source current. For a majority of applications, this bit is cleared (QPP = 0). For applications where an external amplifier is in the loop filter, this bit is set to 1 to change the charge pump polarity (see Table 7). QPP 0 1 PLL CHARGE PUMP POLARITY Frequency signal < frequency reference. Charge pump sources current. Frequency signal < frequency reference. Charge pump sinks current. Table 7. PLL Charge Pump Polarity Reference Divide Bit Zero (RD0): DB1 This bit sets the reference division of the PLL to either 6 or 12 (see Table 8). RD0 0 1 REFERENCE DIVISION 6 12 NOMINAL REFERENCE FREQUENCY 6.144MHz 12.288MHz Table 8. Reference Frequency Select Receive Closed Loop Bit (RXCL): DB2 This bit is used in Receive mode to put the PLL into either open loop or closed loop (see Table 9). RXCL 0 1 RECEIVE PLL MODE PLL open loop PLL closed loop Table 9. PLL Mode in Normal Receive Operation PLL Frequency Shift Bit (LOL): DB3 LO shift for transmit and receive. For normal operations, it is recommended that LOL = 0 (see Table 10). LOL 0 1 LO SHIFT FOR TRANSMIT 0 +1.024MHz Table 10. PLL Frequency Shift LO SHIFT FOR RECEIVE +1.024MHz 0 DS2722-F-06 FINAL DATASHEET DECEMBER 2005 23 ML2722 Transmit Closed Loop Bit (TXCL): DB4 Used to produce a continuous CW transmitter output for product test with RXON low (see Table 11). TXCL 0 1 TRANSMIT PLL MODE PLL Open Loop, FSK Output PLL Closed Loop, CW Output Table 11. PLL Mode in Transmit Operation Transmit Power Control Bit (TPC): DB5 Controls the state of the TPC/TPQ open-drain output (pin 7). Although this bit may be set at any time, the TPC/TPQ pin only changes state at the falling edge of RXON (see Table 12). TPC 0 1 TPC PIN STATE High Impedance Pulled to Ground Table 12. TPC Pin State REGISTER #1, CHANNEL FREQUENCY REGISTER Channel Frequency Selection Bits (CHQ): These bits set the channel frequency for the transceiver (see Table 13). With a 6.144MHz or 12.288MHz input to the REF pin (pin 9), the channel frequency value is calculated by multiplying the CHQ value by 0.512. A 1.024MHz offset is automatically added in the RECEIVE mode to accommodate the IF frequency. The recommended operating range value of the CHQ is from 1,024 (400 hex) to 4093 (FFD hex). These bits should be programmed to a valid channel frequency before XCEN is asserted. The divide ratio is calculated as fC /0.512, where fC is the channel frequency in MHz. B15 0 B14 0 B13 TO B2 PLL divide ratio B1 0 B0 1 Table 13. Main Divider DS2722-F-06 FINAL DATASHEET DECEMBER 2005 24 ML2722 REGISTER #2, FILTER TUNING SELECT TEST MODE Analog Test Control Bits (ATM): The test mode selected is described in Table 14. The performance of the ML2722 is not specified in these test modes. Although primarily intended for IC test and debug, they also can help in debugging the radio system. The default (power-up) state of these bits is ATM = . When a non-zero value is written to the field, RSSI/TPI (pin 28) and TPC/TPQ (pin 7) become analog test access ports, giving access to the outputs of key signal processing stages in the transceiver. During normal operation, the ATM field should be set to zero. ATM2 0 0 0 0 1 1 1 1 ATM1 0 0 1 1 0 0 1 1 ATM0 0 1 0 1 0 1 0 1 RSSI/TPI RSSI I No Connect I IF Buffer Output I IF Buffer Output I IF Buffer Output I Data Slicer Input I IF Limiter Outputs 1.67V Ref. TPC/TPQ TPC (PA Control) Q No Connect Q IF Buffer Output Q IF Buffer Output Q IF Buffer Output Q Data Slicer Input Q IF Limiter Outputs VCO Mod. Voltage Table 14. Analog Test Control Bits Digital Test Control Bits (DTM): The DTM bit functions are described in Table 15. The performance of the ML2722 is not specified in these test modes. Although primarily intended for IC test and debug, they also can help in debugging the radio system. The default (power-up) state of these bits is DTM = . When a non-zero value is written to these fields, DOUT (pin 32) becomes a digital test access port for key digital signals in the transceiver. During normal operation, the DTM field should be set to zero. DTM2 0 0 0 0 DTM1 0 0 1 1 DTM0 0 1 0 1 DOUT Demodulated data Receiver AGC state PLL Main Divider Output PLL Reference Divider Output Table 15. Digital Test Control Bits TRANSMIT AND RECEIVE DATA INTERFACES The DIN and DOUT CMOS logic levels are serial data that correspond to FSK modulated data on the radio channel. The ML2722 operates as an FSK transceiver in the 902 to 928MHz ISM band. The chip rate, bit rate and spreading code are controlled by the baseband processor, and the FM deviation and transmit filtering are controlled by the transceiver. DIN provides data to the Transmit data filter, which band limits the transmitted chips or bits before they are FM modulated. There is no re-timing of the chips or bits, so the transmitted FSK chips or bits take their timing from DIN (pin 30). In the Receive chain, FM demodulation, data filtering, and data slicing take place in the ML2722 receiver, with chip, bit and word rate timing recovery performed in the baseband processor. RSSI AND REF There are two other interface pins between the ML2722 transceiver and the baseband IC: the RSSI/TPI (pin 28) and REF (pin 9). DS2722-F-06 FINAL DATASHEET DECEMBER 2005 25 ML2722 REF is the master reference frequency for the transceiver. It supplies the frequency reference for the RF channel frequency and the filter tuning. The REF pin is a CMOS input with internal biasing resistors. It can be AC coupled through a 470pF coupling capacitor to a sine wave source of at least 2.0V peak-to-peak. The PLL comparison and the IF filter center frequency are both equal to the REF input frequency divided by either 6 or 12, depending on the setting of the RDIV bit in the PLL configuration control word. The IF filter and data filter bandwidths track the IF filter center frequency. The Received Signal Strength Indicator (RSSI) pin supplies a voltage indicating the amplitude of the received RF signal. It is normally connected to the input of a low-speed ADC on an external baseband IC, and is used during channel scanning to detect clear channels on which the radio may transmit. The RSSI voltage is proportional to the logarithm of the received power level. A voltage of 0V to 2.7V typically corresponds to an RF input power of –95 to –20dBm with a nominal slope of 35mV/dB. CONTROL OUTPUTS TO THE PA – PAON AND TPC The ML2722 has two output pins to control and sequence the power amplifier – PAON and TPC (see Figure 6). RXON Internal PLLEN PAON Output from TRFO t1 t3 Figure 6. Power Amplifier Interface t2 SYMBOL t1 t2 PARAMETER RXON falling edge to PAON rising edge RXON rising edge to PLL recalibration RXON rising edge to receive mode RXON rising edge to PAON falling edge TIME/μS 62.5 6.5 70 < 0.1 t4 t3 t4 The PAON (PA control) is a CMOS output to control an off-chip RF PA (power amplifier). It outputs a logic high when the PA should be enabled, and a logic low at all other times. This output is inhibited if the PLL fails to lock, or the power supply to the ML2722 falls below 2.6V. The PLL lock detect or low voltage signals are latched, so that the transmitter is inhibited for the entire transmit time slot. These latches are reset at the end of the transmit time slot, so that the ML2722 will transmit in the next time slot following a transient fault condition. The TPC/TPQ (pin 7) is an open drain output intended for transmit power control. It is controlled by the TPC bit in serial bus register 0. This bit can be changed at any time, but the TPC pin will not change state until the beginning of the next transmit time slot, triggered by a falling edge on RXON. This pin interfaces to an external PA power control input via a resistor network to set the output power level. In analog test modes the RSSI/TPI (pin 28) and TPC/TPQ (pin 7) become analog test access ports that allow the user to observe internal signals in the ML2722. RF INTERFACES The RRFI receive input (pin 21) and the TRFO transmit output (pin 23) are the only RF I/O pins. The RRFI pin requires a simple impedance matching network for best input noise figure, and the TRFO pin is matched to 50Ω by an AC coupling capacitor. The associated RF input and output ground pins must have direct connections to an RF ground plane, and the RF block supply pins must be well decoupled to the RF ground pins. f GHz 0.9 MAG 0.757 S11 ANGLE -83.0 f GHz 0.9 MAG 0.208 S11 ANGLE 139.5 RRFI S-PARAMETERS AT 3.3V, OPERATING TEMPERATURE 25OC Table 16. Typical Receive RF Input TRFO S-PARAMETERS AT 3.3V, OPERATING TEMPERATURE 25OC Table 17. Typical Transmit RF Output DS2722-F-06 FINAL DATASHEET DECEMBER 2005 26 ML2722 PHYSICAL DIMENSIONS (INCHES/MILLIMETERS) Package: 32-Pin (7 x 7 x 1mm) 0.354 BSC (9.00 BSC) 0.276 BSC (7.00 BSC) 0º - 8º 25 0.003 - 0.008 (0.09 - 0.20) 1 PIN 1 ID 0.276 BSC (7.00 BSC) 0.354 BSC (9.00 BSC) 17 0.018 - 0.030 (0.45 - 0.75) 9 0.032 BSC (0.8 BSC) 0.012 - 0.018 (0.29 - 0.45) 0.048 MAX (1.20 MAX) 0.037 - 0.041 (0.95 - 1.05) SEATING PLANE Leads cannot exceed 0.004 maximum coplanarity (0.102) Note: This package meets “Green” Pb-Free requirements and is compliant with the European Union directives WEEE (Waste Electrical and Electronic Equipment) and RoHS (Restriction of the use of certain Hazardous Substances in electrical and electronic equipment). The package pins are finished with 100% matte tin. DS2722-F-06 FINAL DATASHEET DECEMBER 2005 27 ML2722 WARRANTY Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document. The circuits contained in this document are offered as possible applications only. Particular uses or applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Micro Linear products are not designed for use in medical, life saving, or life sustaining applications. If this document is “Advance”, its contents describe a Micro Linear product that is currently under development. All detailed specifications including pinouts and electrical specifications may be changed without notice. If this document is “Preliminary”, its contents are based on early silicon measurements. Typical data is representative of the product but is subject to change without notice. Pinout and mechanical dimensions are final. Preliminary documents supersede all Advance documents and all previous Preliminary versions. If this document is “Final”, its contents are based on a characterized product, and it is believed to be accurate at the time of publication. Final Data Sheets supersede all previously published versions. © 2005 Micro Linear Corporation. All rights reserved. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,704,176; 2,821,714. Other patents are pending. 4,964,026; 5,565,761; 5,742,151; 5,811,999; 2,619,299; Micro Linear Corporation 2050 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com DS2722-F-06 FINAL DATASHEET DECEMBER 2005 28