ML4875CS-T

July 2000 ML4875* Low Voltage Boost Regulator with Shutdown GENERAL DESCRIPTION The ML4875 is a boost regulator designed for DC to DC conversion in 1 to 3 cell battery powered systems. The combination of BiCMOS process technology, internal synchronous rectification, variable frequency operation, and low supply current make the ML4875 ideal for 1 cell applications. The ML4875 is capable of start-up with input voltages as low as 1V and is available in 5V, 3.3V, and 3V output versions with an output voltage accuracy of ±3%. Unlike regulators using external Schottky diodes, the ML4875 isolates the load from the battery when the SHDN pin is high. This is accomplished by an integrated synchronous rectifier which eliminates the need for an external Schottky diode and provides a lower forward voltage drop, resulting in higher conversion efficiency. In addition, low quiescent battery current and variable frequency operation result in high efficiency even at light loads. The ML4875 requires only one inductor and two capacitors to build a very small regulator circuit capable of achieving conversion efficiencies in excess of 90%. The circuit contains a RESET output which goes low when the DETECT input drops below 200mV. FEATURES s s s s s s s Guaranteed start-up and operation at 1V input Pulse Frequency Modulation and Internal Synchronous Rectification for high efficiency Isolates the load from the input during shutdown Minimum external components Low ON resistance internal switching FETs Micropower operation 5V, 3.3V, and 3V output versions *Some Packages Are End Of Life Or Obsolete BLOCK DIAGRAM L1 VOUT PWR GND 8 VL 6 5 VOUT VIN 1 FEEDBACK *CIN VBAT BOOST CONTROL COUT GND 3 REGULATION & SHUTDOWN CONTROL REF + – SHDN 2 DETECT 4 *RA RESET 7 FROM POWER MANAGEMENT *RB 5V *Optional 1 ML4875 PIN CONNECTION ML4875-5/-3/-T 8-Pin SOIC (S08) VIN SHDN GND DETECT 1 2 3 4 8 7 6 5 PWR GND RESET VL VOUT TOP VIEW PIN DESCRIPTION PIN NO. PIN NO. NAME FUNCTION NAME FUNCTION 1 2 VIN SHDN Battery input voltage Pulling this pin high shuts down the regulator, isolating the load from the input Analog signal ground When this pin below VREF, causes the RESET pin to go low 5 6 7 VOUT VL RESET Boost regulator output Boost inductor connection Output goes low when regulation cannot be achieved or when DETECT goes below 200mV 3 4 GND DETECT 8 PWR GND Return for the NMOS output transistor 2 ML4875 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VOUT ................................................................................................ 7V Voltage on any other pin ...... GND – 0.3V to VOUT + 0.3V Peak Switch Current, I(PEAK) ................................................. 1.5A Average Switch Current, I(AVG) ....................................... 300mA Junction Temperature ............................................. 150°C Storage Temperature Range ...................... –65°C to 150°C Lead Temperature (Soldering 10 sec.) ..................... 260°C Thermal Resistance (qJA) Plastic SOIC ................. 160°C/W OPERATING CONDITIONS Temperature Range ML4875CS-X .............................................. 0°C to 70°C ML4875ES-X ........................................... –20°C to 70°C VIN Operating Range ML4875CS-X ................................. 1.0V to VOUT –0.2V ML4875ES-X .................................. 1.1V to VOUT –0.2V ELECTRICAL CHARACTERISTICS Unless otherwise specified, VIN = Operating Voltage Range, TA = Operating Temperature Range (Note 1). PARAMETER SUPPLY VIN Current VIN = VOUT – 0.2V VIN = 4.8V, SHDN = VIN VOUT Quiescent Current VL Quiescent Current PFM REGULATOR Pulse Width (TON) Output Voltage (VOUT) ML4875-5 ML4875-3 ML4875-T Load Regulation ML4875-5 ML4875-3 ML4875-T Under-Voltage Lockout Threshold SHUTDOWN Input Bias Current Shutdown Threshold Shutdown Hysteresis RESET COMPARATOR DETECT Threshold DETECT Bias Current RESET ON Voltage RESET OFF Current Note 1: CONDITIONS MIN TYP. MAX UNITS 50 20 8 65 30 12 1 µA µA µA µA 8.9 TON = 0 at VOUT(MAX), 8.9µs - TON - 11.1µs VOUT(MIN) See Figure 1 VIN = 1.2V, IOUT - 20mA VIN = 2.4V, IOUT - 100mA VIN = 1.2V, IOUT - 30mA VIN = 2.4V, IOUT - 140mA VIN = 1.2V, IOUT - 35mA VIN = 2.4V, IOUT - 160mA 4.85 3.2 2.91 4.85 4.85 3.2 3.2 2.91 2.91 10 5.0 3.3 3.0 5.0 5.0 3.3 3.3 3.0 3.0 0.85 11.1 5.15 3.4 3.09 5.15 5.15 3.4 3.4 3.09 3.09 1 µs V V V V V V V V V V –100 VSHDN = high to low 180 200 50 100 220 70 nA mV mV 194 –100 IRESET = 50µA VRESET = 5V 200 206 100 mV nA mV µA 100 200 1 Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions. 3 ML4875 VIN 100µF VIN SHDN GND DETECT PWR GND RESET VL VOUT 100µF IOUT VOUT 27µH (Sumida CD75) Figure 1. Application Test Circuit Q3 L1 VIN 6 VL SHUTDOWN START-UP Q2 + A2 VOUT 5 C1 + VOUT – – R Q S Q1 10µs ONE SHOT R1 R2 – A1 + 200mV Figure 2. PFM Regulator Block Diagram 4 ML4875 FUNCTIONAL DESCRIPTION The ML4875 combines Pulse Frequency Modulation (PFM) and synchronous rectification to create a boost converter that is both highly efficient and simple to use. A PFM regulator charges a single inductor for a fixed period of time and then completely discharges before another cycle begins, simplifying the design by eliminating the need for conventional current limiting circuitry. Synchronous rectification is accomplished by replacing an external Schottky diode with an on-chip PMOS device, reducing switching losses and external component count. REGULATOR OPERATION A block diagram of the boost converter is shown in Figure 2. The circuit remains idle when VOUT is at or above the desired output voltage, drawing 50µA from VIN, and 8µA from VOUT through the feedback resistors R1 and R2. When VOUT drops below the desired output level, the output of amplifier A1 goes high, signaling the regulator to deliver charge to the output. Since the output of amplifier A2 is normally high, the flip-flop captures the A1 set signal and creates a pulse at the gate of the NMOS transistor Q1. The NMOS transistor will charge the inductor L1 for 10µs, resulting in a peak current given by: SHUTDOWN The ML4875 output can be shut down by pulling the SHDN pin high. When SHDN is high, the regulator stops switching, the control circuitry is powered down, and the body diode of the PMOS synchronous rectifier is disconnected from the output, allowing the output voltage to drop below the input voltage. This feature is unique to the ML4875, as most boost regulators use external Schottky diode rectifier which cannot be disconnected during shutdown. Leaving the Schottky diode connected causes excess power dissipation in the load during shutdown because the Schottky conducts whenever the output voltage drops 300mV below the input voltage. RESET COMPARATOR An additional comparator is provided to detect low VIN, or any other error condition that is important to the user. The inverting input of the comparator is internally connected to VREF, while the non-inverting input is provided externally at the DETECT pin. The output of the comparator is the RESET pin, which swings from VOUT to GND when an error is detected. DESIGN CONSIDERATIONS INDUCTOR Selecting the proper inductor for a specific application usually involves a trade-off between efficiency and maximum output current. Choosing too high a value will keep the regulator from delivering the required output current under worst case conditions. Choosing too low a value causes efficiency to suffer. It is necessary to know the maximum required output current and the input voltage range to select the proper inductor value. The maximum inductor value can be estimated using the following formula: V × TON(MIN) × η LMAX = IN(MIN) 2 × VOUT × IOUT(MAX) 2 IL(PEAK) T × VIN 10µs × VIN = ON ≈ L1 L1 (1) For reliable operation, L1 should be chosen so that IL(PEAK) does not exceed 1.5A. When the one-shot times out, the NMOS transistor releases the VL pin, allowing the inductor to fly-back and momentarily charge the output through the body diode of PMOS transistor Q2 in series with shutdown transistor Q3. But, as the voltage across the PMOS transistor changes polarity, its gate will be driven low by the current sense amplifier A2, causing Q2 to short out its body diode. The inductor then discharges into the load through Q2. The output of A2 also serves to reset the flip-flop and one-shot in preparation for the next charging cycle. A2 releases the gate of Q2 when its current falls to zero. If VOUT is still low, the flip-flop will immediately initiate another pulse. The output capacitor (C1) filters the inductor current, limiting output voltage ripple. Inductor current and oneshot waveforms are shown in Figure 3. (2) where h is the efficiency, typically between 0.8 and 0.9. Note that this is the value of inductance that just barely delivers the required output current under worst case conditions. A lower value may be required to cover inductor tolerance, the effect of lower peak inductor currents caused by resistive losses, and minimum dead time between pulses. Another method of determining the appropriate inductor value is to make an estimate based on the typical performance curves given in Figures 4 and 5. Figure 4 shows maximum output current as a function of input voltage for several inductor values. These are typical performance curves and leave no margin for inductance and ON-time variations. To accommodate worst case conditions, it is necessary to derate these curves by at least 10% in addition to inductor tolerance. For example, a two cell to 5V application requires 80mA of output current while using an inductor with 15% tolerance. The output current should be derated by 25% to 100mA to cover the combined inductor and ON-time INDUCTOR CURRENT Q(ONE SHOT) Q1 ON Q1 & Q2 OFF Q2 ON Q1 ON Q2 ON Figure 3. PFM Inductor Current Waveforms and Timing. 5 ML4875 ML4875-5.0 400 L = 15µH L = 27µH 400 ML4875-3.3 L = 15µH 300 IOUT (mA) IOUT (mA) 300 L = 27µH L = 56µH 200 200 L = 56µH 100 100 0 0 0 1.0 2.0 3.0 VIN (V) 4.0 5.0 0 1.0 2.0 3.0 VIN (V) 4.0 5.0 ML4875-3.0 400 L = 15µH 300 IOUT (mA) L = 27µH 200 L = 56µH 100 0 0 1.0 2.0 3.0 4.0 VIN (V) Figure 4. Output Current vs Input Voltage. tolerances. Assuming that 2V is the end of life voltage of a two cell input, Figure 4 shows that with a 2V input, the ML4875-5 delivers 99mA with a 27µH inductor. Figure 5 shows efficiency under the conditions used to create Figure 4. It can be seen that efficiency is mostly independent of input voltage and is closely related to inductor value. This illustrates the need to keep the inductor value as high as possible to attain peak system efficiency. As the inductor value goes down to 15µH, the efficiency drops to between 70% and 75%. With 56µH, the efficiency approaches 90% and there is little room for improvement. At values greater than 100µH, the operation of the synchronous rectifier becomes unreliable because the inductor current is so small that it is difficult for the control circuitry to detect. The data used to generate Figures 4 and 5 is provided in Table 1. After the appropriate inductor value is chosen, it is necessary to find the minimum inductor current rating required. Peak inductor current is determined from the following formula: IL(PEAK) = TON(MAX) × VIN(MAX) LMIN (3) In the two cell application previously described, a maximum input voltage of 3V would give a peak current of 1.2A. When comparing various inductors, it is important to keep in mind that suppliers use different criteria to determine their ratings. Many use a conservative current level, where inductance has dropped to 90% of its normal level. In any case, it is a good idea to try inductors of various current ratings with the ML4875 to determine which inductor is the best choice. Check efficiency and maximum output current, and if a current probe is available, look at the inductor current to see if it looks like the waveform shown in Figure 3. For additional information, see Applications Note 29. Suitable inductors can be purchased from the following suppliers: Coilcraft Coiltronics Dale Sumida (708) 639-6400 (407) 241-7876 (605) 665-9301 (708) 956-0666 6 ML4875 ML4875-5.0 100 L = 56µH 90 EFFICIENCY (%) 90 L = 56µH L = 27µH 80 L = 15µH 70 L = 27µH 80 L = 15µH 70 100 ML4875-3.3 60 EFFICIENCY (%) 60 50 0 1.0 2.0 3.0 VIN (V) 4.0 5.0 50 0 1.0 2.0 VIN (V) 3.0 ML4875-3.0 100 90 EFFICIENCY (%) L = 56µH L = 27µH 80 70 L = 15µH 60 50 0 1.0 2.0 VIN (V) 3.0 Figure 5. Typical Efficiency as a Function of VIN. OUTPUT CAPACITOR The choice of output capacitor is also important, as it controls the output ripple and optimizes the efficiency of the circuit. Output ripple is influenced by three capacitor parameters: capacitance, ESR, and ESL. The contribution due to capacitance can be determined by looking at the change in capacitor voltage required to store the energy delivered by the inductor in a single charge-discharge cycle, as determined by the following formula: ∆VOUT = TON × VIN 2 × L × C × (VOUT − VIN) 2 2 output current ramps quickly to match the peak inductor current. This fast change in current through the output capacitor’s ESL causes a high frequency (5ns) spike that can be over 1V in magnitude. After the ESL spike settles, the output voltage still has a ripple component equal to the inductor discharge current times the ESR. This component will have a sawtooth shape and a peak value equal to the peak inductor current times the ESR. ESR also has a negative effect on efficiency by contributing I-squared R losses during the discharge cycle. An output capacitor with a capacitance of 100µF, an ESR of less than 0.1ý, and an ESL of less than 5nH is a good general purpose choice. Tantalum capacitors which meet these requirements can be obtained from the following suppliers: Matsuo Sprague (714) 969-2491 (603) 224-1961 (4) For a 2.4V input, and 5V output, a 27µH inductor, and a 47µF capacitor, the expected output ripple due to capacitor value is 87mV. Capacitor Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL), also contribute to the output ripple due to the inductor discharge current waveform. Just after the NMOS transistor turns off, the If ESL spikes are causing output noise problems, an EMI filter can be added in series with the output. 7 ML4875 INPUT CAPACITOR Unless the input source is a very low impedance battery, it will be necessary to decouple the input with a capacitor with a value of between 47µF and 100µF. This provides the benefits of preventing input ripple from affecting the ML4875 control circuitry, and it also improves efficiency by reducing I-squared R losses during the charge and discharge cycles of the inductor. Again, a low ESR capacitor (such as tantalum) is recommended. DRIVING THE SHDN INPUT Unlike other boost regulators which use external Schottky diodes, the ML4875 has the ability to isolate the load from the battery input when the SHDN pin is high. Since there may be no other voltage available when the regulator is in shutdown, the SHDN input threshold is set well below the minimum VIN voltage. SHDN can be driven directly from an open collector device with a high value pull-up resistor to VIN. If SHDN is driven from a TTL or CMOS output device, a resistor divider should be used to prevent the SHDN input high level from exceeding VIN, and to ensure the SHDN input low level is below the 200mV threshold. SETTING THE RESET THRESHOLD To use the RESET comparator as an input voltage monitor, it is necessary to use an external resistor divider tied to the DETECT pin as shown in the block diagram. The resistor values RA and RB can be calculated using the following equation: LAYOUT Good PC board layout practices will ensure the proper operation of the ML4875. Important layout considerations include: • Use adequate ground and power traces or planes • Keep components as close as possible to the ML4875 • Use short trace lengths from the inductor to the VL pin and from the output capacitor to the VOUT pin • Use a single point ground for the ML4875 ground pins, and the input and output capacitors VIN(MIN) = 0.2 × (R A + RB ) RB (5) The value of RB should be 100ký or less to minimize bias current errors. RA is then found by rearranging the equation:  V R A = RB ×  IN(MIN) − 1    0.2 (6) 8 ML4875 TABLE 1. MAXIMUM OUTPUT CURRENT AND EFFICIENCY. ML4875-5.0 VIN (V) L = 15µH 1.0 1.5 2.0 2.5 3.0 3.5 L = 27µH 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 L = 56µH 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 IIN (mA) 237.5 373.3 494.6 616.0 710.5 793.9 138.2 220.7 296.2 374.1 441.6 496.4 538.2 542.6 72.5 113.1 158.7 201.6 237.5 270.4 297.4 310.4 IOUT (mA) 35.7 86.2 151.8 233.5 319.7 410.5 22.0 54.8 98.8 156.1 220.7 289.4 358.5 408.0 12.2 29.8 56.3 89.7 127.0 169.0 212.9 251.0 EFFICIENCY % 75.2 77.0 76.7 75.8 75.0 73.9 79.6 82.8 83.4 83.5 83.3 83.3 83.3 83.5 84.1 87.8 88.7 89.0 89.1 89.3 89.5 89.8 ML4875-3.0 VIN (V) L = 15µH 1.0 1.5 2.0 2.5 L = 27µH 1.0 1.5 2.0 2.5 L = 56µH 1.0 1.5 2.0 2.5 IIN (mA) 242.8 362.6 461.6 523.5 144.9 218.7 286.8 325.6 74.3 119.1 154.9 183.0 IOUT (mA) 59.2 131.3 219.2 308.5 38.9 88.2 153.4 217.5 21.5 52.0 90.2 133.2 EFFICIENCY % 73.1 72.4 71.2 70.7 80.5 80.7 80.2 80.2 86.8 87.3 87.3 87.3 ML4875-3.3 VIN (V) L = 15µH 1.0 1.5 2.0 2.5 3.0 L = 27µH 1.0 1.5 2.0 2.5 3.0 L = 56µH 1.0 1.5 2.0 2.5 3.0 IIN (mA) 243.1 346.6 473.6 551.9 563.6 144.5 218.4 292.3 345.7 357.2 73.9 118.5 156.8 189.0 206.6 IOUT (mA) 54.6 122.1 207.8 299.9 368.0 35.4 80.9 143.6 211.8 263.7 19.5 47.2 83.4 125.7 165.5 EFFICIENCY % 74.1 77.5 72.4 71.7 71.8 80.8 81.5 81.1 80.9 81.2 87.1 87.6 87.8 87.8 88.1 9 ML4875 PHYSICAL DIMENSIONS inches (millimeters) Package: S08 8-Pin SOIC Package: S08 8-Pin SOIC 0.189 - 0.199 (4.80 - 5.06) 8 PIN 1 ID 0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20) 1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0º - 8º 0.055 - 0.061 (1.40 - 1.55) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.004 - 0.010 (0.10 - 0.26) 0.015 - 0.035 (0.38 - 0.89) 0.006 - 0.010 (0.15 - 0.26) ORDERING INFORMATION PART NUMBER ML4875CS-T (Obsolete) ML4875CS-3 ML4875CS-5 ML4875ES-T ML4875ES-3 (End Of Life) ML4875ES-5 (End Of Life) OUTPUT VOLTAGETEMPERATURE RANGE 3.0V 3.3V 5.0V 3.0V 3.3V 5.0V 0°C to 70°C 0°C to 70°C 0°C to 70°C –20°C to 70°C –20°C to 70°C –20°C to 70°C PACKAGE 8-Pin SOIC (S08) 8-Pin SOIC (S08) 8-Pin SOIC (S08) 8-Pin SOIC (S08) 8-Pin SOIC (S08) 8-Pin SOIC (S08) DS4875-01 © Micro Linear 1996 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 7/16/96 Printed in U.S.A. 10