4Gb: x4, x8, x16 DDR3L SDRAM
Description
DDR3L SDRAM
MT41K1G4 – 128 Meg x 4 x 8 banks
MT41K512M8 – 64 Meg x 8 x 8 banks
MT41K256M16 – 32 Meg x 16 x 8 banks
• TC of 0°C to +95°C
– 64ms, 8192-cycle refresh at 0°C to +85°C
– 32ms at +85°C to +95°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Description
DDR3L SDRAM (1.35V) is a low voltage version of the
DDR3 (1.5V) SDRAM. Refer to the DDR3 (1.5V)
SDRAM data sheet specifications when running in
1.5V compatible mode.
Features
• VDD = V DDQ = 1.35V (1.283–1.45V)
• Backward compatible to V DD = V DDQ = 1.5V ±0.075V
– Supports DDR3L devices to be backward compatible in 1.5V applications
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
Options
Marking
• Configuration
– 1 Gig x 4
– 512 Meg x 8
– 256 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (10.5mm x 12mm) Rev. D
– 78-ball (9mm x 10.5mm) Rev. E, J
• FBGA package (Pb-free) – x16
– 96-ball (10mm x 14mm) Rev. D
– 96-ball (9mm x 14mm) Rev. E
• Timing – cycle time
– 1.071ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.875ns @ CL = 7 (DDR3-1066)
• Operating temperature
– Commercial (0°C ≤ T C ≤ +95°C)
– Industrial (–40°C ≤ T C ≤ +95°C)
• Revision
1G4
512M8
256M16
RA
RH
RE
HA
-107
-125
-15E
-187E
None
IT
:D/:E/:J
Table 1: Key Timing Parameters
Speed Grade
Data Rate (MT/s)
Target tRCD-tRP-CL
-1071, 2, 3
1866
13-13-13
13.91
13.91
13.91
-1251, 2
1600
11-11-11
13.75
13.75
13.75
-15E1
1333
9-9-9
13.5
13.5
13.5
-187E
1066
7-7-7
13.1
13.1
13.1
Notes:
tRCD
(ns)
tRP
(ns)
CL (ns)
1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1600, CL = 11 (-125).
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Products and specifications discussed herein are subject to change by Micron without notice.
4Gb: x4, x8, x16 DDR3L SDRAM
Description
Table 2: Addressing
Parameter
Configuration
1 Gig x 4
512 Meg x 8
256 Meg x 16
128 Meg x 4 x 8 banks
64 Meg x 8 x 8 banks
32 Meg x 16 x 8 banks
Refresh count
8K
8K
8K
Row address
64K (A[15:0])
64K (A[15:0])
32K (A[14:0])
Bank address
8 (BA[2:0])
8 (BA[2:0])
8 (BA[2:0])
2K (A[11, 9:0])
1K (A[9:0])
1K (A[9:0])
1KB
1KB
2KB
Column address
Page size
Figure 1: DDR3L Part Numbers
Example Part Number:
MT41K512M8RH-125:E
-
Configuration
Package
Speed
Revision
{
MT41K
:
:D/:E/:J/:Q Revision
Temperature
Configuration
1 Gig x 4
1G4
Commercial
512 Meg x 8
512M8
Industrial temperature
256 Meg x 16
256M16
None
IT
Speed Grade
Note:
Package
78-ball 10.5mm x 12mm FBGA
Rev.
D
Mark
RA
78-ball 9mm x 10.5mm FBGA
E, J, Q
RH
96-ball 10.0mm x 14mm FBGA
96-ball 9mm x 14mm FBGA
D
E, Q
RE
HA
-107
tCK
= 1.071ns, CL = 13
-125
tCK
= 1.25ns, CL = 11
-15E
tCK
= 1.5ns, CL = 9
-187E
tCK
= 1.875ns, CL = 7
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com for available offerings.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
Contents
State Diagram ................................................................................................................................................ 11
Functional Description ................................................................................................................................... 12
Industrial Temperature ............................................................................................................................... 12
General Notes ............................................................................................................................................ 12
Functional Block Diagrams ............................................................................................................................. 14
Ball Assignments and Descriptions ................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 22
Electrical Specifications .................................................................................................................................. 26
Absolute Ratings ......................................................................................................................................... 26
Input/Output Capacitance .......................................................................................................................... 27
Thermal Characteristics .................................................................................................................................. 28
Electrical Specifications – IDD Specifications and Conditions ............................................................................ 30
Electrical Characteristics – DDR3L (1.35V) Operating IDD Specifications ........................................................... 41
Electrical Specifications – DC and AC .............................................................................................................. 45
DC Operating Conditions ........................................................................................................................... 45
Input Operating Conditions ........................................................................................................................ 46
DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 50
DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 53
DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 55
ODT Characteristics ....................................................................................................................................... 56
1.35V ODT Resistors ................................................................................................................................... 57
ODT Sensitivity .......................................................................................................................................... 58
ODT Timing Definitions ............................................................................................................................. 58
Output Driver Impedance ............................................................................................................................... 62
34 Ohm Output Driver Impedance .............................................................................................................. 63
DDR3L 34 Ohm Driver ................................................................................................................................ 64
DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 65
DDR3L Alternative 40 Ohm Driver ............................................................................................................... 66
DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 66
Output Characteristics and Operating Conditions ............................................................................................ 68
Reference Output Load ............................................................................................................................... 71
Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 71
Slew Rate Definitions for Differential Output Signals .................................................................................... 73
Speed Bin Tables ............................................................................................................................................ 74
Electrical Characteristics and AC Operating Conditions ................................................................................... 78
Command and Address Setup, Hold, and Derating ........................................................................................... 98
Data Setup, Hold, and Derating ...................................................................................................................... 105
Commands – Truth Tables ............................................................................................................................. 113
Commands ................................................................................................................................................... 116
DESELECT ................................................................................................................................................ 116
NO OPERATION ........................................................................................................................................ 116
ZQ CALIBRATION LONG ........................................................................................................................... 116
ZQ CALIBRATION SHORT .......................................................................................................................... 116
ACTIVATE ................................................................................................................................................. 116
READ ........................................................................................................................................................ 116
WRITE ...................................................................................................................................................... 117
PRECHARGE ............................................................................................................................................. 118
REFRESH .................................................................................................................................................. 118
SELF REFRESH .......................................................................................................................................... 119
DLL Disable Mode ..................................................................................................................................... 120
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
Input Clock Frequency Change ...................................................................................................................... 124
Write Leveling ............................................................................................................................................... 126
Write Leveling Procedure ........................................................................................................................... 128
Write Leveling Mode Exit Procedure ........................................................................................................... 130
Initialization ................................................................................................................................................. 131
Voltage Initialization / Change ....................................................................................................................... 133
VDD Voltage Switching ............................................................................................................................... 134
Mode Registers .............................................................................................................................................. 135
Mode Register 0 (MR0) ................................................................................................................................... 136
Burst Length ............................................................................................................................................. 136
Burst Type ................................................................................................................................................. 137
DLL RESET ................................................................................................................................................ 138
Write Recovery .......................................................................................................................................... 138
Precharge Power-Down (Precharge PD) ...................................................................................................... 139
CAS Latency (CL) ....................................................................................................................................... 139
Mode Register 1 (MR1) ................................................................................................................................... 140
DLL Enable/DLL Disable ........................................................................................................................... 140
Output Drive Strength ............................................................................................................................... 141
OUTPUT ENABLE/DISABLE ...................................................................................................................... 141
TDQS Enable ............................................................................................................................................. 141
On-Die Termination .................................................................................................................................. 142
WRITE LEVELING ..................................................................................................................................... 142
POSTED CAS ADDITIVE Latency ................................................................................................................ 142
Mode Register 2 (MR2) ................................................................................................................................... 143
CAS Write Latency (CWL) ........................................................................................................................... 144
AUTO SELF REFRESH (ASR) ....................................................................................................................... 144
SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 145
SRT vs. ASR ............................................................................................................................................... 145
DYNAMIC ODT ......................................................................................................................................... 145
Mode Register 3 (MR3) ................................................................................................................................... 146
MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 146
MPR Functional Description ...................................................................................................................... 147
MPR Register Address Definitions and Bursting Order ................................................................................. 148
MPR Read Predefined Pattern .................................................................................................................... 154
MODE REGISTER SET (MRS) Command ........................................................................................................ 154
ZQ CALIBRATION Operation ......................................................................................................................... 155
ACTIVATE Operation ..................................................................................................................................... 156
READ Operation ............................................................................................................................................ 158
WRITE Operation .......................................................................................................................................... 169
DQ Input Timing ....................................................................................................................................... 177
PRECHARGE Operation ................................................................................................................................. 179
SELF REFRESH Operation .............................................................................................................................. 179
Extended Temperature Usage ........................................................................................................................ 181
Power-Down Mode ........................................................................................................................................ 182
RESET Operation ........................................................................................................................................... 190
On-Die Termination (ODT) ............................................................................................................................ 192
Functional Representation of ODT ............................................................................................................. 192
Nominal ODT ............................................................................................................................................ 192
Dynamic ODT ............................................................................................................................................... 194
Dynamic ODT Special Use Case ................................................................................................................. 194
Functional Description .............................................................................................................................. 194
Synchronous ODT Mode ................................................................................................................................ 200
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
ODT Latency and Posted ODT .................................................................................................................... 200
Timing Parameters .................................................................................................................................... 200
ODT Off During READs .............................................................................................................................. 203
Asynchronous ODT Mode .............................................................................................................................. 205
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 207
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 209
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 211
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
List of Figures
Figure 1: DDR3L Part Numbers ........................................................................................................................ 2
Figure 2: Simplified State Diagram ................................................................................................................. 11
Figure 3: 1 Gig x 4 Functional Block Diagram .................................................................................................. 14
Figure 4: 512 Meg x 8 Functional Block Diagram ............................................................................................. 15
Figure 5: 256 Meg x 16 Functional Block Diagram ........................................................................................... 15
Figure 6: 78-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 16
Figure 7: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 17
Figure 8: 78-Ball FBGA – x4, x8 (RA) ................................................................................................................ 22
Figure 9: 78-Ball FBGA – x4, x8 (RH) ............................................................................................................... 23
Figure 10: 96-Ball FBGA – x16 (RE) ................................................................................................................. 24
Figure 11: 96-Ball FBGA – x16 (HA) ................................................................................................................. 25
Figure 12: Thermal Measurement Point ......................................................................................................... 29
Figure 13: DDR3L 1.35V Input Signal .............................................................................................................. 49
Figure 14: Overshoot ..................................................................................................................................... 50
Figure 15: Undershoot ................................................................................................................................... 50
Figure 16: V IX for Differential Signals .............................................................................................................. 51
Figure 17: Single-Ended Requirements for Differential Signals ........................................................................ 51
Figure 18: Definition of Differential AC-Swing and tDVAC ............................................................................... 52
Figure 19: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 54
Figure 20: DDR3L 1.35V Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .............. 55
Figure 21: ODT Levels and I-V Characteristics ................................................................................................ 56
Figure 22: ODT Timing Reference Load .......................................................................................................... 59
Figure 23: tAON and tAOF Definitions ............................................................................................................ 60
Figure 24: tAONPD and tAOFPD Definitions ................................................................................................... 60
Figure 25: tADC Definition ............................................................................................................................. 61
Figure 26: Output Driver ................................................................................................................................ 62
Figure 27: DQ Output Signal .......................................................................................................................... 69
Figure 28: Differential Output Signal .............................................................................................................. 70
Figure 29: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 71
Figure 30: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 72
Figure 31: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 73
Figure 32: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) ............................................. 101
Figure 33: Nominal Slew Rate for tIH (Command and Address – Clock) ........................................................... 102
Figure 34: Tangent Line for tIS (Command and Address – Clock) .................................................................... 103
Figure 35: Tangent Line for tIH (Command and Address – Clock) .................................................................... 104
Figure 36: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ......................................................................... 109
Figure 37: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 110
Figure 38: Tangent Line for tDS (DQ – Strobe) ................................................................................................ 111
Figure 39: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 112
Figure 40: Refresh Mode ............................................................................................................................... 119
Figure 41: DLL Enable Mode to DLL Disable Mode ........................................................................................ 121
Figure 42: DLL Disable Mode to DLL Enable Mode ........................................................................................ 122
Figure 43: DLL Disable tDQSCK .................................................................................................................... 123
Figure 44: Change Frequency During Precharge Power-Down ........................................................................ 125
Figure 45: Write Leveling Concept ................................................................................................................. 126
Figure 46: Write Leveling Sequence ............................................................................................................... 129
Figure 47: Write Leveling Exit Procedure ....................................................................................................... 130
Figure 48: Initialization Sequence ................................................................................................................. 132
Figure 49: V DD Voltage Switching .................................................................................................................. 134
Figure 50: MRS to MRS Command Timing ( tMRD) ......................................................................................... 135
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
Figure 51: MRS to nonMRS Command Timing ( tMOD) .................................................................................. 136
Figure 52: Mode Register 0 (MR0) Definitions ................................................................................................ 137
Figure 53: READ Latency .............................................................................................................................. 139
Figure 54: Mode Register 1 (MR1) Definition ................................................................................................. 140
Figure 55: READ Latency (AL = 5, CL = 6) ....................................................................................................... 143
Figure 56: Mode Register 2 (MR2) Definition ................................................................................................. 144
Figure 57: CAS Write Latency ........................................................................................................................ 144
Figure 58: Mode Register 3 (MR3) Definition ................................................................................................. 146
Figure 59: Multipurpose Register (MPR) Block Diagram ................................................................................. 147
Figure 60: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 150
Figure 61: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 151
Figure 62: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 152
Figure 63: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 153
Figure 64: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 155
Figure 65: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 156
Figure 66: Example: tFAW ............................................................................................................................. 157
Figure 67: READ Latency .............................................................................................................................. 158
Figure 68: Consecutive READ Bursts (BL8) .................................................................................................... 160
Figure 69: Consecutive READ Bursts (BC4) .................................................................................................... 160
Figure 70: Nonconsecutive READ Bursts ....................................................................................................... 161
Figure 71: READ (BL8) to WRITE (BL8) .......................................................................................................... 161
Figure 72: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 162
Figure 73: READ to PRECHARGE (BL8) .......................................................................................................... 162
Figure 74: READ to PRECHARGE (BC4) ......................................................................................................... 163
Figure 75: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 163
Figure 76: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 163
Figure 77: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 165
Figure 78: Data Strobe Timing – READs ......................................................................................................... 166
Figure 79: Method for Calculating tLZ and tHZ ............................................................................................... 167
Figure 80: tRPRE Timing ............................................................................................................................... 167
Figure 81: tRPST Timing ............................................................................................................................... 168
Figure 82: tWPRE Timing .............................................................................................................................. 170
Figure 83: tWPST Timing .............................................................................................................................. 170
Figure 84: WRITE Burst ................................................................................................................................ 171
Figure 85: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 172
Figure 86: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 172
Figure 87: Nonconsecutive WRITE to WRITE ................................................................................................. 173
Figure 88: WRITE (BL8) to READ (BL8) .......................................................................................................... 173
Figure 89: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 174
Figure 90: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 175
Figure 91: WRITE (BL8) to PRECHARGE ........................................................................................................ 176
Figure 92: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 176
Figure 93: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 177
Figure 94: Data Input Timing ........................................................................................................................ 178
Figure 95: Self Refresh Entry/Exit Timing ...................................................................................................... 180
Figure 96: Active Power-Down Entry and Exit ................................................................................................ 184
Figure 97: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 184
Figure 98: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 185
Figure 99: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 185
Figure 100: Power-Down Entry After WRITE .................................................................................................. 186
Figure 101: Power-Down Entry After WRITE with Auto Precharge (WRAP) ...................................................... 186
Figure 102: REFRESH to Power-Down Entry .................................................................................................. 187
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
Figure 103:
Figure 104:
Figure 105:
Figure 106:
Figure 107:
Figure 108:
Figure 109:
Figure 110:
Figure 111:
Figure 112:
Figure 113:
Figure 114:
Figure 115:
Figure 116:
Figure 117:
Figure 118:
Figure 119:
Figure 120:
Figure 121:
ACTIVATE to Power-Down Entry ................................................................................................. 187
PRECHARGE to Power-Down Entry ............................................................................................. 188
MRS Command to Power-Down Entry ......................................................................................... 188
Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 189
RESET Sequence ......................................................................................................................... 191
On-Die Termination ................................................................................................................... 192
Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 197
Dynamic ODT: Without WRITE Command .................................................................................. 197
Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 198
Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 199
Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 199
Synchronous ODT ...................................................................................................................... 201
Synchronous ODT (BC4) ............................................................................................................. 202
ODT During READs .................................................................................................................... 204
Asynchronous ODT Timing with Fast ODT Transition .................................................................. 206
Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 208
Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 210
Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 212
Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 212
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Addressing ......................................................................................................................................... 2
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................. 18
Table 4: 96-Ball FBGA – x16 Ball Descriptions ................................................................................................. 20
Table 5: Absolute Maximum Ratings .............................................................................................................. 26
Table 6: DDR3L Input/Output Capacitance .................................................................................................... 27
Table 7: Thermal Characteristics .................................................................................................................... 28
Table 8: DDR3L Timing Parameters Used for I DD Measurements – Clock Units ................................................. 30
Table 9: DDR3L IDD0 Measurement Loop ........................................................................................................ 31
Table 10: DDR3L IDD1 Measurement Loop ...................................................................................................... 32
Table 11: DDR3L IDD Measurement Conditions for Power-Down Currents ....................................................... 33
Table 12: DDR3L IDD2N and IDD3N Measurement Loop .................................................................................... 34
Table 13: DDR3L IDD2NT Measurement Loop .................................................................................................. 34
Table 14: DDR3L IDD4R Measurement Loop .................................................................................................... 35
Table 15: DDR3L IDD4W Measurement Loop .................................................................................................... 36
Table 16: DDR3L IDD5B Measurement Loop .................................................................................................... 37
Table 17: DDR3L IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 ........................................................ 38
Table 18: DDR3L IDD7 Measurement Loop ...................................................................................................... 39
Table 19: IDD Maximum Limits - Die Rev D ..................................................................................................... 41
Table 20: IDD Maximum Limits Die Rev E, J ..................................................................................................... 43
Table 21: DDR3L 1.35V DC Electrical Characteristics and Operating Conditions .............................................. 45
Table 22: DDR3L 1.35V DC Electrical Characteristics and Input Conditions ..................................................... 46
Table 23: DDR3L 1.35V Input Switching Conditions - Command and Address .................................................. 47
Table 24: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .............................. 48
Table 25: DDR3L Control and Address Pins ..................................................................................................... 50
Table 26: DDR3L 1.35V Clock, Data, Strobe, and Mask Pins ............................................................................. 50
Table 27: DDR3L 1.35V - Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback ...
52
Table 28: Single-Ended Input Slew Rate Definition .......................................................................................... 53
Table 29: DDR3L 1.35V Differential Input Slew Rate Definition ........................................................................ 55
Table 30: On-Die Termination DC Electrical Characteristics ............................................................................ 56
Table 31: 1.35V RTT Effective Impedance ........................................................................................................ 57
Table 32: ODT Sensitivity Definition .............................................................................................................. 58
Table 33: ODT Temperature and Voltage Sensitivity ........................................................................................ 58
Table 34: ODT Timing Definitions .................................................................................................................. 59
Table 35: DDR3L(1.35V) Reference Settings for ODT Timing Measurements .................................................... 59
Table 36: DDR3L 34 Ohm Driver Impedance Characteristics ........................................................................... 63
Table 37: DDR3L 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations ........................................... 64
Table 38: DDR3L 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = DDR3L@1.35V ..................................... 64
Table 39: DDR3L 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = DDR3L@1.45V ..................................... 64
Table 40: DDR3L 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = DDR3L@1.283 ..................................... 65
Table 41: DDR3L 34 Ohm Output Driver Sensitivity Definition ........................................................................ 65
Table 42: DDR3L 34 Ohm Output Driver Voltage and Temperature Sensitivity .................................................. 65
Table 43: DDR3L 40 Ohm Driver Impedance Characteristics ........................................................................... 66
Table 44: DDR3L 40 Ohm Output Driver Sensitivity Definition ........................................................................ 66
Table 45: 40 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 67
Table 46: DDR3L Single-Ended Output Driver Characteristics ......................................................................... 68
Table 47: DDR3L Differential Output Driver Characteristics ............................................................................ 69
Table 48: DDR3L Differential Output Driver Characteristics V OX(AC) ................................................................. 70
Table 49: Single-Ended Output Slew Rate Definition ....................................................................................... 71
Table 50: Differential Output Slew Rate Definition .......................................................................................... 73
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4Gb: x4, x8, x16 DDR3L SDRAM
Description
Table 51:
Table 52:
Table 53:
Table 54:
Table 55:
Table 56:
Table 57:
Table 58:
Table 59:
Table 60:
Table 61:
Table 62:
Table 63:
Table 64:
Table 65:
Table 66:
Table 67:
Table 68:
Table 69:
Table 70:
Table 71:
Table 72:
Table 73:
Table 74:
Table 75:
Table 76:
Table 77:
Table 78:
Table 79:
Table 80:
Table 81:
Table 82:
Table 83:
Table 84:
Table 85:
Table 86:
Table 87:
Table 88:
Table 89:
Table 90:
DDR3L-1066 Speed Bins .................................................................................................................. 74
DDR3L-1333 Speed Bins .................................................................................................................. 75
DDR3L-1600 Speed Bins .................................................................................................................. 76
DDR3L-1866 Speed Bins .................................................................................................................. 77
Electrical Characteristics and AC Operating Conditions .................................................................... 78
Electrical Characteristics and AC Operating Conditions .................................................................... 80
Electrical Characteristics and AC Operating Conditions for Speed Extensions .................................... 90
DDR3L Command and Address Setup and Hold Values 1 V/ns Referenced – AC/DC-Based ................ 99
DDR3L-800/1066/1333/1600 Derating Values tIS/tIH – AC160/DC90-Based ...................................... 99
DDR3L-800/1066/1333/1600 Derating Values for tIS/tIH – AC135/DC90-Based ................................. 99
DDR3L-1866 Derating Values for tIS/tIH – AC125/DC90-Based ........................................................ 100
DDR3L Minimum Required Time tVAC Above V IH(AC) (Below V IL[AC]) for Valid ADD/CMD Transition . 100
DDR3L Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based ....................... 106
DDR3L Derating Values for tDS/tDH – AC160/DC90-Based .............................................................. 106
DDR3L Derating Values for tDS/tDH – AC135/DC100-Based ............................................................ 106
DDR3L Derating Values for tDS/tDH – AC130/DC100-Based at 2V/ns ............................................... 107
DDR3L Minimum Required Time tVAC Above V IH(AC) (Below V IL(AC)) for Valid DQ Transition ............. 108
Truth Table – Command ................................................................................................................. 113
Truth Table – CKE .......................................................................................................................... 115
READ Command Summary ............................................................................................................ 117
WRITE Command Summary .......................................................................................................... 117
READ Electrical Characteristics, DLL Disable Mode ......................................................................... 123
Write Leveling Matrix ..................................................................................................................... 127
Burst Order .................................................................................................................................... 138
MPR Functional Description of MR3 Bits ........................................................................................ 147
MPR Readouts and Burst Order Bit Mapping ................................................................................... 148
Self Refresh Temperature and Auto Self Refresh Description ............................................................ 181
Self Refresh Mode Summary ........................................................................................................... 181
Command to Power-Down Entry Parameters .................................................................................. 182
Power-Down Modes ....................................................................................................................... 183
Truth Table – ODT (Nominal) ......................................................................................................... 193
ODT Parameters ............................................................................................................................ 193
Write Leveling with Dynamic ODT Special Case .............................................................................. 194
Dynamic ODT Specific Parameters ................................................................................................. 195
Mode Registers for RTT,nom ............................................................................................................. 195
Mode Registers for RTT(WR) ............................................................................................................. 196
Timing Diagrams for Dynamic ODT ................................................................................................ 196
Synchronous ODT Parameters ........................................................................................................ 201
Asynchronous ODT Timing Parameters for All Speed Bins ............................................................... 206
ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period ................................... 208
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4Gb: x4, x8, x16 DDR3L SDRAM
State Diagram
State Diagram
Figure 2: Simplified State Diagram
CKE L
Power
applied
Power
on
MRS, MPR,
write
leveling
Initialization
Reset
procedure
Self
refresh
SRE
ZQCL
From any
state
RESET
ZQ
calibration
MRS
SRX
REF
ZQCL/ZQCS
Refreshing
Idle
PDE
ACT
PDX
Active
powerdown
Precharge
powerdown
Activating
PDX
CKE L
CKE L
PDE
Bank
active
WRITE
WRITE
READ
WRITE AP
Writing
READ
READ AP
READ
WRITE
WRITE AP
Reading
READ AP
WRITE AP
READ AP
PRE, PREA
Writing
PRE, PREA
PRE, PREA
Reading
Precharging
Automatic
sequence
Command
sequence
ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
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PREA = PRECHARGE ALL
READ = RD, RDS4, RDS8
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry
11
SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION
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4Gb: x4, x8, x16 DDR3L SDRAM
Functional Description
Functional Description
DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write
operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK
going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select
the bank and the starting column location for the burst access.
The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM
allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
Industrial Temperature
The industrial temperature (IT) device requires that the case temperature not exceed
–40°C or 95°C. JEDEC specifications require the refresh rate to double when T C exceeds
85°C; this also requires use of the high-temperature self refresh option. Additionally,
ODT resistance and the input/output impedance must be derated when T C is < 0°C or
>95°C.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL enable mode of operation (normal operation).
• Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be
interpreted as any and all DQ collectively, unless specifically stated otherwise.
• The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as
DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.
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4Gb: x4, x8, x16 DDR3L SDRAM
Functional Description
• Complete functionality may be described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements.
• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated is considered undefined, illegal, and not supported, and can result in unknown operation.
• Row addressing is denoted as A[n:0]. For example, 1Gb: n = 12 (x16); 1Gb: n = 13 (x4,
x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4,
x8).
• Dynamic ODT has a special use case: when DDR3 devices are architected for use in a
single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer
to the Dynamic ODT Special Use Case section.
• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be
used, use the lower byte for data transfers and terminate the upper byte as noted:
–
–
–
–
Connect UDQS to ground via 1kΩ* resistor.
Connect UDQS# to V DD via 1kΩ* resistor.
Connect UDM to V DD via 1kΩ* resistor.
Connect DQ[15:8] individually to either V SS, V DD, or V REF via 1kΩ resistors,* or float
DQ[15:8].
*If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT.
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4Gb: x4, x8, x16 DDR3L SDRAM
Functional Block Diagrams
Functional Block Diagrams
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
Figure 3: 1 Gig x 4 Functional Block Diagram
ODT
control
ODT
ZQ
RZQ
ZQCL, ZQCS
CKE
VSSQ
To pull-up/pull-down
networks
ZQ CAL
RESET#
Control
logic
A12
CK, CK#
VDDQ/2
BC4 (burst chop)
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
19
Columns 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
16
16
Bank 0
rowaddress
latch
and
decoder
65,536
DLL
(1 . . . 4)
Bank 0
memory
array
(65,536 x 256 x 32)
32
READ
FIFO
and
data
MUX
4
DQ[3:0]
READ
drivers
BC4
RTT,nom
8,192
BC4
OTF
A[15:0]
BA[2:0]
19
Address
register
3
sw1
sw2
DM
(1, 2)
Columnaddress
counter/
latch
DQS, DQS#
VDDQ/2
32
Data
interface
Column
decoder
4
Data
WRITE
drivers
and
input
logic
8
RTT,nom
sw1
RTT(WR)
sw2
DM
3
Columns 0, 1, and 2
CK, CK#
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RTT(WR)
Bank
control
logic
256
(x32)
11
DQ[3:0]
DQS, DQS#
VDDQ/2
32
I/O gating
DM mask logic
sw2
sw1
Sense amplifiers
3
RTT(WR)
CK, CK#
16
Rowaddress
MUX
RTT,nom
14
Column 2
(select upper or
lower nibble for BC4)
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4Gb: x4, x8, x16 DDR3L SDRAM
Functional Block Diagrams
Figure 4: 512 Meg x 8 Functional Block Diagram
ODT
control
ODT
ZQ
RZQ
Control
logic
CKE
VSSQ
To ODT/output drivers
ZQ CAL
RESET#
ZQCL, ZQCS
A12
VDDQ/2
CK, CK#
BC4 (burst chop)
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
CK, CK#
sw1
(1 . . . 8)
19
Bank 0
Memory
array
(65,536 x 128 x 64)
Bank 0
rowaddress
65,536
latch
and
decoder
16
16
Sense amplifiers
sw2
DLL
16
Rowaddress
MUX
64
DQ8
READ
FIFO
and
data
MUX
8
19
Address
register
DQ[7:0]
DQS, DQS#
VDDQ/2
64
BC4
OTF
RTT,nom
sw1
RTT(WR)
sw2
I/O gating
DM mask logic
3
A[15:0]
BA[2:0]
TDQS#
DQ[7:0]
Read
drivers
BC4
8,192
RTT(WR)
RTT,nom
Columns 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
(1, 2)
Bank
control
logic
3
VDDQ/2
(128
x64)
64
8
Data
interface
Data
Column
decoder
Columnaddress
counter/
latch
10
DQS/DQS#
Write
drivers
and
input
logic
RTT,nom
sw1
RTT(WR)
sw2
7
DM/TDQS
(shared pin)
3
Columns 0, 1, and 2
CK, CK#
Column 2
(select upper or
lower nibble for BC4)
Figure 5: 256 Meg x 16 Functional Block Diagram
ODT
control
ODT
ZQ
RZQ
ZQ CAL
RESET#
Control
logic
CKE
VSSQ
To ODT/output drivers
ZQCL, ZQCS
A12
VDDQ/2
CK, CK#
BC4 (burst chop)
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
18
Column 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
15
15
Bank 0
rowaddress
latch
and
decoder
32,768
DLL
(1 . . . 16)
128
READ
FIFO
and
data
MUX
16
DQ[15:0]
READ
drivers
LDQS, LDQS#, UDQS, UDQS#
BC4
128
18
Address
register
3
sw2
LDQS, LDQS#
Bank
control
logic
(1 . . . 4)
Columnaddress
counter/
latch
UDQS, UDQS#
VDDQ/2
128
Data
interface
Column
decoder
16
Data
WRITE
drivers
and
input
logic
RTT,nom
sw1
RTT(WR)
sw2
7
(1, 2)
LDM/UDM
3
Columns 0, 1, and 2
CK, CK#
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RTT(WR)
I/O gating
DM mask logic
(128
x128)
10
RTT,nom
sw1
BC4
OTF
3
DQ[15:0]
VDDQ/2
Sense amplifiers
A[14:0]
BA[2:0]
sw2
sw1
Bank 0
memory
array
(32,768 x 128 x 128)
16,384
RTT(WR)
CK, CK#
13
Rowaddress
MUX
RTT,nom
15
Column 2
(select upper or
lower nibble for BC4)
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© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 6: 78-Ball FBGA – x4, x8 (Top View)
1
2
3
VSS
VDD
VSS
VDDQ
4
5
6
7
8
9
NC
NF, NF/TDQS#
VSS
VDD
VSSQ
DQ0
DM, DM/TDQS
VSSQ
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
NF, DQ6 DQS#
VDD
VSS
VSSQ
A
B
C
D
VSSQ
E
VREFDQ
NF, DQ7 NF, DQ5
VDDQ NF, DQ4
VDDQ
F
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
A15
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
A14
A8
VSS
G
H
J
K
L
M
N
Notes:
PDF: 09005aef84780270
4Gb_DDR3L.pdf - Rev. I 9/13 EN
1. Ball descriptions listed in Table 3 (page 18) are listed as “x4, x8” if unique; otherwise,
x4 and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 3).
16
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4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Figure 7: 96-Ball FBGA – x16 (Top View)
1
2
3
VDDQ
DQ13
VSSQ
4
5
6
7
8
9
DQ15
DQ12
VDDQ
VSS
VDD
VSS
UDQS#
DQ14
VSSQ
VDDQ
DQ11
DQ9
UDQS
DQ10
VDDQ
VSSQ
VDDQ
UDM
DQ8
VSSQ
VDD
VSS
VSSQ
DQ0
LDM
VSSQ
VDDQ
VDDQ
DQ2
LDQS
DQ1
DQ3
VSSQ
VSSQ
DQ6
LDQS#
VDD
VSS
VSSQ
VREFDQ
VDDQ
DQ4
DQ7
DQ5
VDDQ
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
NC
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
A14
A8
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Note:
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4Gb_DDR3L.pdf - Rev. I 9/13 EN
1. A slash defines a selectable function.
17
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4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions
Symbol
Type
Description
[15:13], A12/BC#,
A11, A10/AP, A[9:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during
READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Truth Table - Command in
the DDR3 SDRAM data sheet.
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW)
internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/
disabled is dependent upon the DDR3 SDRAM configuration and operating mode.
Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations
(all banks idle), or active power-down (row active in any bank). CKE is synchronous
for power-down entry and exit and for self refresh entry. CKE is asynchronous for
self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are
disabled during POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to VREFCA.
DM
Input
Input data mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with the input data during a write access.
Although the DM ball is input-only, the DM loading is designed to match that of the
DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on
the x8.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,
and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is
ignored if disabled via the LOAD MODE command. ODT is referenced to REFCA.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to VREFCA.
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and
DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous.
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4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)
Symbol
Type
DQ[3:0]
I/O
Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are
referenced to REFDQ.
DQ[7:0]
I/O
Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are
referenced to VREFDQ.
DQS, DQS#
I/O
Data strobe: Output with read data. Edge-aligned with read data. Input with write
data. Center-aligned to write data.
TDQS, TDQS#
Output
Termination data strobe: Applies to the x8 configuration only. When TDQS is
enabled, DM is disabled, and the TDQS and TDQS# balls provide termination
resistance.
VDD
Supply
Power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation.
VDDQ
Supply
DQ power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation.
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA must be
maintained at all times (including self refresh) for proper device operation.
VREFDQ
Supply
Reference voltage for data:REFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
ZQ
Reference
NC
–
No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
NF
–
No function: When configured as a x4 device, these balls are NF. When configured
as a x8 device, these balls are defined as TDQS#, DQ[7:4].
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4Gb_DDR3L.pdf - Rev. I 9/13 EN
Description
External reference ball for output drive calibration: This ball is tied to an
external 240Ω resistor (RZQ), which is tied to VSSQ.
19
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© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Table 4: 96-Ball FBGA – x16 Ball Descriptions
Symbol
Type
Description
[14:13], A12/BC#,
A11, A10/AP, A[9:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during
READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Truth Table - Command in
the DDR3 SDRAM data sheet.
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle),or active power-down (row active in any bank). CKE is synchronous for powerdown entry and exit and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF
REFRESH. CKE is referenced to VREFCA.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to VREFCA.
LDM
Input
Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte
input data is masked when LDM is sampled HIGH along with the input data during a
write access. Although the LDM ball is input-only, the LDM loading is
designed to match that of the DQ and DQS balls. LDM is referenced to VREFDQ.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS,
LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS,
and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for
the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is
referenced to VREFCA.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to VREFCA.
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20
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© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued)
Symbol
Type
Description
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and
DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous.
UDM
Input
Input data mask: UDM is an upper-byte, input mask signal for write data. Upperbyte input data is masked when UDM is sampled HIGH along with that input data
during a WRITE access. Although the UDM ball is input-only, the UDM loading is
designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ.
DQ[7:0]
I/O
Data input/output: Lower byte of bidirectional data bus for the x16 configuration.
DQ[7:0] are referenced to VREFDQ.
DQ[15:8]
I/O
Data input/output: Upper byte of bidirectional data bus for the x16 configuration.
DQ[15:8] are referenced to VREFDQ.
LDQS, LDQS#
I/O
Lower byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
UDQS, UDQS#
I/O
Upper byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. DQS is center-aligned to write data.
VDD
Supply
Power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation.
VDDQ
Supply
DQ power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation.
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA must be
maintained at all times (including self refresh) for proper device operation.
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
VSS
Supply
Ground.
VSSQ
Supply
ZQ
Reference
NC
–
PDF: 09005aef84780270
4Gb_DDR3L.pdf - Rev. I 9/13 EN
DQ ground: Isolated on the device for improved noise immunity.
External reference ball for output drive calibration: This ball is tied to an
external 240Ω resistor (RZQ), which is tied to VSSQ.
No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
21
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© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Package Dimensions
Package Dimensions
Figure 8: 78-Ball FBGA – x4, x8 (RA)
0.155
Seating plane
A
0.12 A
1.8 CTR
Nonconductive
overmold
78X Ø0.45
Dimensions apply
to solder balls postreflow on Ø0.35 SMD
ball pads.
Ball A1 ID
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
12 ±0.1
9.6 CTR
0.8 TYP
1.1 ±0.1
0.8 TYP
6.4 CTR
0.25 MIN
10.5 ±0.1
Notes:
PDF: 09005aef84780270
4Gb_DDR3L.pdf - Rev. I 9/13 EN
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu)
22
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Package Dimensions
Figure 9: 78-Ball FBGA – x4, x8 (RH)
0.155
Seating plane
A
78X Ø0.45
Dimensions apply
to solder balls postreflow on Ø0.35 SMD
ball pads.
0.12 A
1.8 CTR
Nonconductive
overmold
Ball A1 ID
(covered by SR)
9
8
7
3
2
Ball A1 ID
1
A
B
C
D
E
F
10.5 ±0.1
G
9.6 CTR
H
J
K
L
M
N
0.8 TYP
0.8 TYP
1.1 ±0.1
6.4 CTR
0.25 MIN
9 ±0.1
Notes:
PDF: 09005aef84780270
4Gb_DDR3L.pdf - Rev. I 9/13 EN
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu)
23
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Package Dimensions
Figure 10: 96-Ball FBGA – x16 (RE)
0.155
Seating plane
A
0.12 A
1.8 CTR
Nonconductive
overmold
96X Ø0.45
Dimensions apply
to solder balls
post-reflow on
Ø0.35 SMD ball pads
Ball A1 ID
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
14 ±0.1
12 CTR
0.8 TYP
1.1 ±0.1
0.8 TYP
0.25 MIN
6.4 CTR
10 ±0.1
Notes:
PDF: 09005aef84780270
4Gb_DDR3L.pdf - Rev. I 9/13 EN
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu)
24
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Package Dimensions
Figure 11: 96-Ball FBGA – x16 (HA)
0.155
Seating plane
1.8 CTR
Nonconductive
overmold
96X Ø0.45
Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.
9
8
7
3
A
2
0.12
A
Ball A1 Index
(covered by SR)
1
Ball A1 Index
A
B
C
D
E
F
G
H
12 CTR
J
14 ±0.1
K
L
M
N
P
R
0.8 TYP
T
0.8 TYP
1.1 ±0.1
6.4 CTR
0.25 MIN
9 ±0.1
Notes:
PDF: 09005aef84780270
4Gb_DDR3L.pdf - Rev. I 9/13 EN
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu)
25
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications
Electrical Specifications
Absolute Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 5: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
1
VDD
VDD supply voltage relative to VSS
–0.4
1.975
V
VDDQ
VDD supply voltage relative to VSSQ
–0.4
1.975
V
VIN, VOUT
Voltage on any pin relative to VSS
–0.4
1.975
V
0
95
°C
2, 3
Operating case temperature – Industrial
–40
95
°C
2, 3
Operating case temperature – Automotive
–40
105
°C
2, 3
Storage temperature
–55
150
°C
TC
TSTG
Operating case temperature – Commercial
Notes:
PDF: 09005aef84780270
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1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
greater than 0.6 × VDDQ. When VDD and VDDQ are 85°C: IDD4R, IDD4W, IDD5B, and IDD7 must be derated by 5%; IDD0, IDD1,
IDD2P1, IDD3N, and IDD3P must be derated by 15%; IDD2P0, IDD2Q, IDD2N, and IDD2NT must be
derated by 40%.
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics – DDR3L (1.35V) Operating IDD Specifications
Table 20: IDD Maximum Limits Die Rev E, J
Speed Bin
Parameter
Symbol Width
Operating current 0: One
bank
ACTIVATE-to-PRECHARGE
IDD0
Operating current 1: One
bank ACTIVATE-to-READ-toPRECHARGE
IDD1
Precharge power-down current: Slow exit
DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 Units
Notes
x4, x8
44
47
55
62
mA
1, 2
x16
55
58
66
73
mA
1, 2
x4
53
57
61
65
mA
1, 2
x8
59
62
66
70
mA
1, 2
x16
80
84
87
91
mA
1, 2
IDD2P0
All
18
18
18
18
mA
1, 2
Precharge power-down current: Fast exit
IDD2P1
All
26
28
32
37
mA
1, 2
Precharge quiet standby
current
IDD2Q
All
27
28
32
35
mA
1, 2
Precharge standby current
IDD2N
All
28
29
32
35
mA
1, 2
Precharge standby ODT current
IDD2NT
x4, x8
32
35
39
42
mA
1, 2
x16
35
39
42
45
mA
1, 2
Active power-down current
IDD3P
All
32
35
38
41
mA
1, 2
Active standby current
IDD3N
x4, x8
32
35
38
41
mA
1, 2
Burst read operating current
IDD4R
Burst write operating current
IDD4W
x16
41
45
47
49
mA
1, 2
x4
113
130
147
164
mA
1, 2
x8
123
140
157
174
mA
1, 2
x16
185
202
235
252
mA
1, 2
x4
87
103
118
133
mA
1, 2
x8
95
110
125
141
mA
1, 2
x16
137
152
171
190
mA
1, 2
Burst refresh current
IDD5B
All
224
228
235
242
mA
1, 2
Room temperature self refresh
IDD6
All
20
20
20
20
mA
1, 2, 3
Extended temperature self
refresh
IDD6ET
All
25
25
25
25
mA
2, 4
All banks interleaved read
current
IDD7
x4, x8
160
190
220
251
mA
1, 2
x16
198
217
243
274
mA
1, 2
Reset current
IDD8
All
IDD2P + 2mA
IDD2P + 2mA
IDD2P + 2mA
IDD2P + 2mA
mA
1, 2
Notes:
PDF: 09005aef84780270
4Gb_DDR3L.pdf - Rev. I 9/13 EN
1.
2.
3.
4.
5.
TC = 85°C; SRT and ASR are disabled.
Enabling ASR could increase IDDx by up to an additional 2mA.
Restricted to TC (MAX) = 85°C.
TC = 85°C; ASR and ODT are disabled; SRT is enabled.
The IDD values must be derated (increased) on IT-option devices when operated outside
of the range 0°C ≤ TC ≤ +85°C:
43
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics – DDR3L (1.35V) Operating IDD Specifications
5a. When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD4W must
be derated by 2%; and IDD6, IDD6ET and IDD7 must be derated by 7%.
5b. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B
must be derated by 2%; IDD2Px must be derated by 30%.
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
Electrical Specifications – DC and AC
DC Operating Conditions
Table 21: DDR3L 1.35V DC Electrical Characteristics and Operating Conditions
All voltages are referenced to VSS
Parameter/Condition
Symbol
Min
Nom
Max
Unit
Notes
Supply voltage
VDD
1.283
1.35
1.45
V
1–7
I/O supply voltage
VDDQ
1.283
1.35
1.45
V
1–7
II
–2
–
2
μA
IVREF
–1
–
1
μA
Input leakage current
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V
(All other pins not under test = 0V)
VREF supply leakage current
VREFDQ = VDD/2 or VREFCA = VDD/2
(All other pins not under test = 0V)
Notes:
PDF: 09005aef84780270
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8, 9
1. VDD and VDDQ must track one another. VDDQ must be ≤ VDD. VSS = VSSQ.
2. VDD and VDDQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the
DC (0 Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC
timing parameters.
3. Maximum DC value may not be greater than 1.425V. The DC value is the linear average
of VDD/VDDQ(t) over a very long period of time (for example, 1 second).
4. Under these supply voltages, the device operates to this DDR3L specification.
5. If the maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
6. Under 1.5V operation, this DDR3L device operates in accordance with the DDR3 specifications under the same speed timings as defined for this device.
7. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is
in reset while VDD and VDDQ are changed for DDR3 operation (see VDD Voltage Switching (page 134)).
8. The minimum limit requirement is for testing purposes. The leakage current on the VREF
pin should be minimal.
9. VREF (see Table 22).
45
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© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
Input Operating Conditions
Table 22: DDR3L 1.35V DC Electrical Characteristics and Input Conditions
All voltages are referenced to VSS
Parameter/Condition
Symbol
Min
Nom
Max
Unit
VIN low; DC/commands/address busses
VIL
VSS
N/A
See Table 23
V
VIN high; DC/commands/address busses
VIH
See Table 23
N/A
VDD
V
Notes
Input reference voltage command/address bus
VREFCA(DC)
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
1, 2
I/O reference voltage DQ bus
VREFDQ(DC)
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
2, 3
I/O reference voltage DQ bus in SELF REFRESH
VREFDQ(SR)
VSS
0.5 × VDD
VDD
V
4
VTT
–
0.5 × VDDQ
–
V
5
Command/address termination voltage
(system level, not direct DRAM input)
Notes:
PDF: 09005aef84780270
4Gb_DDR3L.pdf - Rev. I 9/13 EN
1. VREFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC
level. Externally generated peak noise (non-common mode) on VREFCA may not exceed
±1% × VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed ±2% of VREFCA(DC).
2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifications if the DRAM induces additional AC noise greater than 20 MHz in frequency.
3. VREFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC
level. Externally generated peak noise (non-common mode) on VREFDQ may not exceed
±1% × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed ±2% of VREFDQ(DC).
4. VREFDQ(DC) may transition to VREFDQ(SR) and back to VREFDQ(DC) when in SELF REFRESH,
within restrictions outlined in the SELF REFRESH section.
5. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. Minimum and maximum values are system-dependent.
46
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
Table 23: DDR3L 1.35V Input Switching Conditions - Command and Address
Parameter/Condition
Symbol
DDR3L-800/1066
DDR3L-1333/1600
DDR3L-1866
Units
Command and Address
Input high AC voltage: Logic 1
VIH(AC160),min
5
160
160
–
mV
Input high AC voltage: Logic 1
VIH(AC135),min5
135
135
135
mV
Input high AC voltage: Logic 1
VIH(AC125,)min
5
–
–
125
mV
Input high DC voltage: Logic 1
VIH(DC90),min
90
90
90
mV
Input low DC voltage: Logic 0
VIL(DC90),min
–90
–90
–90
mV
Input low AC voltage: Logic 0
VIL(AC125),min5
–
–
–125
mV
Input low AC voltage: Logic 0
VIL(AC135),min
5
–135
–135
–135
mV
Input low AC voltage: Logic 0
VIL(AC160),min
5
–160
–160
–
mV
Input high AC voltage: Logic 1
VIH(AC160),min5
160
160
–
mV
Input high AC voltage: Logic 1
5
135
135
135
mV
5
–
–
130
mV
DQ and DM
VIH(AC135),min
Input high AC voltage: Logic 1
VIH(AC125),min
Input high DC voltage: Logic 1
VIH(DC90),min
90
90
90
mV
Input low DC voltage: Logic 0
VIL(DC90),min
–90
–90
–90
mV
Input low AC voltage: Logic 0
VIL(AC125),min5
–
–
–130
mV
Input low AC voltage: Logic 0
VIL(AC135),min
5
–135
–135
–135
mV
VIL(AC160),min
5
–160
–160
–
mV
Input low AC voltage: Logic 0
Notes:
1. All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All
slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ
and DM inputs.
2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC).
3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC).
4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is
900mV (peak-to-peak).
5. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may
be used for data inputs.
For example, for DDR3-800, two input AC levels are defined: VIH(AC160),min and
VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDR3-800, the address/
command inputs must use either VIH(AC160),min with tIS(AC160) of 210ps or VIH(AC150),min
with tIS(AC135) of 365ps; independently, the data inputs must use either VIH(AC160),min
with tDS(AC160) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps.
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4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
Table 24: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#)
Parameter/Condition
Symbol
Min
Max
Units
Notes
Differential input logic high – slew
VIH,diff(AC)slew
180
N/A
mV
4
Differential input logic low – slew
VIL,diff(AC)slew
N/A
–180
mV
4
Differential input logic high
VIH,diff(AC)
2 × (VIH(AC) - VREF)
VDD/VDDQ
mV
5
Differential input logic low
VIL,diff(AC)
VSS/VSSQ
2 × (VIL(AC) - VREF)
mV
6
Differential input crossing voltage
relative to VDD/2 for DQS, DQS#;
CK, CK#
VIX
VREF(DC) - 150
VREF(DC) + 150
mV
5, 7, 9
Differential input crossing voltage
relative to VDD/2 for CK, CK#
VIX (175)
VREF(DC) - 175
VREF(DC) + 175
mV
5, 7–9
VDDQ/2 + 160
VDDQ
mV
5
VDD/2 + 160
VDD
mV
5
VSSQ
VDDQ/2 - 160
mV
6
VSS
VDD/2 - 160
mV
6
Single-ended high level for strobes
VSEH
Single-ended high level for CK,
CK#
Single-ended low level for strobes
Single-ended low level for CK, CK#
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
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4Gb_DDR3L.pdf - Rev. I 9/13 EN
VSEL
Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ.
Reference is VREFCA(DC) for clock and VREFDQ(DC) for strobe.
Differential input slew rate = 2 V/ns.
Defines slew rate reference points, relative to input crossing voltages.
Minimum DC limit is relative to single-ended signals; overshoot specifications are applicable.
Maximum DC limit is relative to single-ended signals; undershoot specifications are applicable.
The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device,
and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which
differential input signals must cross.
The VIX extended range (±175mV) is allowed only for the clock; this VIX extended range
is only allowed when the following conditions are met: The single-ended input signals
are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2 ±250mV, and
the differential slew rate of CK, CK# is greater than 3 V/ns.
VIX must provide 25mV (single-ended) of the voltages separation.
48
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© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
Figure 13: DDR3L 1.35V Input Signal
VIL and VIH levels with ringback
VDDQ + 0.4V
Overshoot
VDD + 0.4V
Narrow pulse width
Minimum VIL and VIH levels
VIH MIN(AC)
VIH MIN(DC)
VIH(AC)
VIH(DC)
VIL MIN(AC)
VDDQ
VREF + 125/135/160mV
VIH(AC)
VREF + 90mV
VIH(DC)
VREF DC MAX + 1% VDD
VREF + 1% VDD
VREF = VDD/2
VREF - 1% VDD
VREF DC MIN - 1% VDD
MAX 2% Total
VREF DC MAX
VREF
DC MIN
MAX 2% Total
VIL MIN(DC)
VDD
VIL(DC)
VREFDQ + AC noise
VREFDQ + DC error
VREFDQ - DC error
VREFDQ - AC noise
VREF - 90mV
VIL(DC)
VREF - 125/135/160mV
VIL(AC)
VIL(AC)
0.0V
VSS
VSS - 0.40V
Undershoot
VSS - 0.40V
Narrow pulse width
Note:
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1. Numbers in diagrams reflect nominal values.
49
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
DDR3L 1.35V AC Overshoot/Undershoot Specification
Table 25: DDR3L Control and Address Pins
Parameter
DDR3L-800
DRR3L-1066
DDR3L-1333
DDR3L-1600
DDR3L-1866
Maximum peak amplitude allowed
for overshoot area
(see Figure 14)
0.4V
0.4V
0.4V
0.4V
0.4V
Maximum peak amplitude allowed
for undershoot area
(see Figure 15)
0.4V
0.4V
0.4V
0.4V
0.4V
Maximum overshoot area above VDD
(see Figure 14)
0.67 Vns
0.5 Vns
0.4 Vns
0.33 Vns
0.28 Vns
Maximum undershoot area below VSS
(see Figure 15)
0.67 Vns
0.5 Vns
0.4 Vns
0.33 Vns
0.28 Vns
Table 26: DDR3L 1.35V Clock, Data, Strobe, and Mask Pins
Parameter
DDR3L-800
DDR3L-1066
DDR3L-1333
DDR3L-1600
DDR3L-1866
Maximum peak amplitude allowed
for overshoot area
(see Figure 14)
0.4V
0.4V
0.4V
0.4V
0.4V
Maximum peak amplitude allowed
for undershoot area
(see Figure 15)
0.4V
0.4V
0.4V
0.4V
0.4V
Maximum overshoot area above
VDD/VDDQ (see Figure 14)
0.25 Vns
0.19 Vns
0.15 Vns
0.13 Vns
0.11 Vns
Maximum undershoot area below
VSS/VSSQ (see Figure 15)
0.25 Vns
0.19 Vns
0.15 Vns
0.13 Vns
0.11 Vns
Figure 14: Overshoot
Maximum amplitude
Overshoot area
Volts (V)
VDD/VDDQ
Time (ns)
Figure 15: Undershoot
VSS/VSSQ
Volts (V)
Undershoot area
Maximum amplitude
Time (ns)
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
Figure 16: VIX for Differential Signals
VDD, VDDQ
VDD, VDDQ
CK#, DQS#
CK#, DQS#
X
VIX
VIX
VDD/2, VDDQ/2
X
X
VDD/2, VDDQ/2
VIX
X
VIX
CK, DQS
CK, DQS
VSS, VSSQ
VSS, VSSQ
Figure 17: Single-Ended Requirements for Differential Signals
VDD or VDDQ
VSEH,min
VDD/2 or VDDQ/2
VSEH
CK or DQS
VSEL,max
VSEL
VSS or VSSQ
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51
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
Figure 18: Definition of Differential AC-Swing and tDVAC
tDVAC
VIH,diff(AC)min
VIH,diff,min
CK - CK#
DQS - DQS#
0.0
VIL,diff,max
VIL,diff(AC)max
tDVAC
Half cycle
Table 27: DDR3L 1.35V - Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC
Ringback
DDR3L-800/1066/1333/1600
tDVAC
tDVAC
DDR3L-1866
tDVAC
tDVAC
tDVAC
Slew Rate (V/ns)
at
320mV (ps)
at
270mV (ps)
at
270mV (ps)
at
250mV (ps)
at
260mV (ps)
>4.0
189
201
163
168
176
4.0
189
201
163
168
176
3.0
162
179
140
147
154
2.0
109
134
95
105
111
1.8
91
119
80
91
97
1.6
69
100
62
74
78
1.4
40
76
37
52
55
1.2
Note1
44
5
22
24
1.0
Note1
Note1
Note1
Note1
Note1
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