LX7180A
4A Step-Down Regulator
Description
The LX7180A is a 4A step-down regulator with
integrated MOSFETs packaged in a space saving
QFN12 2 mm x 2 mm for today’s mobile devices. It uses
an ultra-fast, constant frequency hysteretic control
method to minimize external filter components while
maintaining excellent regulation. The LX7180A reference
voltage is programmable from 0.6 V to 1.195 V through a
high speed (up to 3.4 MHz), bi-directional I2C bus.
The LX7180 operates from 3 V to 5.5 V rails and outputs
0.6 V to 100% of the input voltage.
Cycle-by-cycle current limiting protects against overcurrent conditions. Hiccup mode provides protection for
heavy over-load or short-circuit faults. Thermal
protection shuts down the regulator under overtemperature conditions. Over voltage conditions will
immediately shut off the output to protect against
permanent damage. The LX7180A automatically restarts
when all fault conditions are cleared.
Features
0-4 A Step-down Regulator
Operational Input Supply Voltage Range:
3.0 V - 5.5 V (short durations to 6.5 V)
Hysteretic Control Offers Best Transient Response
PWM Switching at a Constant 1.65 MHz
Power Save Mode (PSM) can be Selected to
Improve Light Load Efficiency.
100% Duty Ratio Operation
Input Under Voltage and Over Voltage Protection
Enable and Power Good Function
I2C Serial Interface at 3.4 Mbps
Internal Soft-start
Cycle-by-Cycle Over Current Protection
Hiccup Mode Protects Against Short Circuit Faults
Seven Bit Adjustable Reference Voltage via I2C Bus
RoHS Compliant
Applications
High Performance HDD
LCD TV
Notebook/Netbook
Server and Workstations
Video Cards
PoE Powered Devices Smart Phone
SW
VIN
1, 10
GND
10 µF
X5R
PVIN
SW
10 µF
X5R
8
EN
FB
LX7180A
2, 11
0.47 µH
7
VOUT
22 µF,
X5R
GND
SCL 5
500 k
9
SDA 6
PG
PGND
3, 12
AGND
4
PGOOD
Figure 1 · Typical Application of LX7180A
June 2015 Rev. 1.2
www.microsemi.com
© 2015 Microsemi Corporation
1
4A Step-Down Regulator
Pin Configuration and Pinout
Figure 2 · Pinout Top View
Marking: “x” is the 2LSB bits of the binary I2C slave Address
“1” is for the set output voltage
YWWL = Year/Week/Lot Code
RoHS / Pb-free Matte Tin Pin Finish
Ordering Information
Ambient
Temperature
Type
Package
Slave
Address
Set
Output
Voltage
0
0.9 V
1
0°C to 85°C
QFN 2X2 mm
12L
LX7180A - xyCLQ*
0.9 V
LX7180A - 01CLQ-TR
1
LX7180A - 11CLQ-TR
2
LX7180A - 21CLQ-TR
3
LX7180A - 31CLQ-TR
LX7180A - xyCLQ-TR*
Note: 1. * Consult factory for other I2C slave address and set output voltage options.
2. “x” is the 2 LSB bits of the binary I2C slave address (0 to 3).
3. “y” is the set output voltage (0 is 0.6 V, 1 is 0.9 V, 2 is 0.95 V, 3 is 0.97 V).
2
Bulk
LX7180A - 31CLQ
3
0
Packaging
Type
LX7180A - 01CLQ
LX7180A - 11CLQ
LX7180A - 21CLQ
2
RoHS
Compliant,
Pb-free
Part Number
Tape and Reel
Pin Description
Pin Description
Pin Number
Pin Designator
Description
1, 10
PVIN
Supply Voltage. Bypass PVIN to ground plane as close as possible to the IC.
2, 11
3, 12
SW
PGND
Switch Output. Drives the external L-C filter.
Power Ground. Connect to ground plane.
4
AGND
Analog Ground. Connect to ground plane.
5
SCL
I2C Serial Clock Digital Input.
6
SDA
I2C Serial Data. Digital Input/Output.
7
FB
8
EN
9
PG
Feedback – Analog input, monitors the output voltage either directly or
through a resistor divider.
Enable – Digital input. Force high to enable the IC.
Power Good – Open drain digital output. Pulls low to indicate a fault
condition. Requires an external pull up resistor.
Block Diagram
Figure 3 · Block Diagram of LX7180A
3
4A Step-Down Regulator
Absolute Maximum Ratings
Parameter
PVIN, EN, PG, SCL, SDA, SW to GND
Min
-0.3
Max
7
Units
V
AGND to GND
SW to GND (Shorter than 50 ns)
-0.3
-2
0.3
7
V
V
Junction Temperature Range
Storage Temperature Range
-10
-65
150
150
°C
°C
260 (+0, -5)
°C
Peak Lead Soldering Temperature (40s, reflow)
Note: Performance is not necessarily guaranteed over this entire range. These are maximum stress ratings only. Exceeding
these ratings, even momentarily, can cause immediate damage, or negatively impact long-term operating reliability.
Operating Ratings
Performance is generally guaranteed over this range as further detailed are provided in Electrical
Characteristics section.
Parameter
Input Voltage
Min
3.0
Max
5.5
Units
V
Output Voltage
Output Current (VIN = 3 V to 5 V)
0.6
0
5.5
4
V
A
0
85
°C
Ambient Temperature
Note: Corresponding Max Junction Temperature is 125°C.
Thermal Properties
Thermal Resistance(θJA)
QFN 2x2mm 12L
Typ
Units
30
°C/W
Note: The θJA number assumes no forced airflow. Junction Temperature is calculated using TJ = TA + (PD x θJA). In particular, θJA
is a function of the PCB construction. The stated number above is for a four-layer board in accordance with JESD-51
(JEDEC).
4
Electrical Characteristics
Electrical Characteristics
Unless otherwise specified, the following specifications apply over the operating ambient temperature of
0°C ≤ TA ≤ 85°C with the following test conditions: PVIN = 5 V. Typical parameters refers to TJ = 25°C. VOUT
is connected directly to FB for closed loop tests (default test condition). VREF is set to 0.9 V. VOUT is
disconnected from FB for open loop tests. Default registers settings. Iload = 0. EN=high. GBD specifications
are guaranteed by design and/or characterization and are not tested on a production basis. SCL and SDA
set to PVIN.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VIN
IQPSM
ISLEEP
IIn_I2C
UVLORISING
UVLOHYST
OVPR
OVPF
PSM Bias Current
Input Current at
Shutdown
I2C Shutdown Sleep
Current
Under Voltage Rising
Threshold
Enable PSM. Force FB to 1 V open
EN = low
0.1
Set VSEL(7)=low, EN=high.
20
PVIN rising
UVLO Hysteresis
PVIN falling
Over Voltage Rising
PVIN rising. Will also trigger on
Threshold
DV/DT > 1 V/µs
Over Voltage Falling
Threshold
350
loop.
µA
3
µA
µA
2.8
V
0.2
V
6.1
V
5.85
V
VSEL(6:0) = 00h.
0.6
V
VSEL(6:0) = 40h.
0.9
V
VSEL(6:0) = 7Fh.
1.195
V
5
mV/µs
1.2
ms
PVIN falling
5.5
VREF
VREFMIN
VREFMEAN
VREFMAX
Minimum Reference
Voltage
Mean Reference
Voltage
Maximum Reference
Voltage
TSS
VREF Slew Rate
THICCUP
Hiccup Time
FB
Enable PWM.
VSEL(6:0) = 40h
VFBSET
VFB Set Point
Enable PWM.
Accuracy
VSEL(6:0) = 00h
Enable PWM.
VSEL(6:0) = 7Fh
0.891
0.9
0.909
V
0.591
0.6
0.609
V
1.177
1.195
1.213
V
0.886
0.9
0.914
V
Enable PWM. TA = 25°C
PVIN = 3 V, IOUT = 0 A
VFBPWM
PWM FB Accuracy
PVIN = 3 V, IOUT = 1 A
PVIN = 5.5 V, IOUT = 0 A
PVIN = 5.5 V, IOUT = 1 A, Note 1
5
4A Step-Down Regulator
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.882
0.9
0.918
V
Enable PSM. TA = 25°C
PVIN = 3 V, IOUT = 0 A
VFBPSM
PSM FB Accuracy
PVIN = 3 V, IOUT = 1 A
PVIN = 5.5 V, IOUT = 0 A
PVIN = 5.5 V, IOUT = 1 A, Note 1
VFBLRPWM
PWM Load
Regulation
ILOAD = 0 A to 4 A. Note 1
-0.17
%/A
0.06
%/V
0.07
%/V
VOUT = 0.9 V. PVIN from 3 V to 5.5 V,
PWM Line Regulation
Enable PWM, ILOAD = 0.1 A.
Note 1
PSM Line Regulation
FBIL
FBUV
RDISC
VOUT = 0.9 V. PVIN from 3 V to 5.5 V,
Enable PSM, ILOAD = 0.1 A. Note 1
FB Input Current
1
FB Under Voltage
VOUT below this threshold will initiate
Threshold
a hiccup sequence.
Output Discharge
Resistance
EN = low
80
80
314
µA
%VREF
500
Ω
SW
RDSON_H
RDSON_L
High Side On
Resistance
Low Side On
Resistance
IRATED
Rated Output Current
ICL
Current Limit
TSH
TH
FSW
Thermal Shutdown
Threshold
Thermal Shutdown
Hysteresis
PWM Switching
Frequency
PVIN = 3 V to 5 V.
Note 1
Peak inductor current.
PVIN = 3 V to 5 V.
Note 1
46
mΩ
21
mΩ
4
5.7
A
7
8.6
A
Note 1
150
°C
Note 1
20
°C
VOUT ≥ 1.8 V, T=25°C
1.55
1.65
1.75
MHz
1.1
V
EN, SDA (as input), SCL
VIH
Input High
VIL
Input Low
IIN
Input Current
0.4
V
0.01
1
µA
PG
VPG90
VPG110
6
PGOOD VOUT Lower
Threshold
PGOOD VOUT Upper
Threshold
VOUT rising
90
% VREF
VOUT falling
110
% VREF
Typical Performance Curves -- (Efficiency)
Symbol
VPGHY
Parameter
Conditions
Min
Hysteresis
PGRDSON
PGILEAK
PGDELAY
Typ
Max
5
PGOOD Pull-down
Resistance
PGOOD Leakage
TJ = 25°C
Current
PGOOD Delay
25
Units
% VREF
13
50
Ω
0
1
µA
45
65
ms
Note: These parameters are not tested, but guaranteed by design and characterization.
Typical Performance Curves -- (Efficiency)
100%
90%
80%
Efficiency
70%
60%
50%
40%
30%
20%
PSM
PWM
10%
0%
0.1
1
10
100
Load Current (mA)
1000
10000
Figure 4 · LX7180A Efficiency with VIN = 5 V, VOUT = 0.9 V, L = 1.0 µH, COUT = 66 µF
7
4A Step-Down Regulator
Step Response (Load Current = 2A to 4A, L= 0.47 µH, COUT= 22 µF)
IOUT= 0.5A
92
IOUT= 1.0A
84
76
68
Output Voltage (V)
Efficiency (%)
100
2.51
2.50
2.49
2.48
2.47
2
3
4
5
6
0
600
800
Figure 6 · Step Response Rising Edge
Figure 7 · Step Response Falling Edge
8
400
Output Current (mA)
Input Voltage (V)
Figure 5 · Step Response
200
1000
I2C Timing Specifications
I2C Timing Specifications
Table 1 · I2C Timing Specifications
Symbol
Parameter
fSCHL
SCLH and SCL clock
frequency
tSU;STA
Conditions
Cb = 100 pF (max)
(Note 2)
Min
Max
Cb = 400 pF
Unit
Min
Max
0
3.4
0
0.4
MHz
Set-up time for a repeated
START condition
160
-
600
-
ns
tHD;STA
Hold time (repeated) START
condition
160
-
600
-
ns
tLOW
LOW period of the SCL
clock
160
-
1300
-
ns
tHIGH
HIGH period of the SCL
clock
60
-
600
-
ns
tSU;DAT
Data set-up time
10
-
100
-
ns
tHD;DAT
Data hold time
47
70
0
-
ns
Rise time of SCLH signal
Rise time of SCLH signal
after a repeated START
condition and after an
acknowledge bit
10
40
20*0.1Cb
300
ns
10
80
20*0.1Cb
300
ns
tfCL
Fall time of SCLH signal
10
40
20*0.1Cb
300
ns
trDA
Rise time of SDAH signal
10
80
20*0.1Cb
300
ns
tfDA
Fall time of SDAH signal
10
80
20*0.01Cb
300
ns
tSU;STO
Set-up time for STOP
condition
160
-
600
-
ns
tBUF
Bus free time between a
STOP and START condition
Data valid time
160
-
1300
-
ns
-
160
-
900
ns
-
160
-
900
ns
SDAH and SCLH
lines
-
100
400
pF
SDAH + SDA line
and SCLH + SCL
line
-
400
400
pF
trCL
trCL1
tVD;DAT
tVD;ACK
Cb
Data valid acknowledge time
Capacitive load for each bus
line
Note: 1. All values referred to VIH (min) and VIL (max) levels of I/O stages table.
2. Loads in excess of 100 pf will restrict bus operation speed below 3.4 MHz.
9
4A Step-Down Regulator
Theory of Operation / Application Information
Basic Operation
The LX7180A compares the FB voltage to an internal reference, VREF. When FB is lower than VREF, the upper
switch turns on and the lower switch turns off. When FB is higher than VREF, the upper switch turns off and the
lower switch turns on. An internal ramp and a frequency control loop keep the switching frequency constant
when in constant conduction mode (CCM) over a wide range of output capacitor values and parasitic
components (i.e. ESR, ESL).
At light loads, if enabled, the converter automatically reduces the switching frequency to optimize efficiency.
An integrated I2C bus interface, operating up to 3.4 Mbps, allows the following user programmability to the
converter:
•
On the fly programming of the reference voltage in 4.7 mV increments.
•
Enable / Disable the regulator.
•
Enable power save mode (PSM) or limit operation to continuous conduction only (PWM).
•
Set the VREF slew rate.
•
Enable/Disable VIN over voltage protection.
•
Force PGOOD to respond to both under and over voltages or just under voltage.
Setting the Output Voltage
The reference voltage can be programmed with the I2C bus VSEL register value.
VREF = 0.6 V + VSEL ⋅ 0.0047 V …………………. (2)
Where VSEL is programmable from 0 to 127.
Startup
The LX7180A is enabled when EN is high and PVIN rises above the UVLO threshold. At start up, after all
the internal bias voltages and currents stabilize, VREF ramps up from 0 V to the target voltage at the defined
slew rate. While VREF ramps, PGOOD is held low. At the end of the ramp time, PGOOD is allowed to go
high 45 ms after FB has reached the PGOOD rising threshold. During the ramp time, the LX7180A always
runs in PSM to allow discontinuous operation. This switchover is independent of the programmed MODE bit
setting.
Over Current Protection
The LX7180A protects against all types of short circuit conditions. Cycle-by-cycle over current protection
turns off the upper switch when the current exceeds the ICL threshold. When this occurs, the upper switch is
kept off for about 360 ns before being allowed to turn on again. After startup, if FB drops below the FBUV
threshold, a hiccup sequence will be initiated where both output switches are shut off for 1.2 ms before
initiating another soft start. This protects against a crowbar short circuit. FB under voltage detection is not
active during startup.
10
Recommended Output Filter Components
Recommended Output Filter Components
The following tables show the recommended feedback component values (RHIGH, RLOW, Cff) for different
input/output voltages, power inductor (L), and output capacitance (C) values that result in optimum closed
loop response of the regulator in each case. The estimated crossover frequency is also shown in the table in
each case. If the L*C factor exceeds a certain number the regulator would run with low phase margin or
become unstable. The L and C range provided in the table provides 30°, or higher of phase margin.
Therefore, it is not recommended to increase L*C factor beyond what is given in the table.
It is a good practice to determine L such that the peak-to-peak inductor ripple current in continuous
conduction mode operation is roughly equal to 30% of converter’s rated output current. In general,
increasing the inductance slows down the closed loop response of the regulator. Hence, for applications that
require fast line/load transient response, lower inductance values should be preferred over larger ones.
Output capacitance can be determined based on desired output ripple voltage staying within the limits
provided in the table depending on the inductance value.
VIN
1
GND
10
10 µF
X5R
10 µF
X5R
8
SW
PVIN
VIN
EN
L
VOUT
Cff
LX7180A
FB
RHIGH
7
COUT
GND
RLOW
SCL 6
500 k
9
PGOOD
2, 11
SDA 5
PGOOD
PGND
3, 12
AGND
4
11
4A Step-Down Regulator
Recommended Output Filter Components - Continued
VIN
(V)
VOUT
(V)
L
(µH)
2.2
COUT
(µF)
RHIGH
(kΩ)
RLOW
(kΩ)
Cff
(pF)
2x22
110
1x22
180
4x22
1.5
1.0
5.0
0.9
0.33
Note: VREF = 0.6 V, if FB network exists.
12
95
3x22
110
2x22
140
1x22
240
5x22
110
4x22
120
3x22
140
2x22
0.47
F
crossover (kHz)
0
∞
none
190
1x22
325
5x22
170
4x22
200
3x22
240
2x22
350
1x22
650
5x22
220
4x22
260
3x22
325
2x22
475
Recommended Output Filter Components - Continued
Recommended Output Filter Components - Continued
VIN
(V)
VOUT
(V)
L
(µH)
2.2
1.5
1.0
3.0
COUT
(µF)
0.47
0.33
RLOW
(kΩ)
Cff
(pF)
F crossover
(kHz)
1x22
130
2x22
110
1x22
162
3x22
110
2x22
140
1x22
220
5x22
120
4x22
0.9
RHIGH
(kΩ)
0
∞
none
140
3x22
170
2x22
220
1x22
400
5x22
150
4x22
180
3x22
220
2x22
300
1x22
550
13
4A Step-Down Regulator
Recommended Output Filter Components – Continued
VIN
(V)
VOUT
(V)
L
(µH)
COUT
(µF)
RHIGH
(kΩ)
RLOW
k(Ω)
Cff
(pF)
49
5x22
20
4x22
2.2
2x22
15
150
5x22
58
4x22
68
15
3x22
240
120
1.0
120
200
5x22
77
15
3x22
8
260
5x22
110
4x22
130
8
3x22
120
475
5x22
4x22
150
240
120
1x22
190
8
3x22
2x22
180
190
60
1x22
14
130
1x22
2x22
0.33
92
120
2x22
0.47
84
1x22
4x22
1.8
85
1x22
2x22
5.0
57
70
3x22
1.5
F
crossover (kHz)
60
30
260
220
500
Recommended Output Filter Components – Continued
Recommended Output Filter Components – Continued
VIN
(V)
VOUT
(V)
L
(µH)
COUT
(µF)
RHIGH
(kΩ)
RLOW
(kΩ)
Cff
(pF)
36
5x22
20
4x22
2.2
3x22
15
1x22
1.8
4x22
49
3x22
15
79
1x22
140
55
240
120
15
3x22
1x22
0.33
60
2x22
2x22
0.47
100
42
4x22
1.0
60
5x22
5x22
3.0
42
50
2x22
1.5
F crossover
(kHz)
64
79
8
87
150
5x22
76
4x22
89
3x22
8
110
2x22
160
1x22
350
5x22
97
4x22
120
3x22
8
150
2x22
240
1x22
525
15
4A Step-Down Regulator
Recommended Output Filter Components – Continued
VIN
(V)
VOUT
(V)
L
(µH)
2.2
COUT
(µF)
RHIGH
(kΩ)
RLOW
(kΩ)
58
4x22
67
2x22
81
3x22
110
3.3
1.0
0.47
30
75
4x22
87
3x22
100
2x22
140
540
240
120
5x22
100
4x22
120
43
3x22
190
1x22
325
5x22
170
4x22
200
43
3x22
1x22
240
350
225
50
8
450
5x22
220
4x22
260
3x22
540
120
30
2x22
1x22
16
140
2x22
2x22
0.33
170
5x22
1x22
5.0
F crossover
(kHz)
5x22
1x22
1.5
Cff
(pF)
325
475
135
30
8
525
Theory of Operation – Continued
Theory of Operation – Continued
Positive Voltage Transitions
After the initial start-up sequence, the output voltage can be programmed to a new value by
Programming the VSEL register bits and then asserting the GO bit. VREF will transition to the new value at
the programmed slew rate. During the transition time the PGOK bit will be low and will go high when the
transition completes.
GO Bit Set
VOUT
PGOK
PGOOD
Figure 8 · Positive Voltage Transition
Negative Voltage Transitions
A negative voltage transition occurs when a lower output voltage is programmed into the Vsel register, and
initiated by asserting the GO bit. During the transition, when in PFM mode of operation, the upper PGOOD
threshold is disabled if set.
GO Bit Set
VOUT
PGOK
PGOOD
Figure 9 · Negative Voltage Transition
17
4A Step-Down Regulator
If the FB voltage does not drop within 10% of the programmed voltage within 30 ms, then PGOOD will go
low. During a transition when in PWM only mode of operation, the PGOOD thresholds will not be disabled
but will trigger if the output falls outside the 10% tolerance window around the ramped programmed voltage.
GO Bit Set
VOUT
30ms
PGOK
PGOOD
Figure 10 · Negative Voltage Transition PGOOD Fail
Enabling Regulator from I2C Bus
In addition to the EN pin, the regulator can be enabled and disabled via the I2C bus by programming the
control register. During disable, the regulator and most of the support circuitry is turned off. However, the
I2C bus circuitry is still active and may be programmed.
I2C Interface
I2C Port Functional Description
•
Simple two wire, bidirectional, serial communication port.
•
Multiple devices on same bus speeds from 400 kbps (FS-Mode) to 3.4 Mbps (HS-Mode).
•
SOC Master controls bus.
•
Devices listen for the unique address that precedes data.
General I2C Port Description
The LX7180A includes an I2C compatible serial interface, using two dedicated pins: SCL and SDA for I²C
clock and data respectively. Each line is externally pulled up to a logic voltage when they are not being
controlled by a device on the bus. The serial port is an I²C slave that is clocked by the incoming SCL clock.
The I²C port will support both the Fast mode (400 kHz max) and typically the High speed mode (3.4 MHz
max). The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). The state
of the SDA line can only be changed when SCL is LOW (except for start, stop, and restart).
Register Map
There are five 8-bit user-accessible registers. See the register map Table 2.
18
I2C Interface (Continued)
I2C Interface (Continued)
Slave Address
In the Table 2, the A1 and A0 are the binary value of the address given in the Ordering Information.
7
1
6
1
5
0
4
1
3
0
2
A1
1
A0
0
R/W
Table 2 · I2C Slave Address
START and STOP Commands
When the bus is idle, both SCL and SDA must be high except in the power up case where they may be held
high or low during the system power up sequence.
The STX SOC (bus master) signals START and STOP bits signify the beginning and the end of the I2C
transfer. The START condition is defined as the SDA signal transitioning from HIGH to LOW while the SCL
line is HIGH. The STOP condition is defined as the SDA transitioning from LOW to HIGH while the SCL is
HIGH. The STX SOC acts as the I2C master and always generates the START and STOP bits. The I2C bus
is considered to be busy after START condition and free after STOP condition. During data transfer, STX
SOC master can generate repeated START conditions. The START and the repeated START conditions
are functionally equivalent.
Data Transfers
Data is transferred in 8 bit bytes by SDA with the MSB transferred first. Each byte of data has to be followed
by an acknowledge (ACK) bit. The acknowledged related clock pulse is generated by the master. The
acknowledge occurs when the transmitter master releases the SDA line to a high state during the
acknowledge clock. The SDA line must be pulled down by the receiver slave during the 9th clock pulse to
signify acknowledgment. A receiver slave which has been addressed must generate an acknowledgement
(“ACK”) after each byte has been received.
After the START condition, the STX SOC (I2C) master sends a chip address. The standard I2C address is
seven bits long. Making the eighth bit a data direction bit (R/W). For the eighth bit (LSB), a “0” indicates a
WRITE and a “1” indicates a READ. (For clarification, communications are broken up into 9-bit segments,
one byte followed by one bit for acknowledging.) The second byte selects the register to which the data will
be written. The third byte contains data to write to the selected register.
When a receiver slave doesn’t acknowledge the slave address, the data line must be left HIGH by the slave.
The master can then generate a STOP command to abort the transfer. If a slave receiver does acknowledge
the slave address but, sometime later in the transfer cannot receive any more data bytes, the master must
again abort the transfer. This is indicated by the slave generating the not acknowledge on the first byte to
follow.
The slave leaves the data line HIGH and the master generates the STOP command. The data line is also
left high by the slave and master after a slave has transmitted a byte of data to the master in a read
operation, but this is a not acknowledge that indicates that the data transfer is successful.
Data Transfer Timing for Write Commands
In order to help assure that bad data is not written into the part, data from a write command is only stored
after a valid STOP command has been performed.
19
4A Step-Down Regulator
I2C Electrical Characteristics
The minimum HIGH and LOW periods of the SCL clock are specified in the I2C Specifications, Table 1
determine the maximum bit transfer rates of, 400 kbit/s for Fast-mode devices, and 3.4 Mbits/s for HS-mode
Plus. Devices must be able to follow transfers at their own maximum bit rates, either by being able to
transmit or receive at that speed or by applying the I2C clock synchronization procedure, which will force the
master into a wait state and stretch the LOW period of the SCL signal. Of course, in the latter case the bit
transfer rate is reduced.
Figure 13 and Figure 14 show all timing parameters for the HS & FS-mode timing. The ‘normal’ START
condition S does not exist in HS-mode. Timing parameters for Address bits, R/W bit, Acknowledge bit and
DATA bits are all the same. Only the rising edge of the first SCL clock signal after an acknowledge bit has a
larger value because the external Rp has to pull-up SCL without the help of the internal current-source.
The HS & FS-mode timing parameters for the bus lines are specified in the I2C Specifications
Table 1. The minimum HIGH and LOW periods and the maximum rise and fall times of the SCL clock signal
determine the highest bit rate.
With an internally generated SCL signal with LOW and HIGH level periods of 200 ns and 100 ns
respectively, an HS-mode master fulfills the timing requirements for the external SCL clock pulses (taking
the rise and fall times into account) for the maximum bit rate of 3.4 Mbit/s. So a basic frequency of 10 MHz,
or a multiple of 10 MHz, can be used by an HS-mode master to generate the SCL signal. There are no limits
for maximum HIGH and LOW periods of the SCL clock, and there is no limit for a lowest bit rate.
Timing parameters are independent for capacitive load up to 100 pF for each bus line allowing the maximum
possible bit rate of 3.4 Mbit/s. At a higher capacitive load on the bus lines, the bit rate decreases gradually.
The timing parameters for a capacitive bus load of 400 pF are specified in I2C Specifications Table 1,
allowing a maximum bit rate of 1.7 Mbit/s. For capacitive bus loads between 100 pF and 400 pF, the timing
parameters must be interpolated linearly. Rise and fall times are in accordance with the maximum
propagation time of the transmission lines SDA and SCL to prevent reflections of the open ends.
Figure 11 · Write Protocol
Figure 12 · Read Protocol
20
I2C Interface (Continued)
I2C Interface (Continued)
Figure 13 · Definition for FS-Mode devices on the I2C Port
Figure 14 · Timing definition for HS-mode devices on the I2C Port
21
4A Step-Down Regulator
I2C Interface (Continued)
Figure 15 · Write Cycle Diagram
Figure 16 · Read Cycle Diagram
Control Register Bit Definition
Bit
Name
Value
Description
Status, Address 00h
7:3
Reserved
2
OCP
0-d
1
OTP
0-d
0
FB_UVLO
0-d
Latched to 1 if the over current limit is reached. Write a “1” to reset the
status flag.
Latched to 1 if an over temperature event occurs. Write a “1” to reset the
status flag.
Latched to 1 if a FB_UVLO event occurs. Write a “1” to reset the status
flag.
VSEL, Address 01h, (aka dac)
7
6:0
EN
1-d
Device enabled.
0
Device disabled.
VSEL[6:0]
7-bit DAC value to set VREF. The default value is 0.9 V.
Ctrl1, Address 02h, (aka reg2)
7:6
Reserved
00-d
5
DLY_DIS
1-d
45 ms delay on PGOOD is disabled when this bit is high.
4
ctrl1
0-d
Not used
3
SW_RATE
1-d
Normal high efficiency rise rate.
22
Control Register Bit Definition
Bit
Name
Value
0
1-d
2
PG_LOHI
0
1
1-d
VIN_OVP
0
1-d
0
MODE
0
Description
Reduced switch node rise rate.
PGOOD will detect both a positive and negative excursion of VOUT from
the reference.
PGOOD senses only a negative voltage excursion of VOUT from the
reference.
When VIN reaches VIN Max, the converter turns off.
VIN OVP disabled. Converter will continue to operate
PWM – Always run in continuous conduction
PSM – Power Save Mode allows the converter to run in discontinuous
conduction
Vendor ID, Address 03h (Read Only)
7:4
VID[3:0]
0010
Microsemi Vendor ID.
3:2
A1A0
00
1:0
VREF
01
two LSB bits.
Designates the default output voltage version, 00 = 0.6 V, 01 = 0.9 V,
10 = 1.0 V, 11 = 1.1 V.
1
Write “1” to this bit to start a Vref transition
Designates the slave address version. These bits will correspond to the
Ctrl2, Address 04h, (aka reg4)
7:6
5
4
Reserved
GO
Discharge
0-d
1
0-d
3
2:0
PGOK
SLEW
The VOUT is ramped to the default VSEL Value.
When the regulator is disabled, the output voltage is discharged through
the SW pin.
When the regulator is disabled, the output voltage is not discharged.
1
Is high when output is in regulation, read only dynamic signal
0
Is low during a output voltage transition, read only dynamic signal
000
Reserved.
001
Reserved.
010
VREF slews at 2.5 mV/μs.
011-d
VREF slews at 5 mV/μs; this is the default setting.
100
VREF slews at 10 mV/μs.
101
VREF slews at 20 mV/μs.
110
VREF slews at 40 mV/μs.
111
Single Step Mode: No slew rate limiting.
23
4A Step-Down Regulator
Package Outline Dimensions
D2
D
DIM
L
10
b
9
1
8
2
7
3
E
e
6
4
5
Top View
b
Bottom View
A
A3
MILLIMETERS
MIN
MAX
INCHES
MIN
MAX
A
A3
0.80
1.00
0.20 REF
0.031
0.039
0.008 REF
B
D
0.20
1.90
0.008
0.075
D2
E
0.50 BSC
1.90
2.10
0.02 BSC
0.075
0.083
e
L
0.50 BSC
0.30
0.45
0.020 REF
0.012
0.018
0.30
2.10
0.012
0.083
Side View
Figure 17 · QFN 2x2mm 12L Package Dimensions
Note: 1. Dimensions do not include mold flash or protrusions; these shall not exceed 0.155 mm (.006”) on any side. Lead
dimension shall not include solder coverage.
2. Dimensions are in millimeters, inches for reference only.
Land Pattern Recommendation
2.20 mm
0.55 mm
0.55 mm
0.50 mm
2.20 mm
0.30 mm
0.70 mm
Disclaimer:
This PCB land pattern recommendation is based on information available to Microsemi by its suppliers. The actual land pattern to be used could be different depending on the
materials and processes used in the PCB assembly, end user must account for this in their final layout. Microsemi makes no warranty or representation of performance based
on this recommended land pattern.
24
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Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
be used in conjunction with mission-critical equipment or applications. Any performance specifications are
believed to be reliable but are not verified, and Buyer must conduct and complete all performance and
other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not
rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s
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information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the
entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly
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