19-6029; Rev 0; 9/11
EVALUATION KIT AVAILABLE
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
General Description
The MAX3636 is a highly flexible, precision phase-locked
loop (PLL) clock generator optimized for the next generation of network equipment that demands low-jitter
clock generation and distribution for robust high-speed
data transmission. The device features subpicosecond
jitter generation, excellent power-supply noise rejection,
and pin-programmable LVDS/LVPECL output interfaces.
The MAX3636 provides nine differential outputs and one
LVCMOS output, divided into three banks. The frequency
and output interface of each output bank can be individually programmed, making this device an ideal replacement for multiple crystal oscillators and clock distribution
ICs on a system board, saving cost and space.
This 3.3V IC is available in a 7mm x 7mm, 48-pin TQFN
package and operates from -40°C to +85°C.
Applications
Ethernet Switches/
Routers
PCIe®, Network
Processors
Wireless Base Stations
Fibre Channel SAN
Features
S Inputs
Crystal Interface: 18MHz to 33.5MHz
LVCMOS Input: 15MHz to 160MHz
Differential Input: 15MHz to 350MHz
S Outputs
LVCMOS Output: Up to 160MHz
LVPECL/LVDS Outputs: Up to 800MHz
S Three Individual Output Banks
Pin-Programmable Dividers
Pin-Programmable Output Interface
S Wide VCO Tuning Range (3.60GHz to 4.025GHz)
S Low Phase Jitter
0.34psRMS (12kHz to 20MHz)
0.14psRMS (1.875MHz to 20MHz)
S Excellent Power-Supply Noise Rejection
S -40NC to +85NC Operating Temperature Range
S 3.3V Supply
Ordering Information appears at end of data sheet.
SONET/SDH Line Cards
Functional Diagram
LVPECL/LVDS
QA0
QA0
LVPECL/LVDS
MAX3636
QA1
QA1
LVPECL/LVDS
QA2
QA2
XOUT
LVPECL/LVDS
XO
QA3
XIN
LVPECL/LVDS
LVCMOS
CIN
QA3
QA4
PLL, DIVIDERS, MUXES
VCO
QA4
LVPECL/LVDS
QB0
QB0
LVPECL
LVPECL/LVDS
DIN
DIN
QB1
QB1
LVPECL/LVDS
QB2
QB2
LVPECL/LVDS
QC
QC
LVCMOS
QCC
PCIe is a registered trademark of PCI-SIG Corp.
1
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (VCC, VCCA, VCCQA,
VCCQB, VCCQC, VCCQCC).................................-0.3V to +4.0V
Voltage Range at CIN, IN_SEL, DM, DF[1:0],
DP[1:0], PLL_BP, DA[1:0], DB[1:0], DC[1:0],
QA_CTRL1, QA_CTRL2, QB_CTRL,
QC_CTRL, QCC.................................... -0.3V to (VCC + 0.3V)
Voltage Range at DIN, DIN......... (VCC - 2.35V) to (VCC - 0.35V)
Voltage Range at QA[4:0], QA[4:0], QB[2:0],
QB[2:0], QC, QC when LVDS Output... -0.3V to (VCC + 0.3V)
Current into QA[4:0], QA[4:0], QB[2:0], QB[2:0],
QC, QC when LVPECL Output...................................... -56mA
Current into QCC.............................................................. Q50mA
Voltage Range at XIN............................................-0.3V to +1.2V
Voltage Range at XOUT..............................-0.3V to (VCC - 0.6V)
Continuous Power Dissipation (TA = +70NC)
TQFN (derate 40mW/NC above +70NC).....................3200mW
Operating Junction Temperature Range.......... -55NC to +150NC
Storage Temperature Range............................. -65NC to +160NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted. Signal applied to
CIN or DIN/DIN only when selected as the reference clock.) (Notes 1, 2)
PARAMETER
Supply Current with PLL
Enabled (Note 3)
SYMBOL
ICC
Supply Current with PLL
Bypassed (Note 3)
CONDITIONS
MIN
TYP
MAX
Configured with LVPECL outputs
170
215
Configured with LVDS outputs
290
365
Configured with LVPECL outputs
110
Configured with LVDS outputs
230
UNITS
mA
mA
LVCMOS/LVTTL CONTROL INPUTS (IN_SEL, DM, DF[1:0], DA[1:0], DB[1:0], DC[1:0], PLL_BP, DP[1:0], QA_CTRL1,
QA_CTRL2, QB_CTRL, QC_CTRL)
Input High Voltage
VIH
Input Low Voltage
VIL
2.0
Input High Current
IIH
VIN = VCC
Input Low Current
IIL
VIN = 0V
V
0.8
V
80
FA
-80
FA
LVCMOS/LVTTL CLOCK INPUT (CIN)
Reference Clock Input
Frequency
fREF
Input Amplitude Range
Internally AC-coupled (Note 4)
Input High Current
IIH
VIN = VCC
Input Low Current
IIL
VIN = 0V
Reference Clock Input Duty
Cycle
15
160
MHz
1.2
3.6
VP-P
80
FA
-80
FA
40
Input Capacitance
60
1.5
%
pF
DIFFERENTIAL CLOCK INPUT (DIN, DIN) (Note 5)
Differential Input Frequency
Input Bias Voltage
Input Differential Voltage Swing
fREF
15
VCMI
VCC 1.8
150
350
VCC 1.3
MHz
V
1800
mVP-P
2
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted. Signal applied to
CIN or DIN/DIN only when selected as the reference clock.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
Single-Ended Voltage Range
VCC 2.0
Input Differential Impedance
80
Differential Input Capacitance
TYP
100
MAX
UNITS
VCC 0.7
V
120
I
1.5
pF
LVDS OUTPUTS (QA[4:0], QA[4:0], QB[2:0], QB[2:0], QC, QC) (Note 6)
Output Frequency
800
Output High Voltage
VOH
Output Low Voltage
VOL
0.925
Differential Output Voltage
|VOD|
250
Change in Magnitude
of Differential Output for
Complementary States
Output Offset Voltage
Change in Magnitude of
Output Offset Voltage for
Complementary States
1.475
1.125
D|VOS|
Differential Output Impedance
78
100
400
mV
25
mV
1.3
V
25
mV
140
I
Short together
3
Short to ground
6
Output Current When Disabled
VQ__ = VQ__ = 0V to VCC
10
Output Rise/Fall Time
20% to 80%
160
240
50
52
Output Current
PLL enabled
Output Duty-Cycle Distortion
48
PLL bypassed (Note 7)
V
V
D|VOD|
VOS
MHz
mA
FA
50
ps
%
LVPECL OUTPUTS (QA[4:0], QA[4:0], QB[2:0], QB[2:0], QC, QC) (Note 8)
Output Frequency
800
MHz
Output High Voltage
VOH
VCC 1.13
VCC 0.98
VCC 0.83
V
Output Low Voltage
VOL
VCC 1.85
VCC 1.70
VCC 1.55
V
0.5
0.7
0.9
VP-P
Output-Voltage Swing
(Single-Ended)
Output Current When Disabled
VQ__ = VQ__ = 0V to VCC
10
Output Rise/Fall Time
20% to 80%
140
240
50
52.1
Output Duty-Cycle Distortion
PLL enabled
PLL bypassed (Note 7)
48
50
FA
ps
%
3
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted. Signal applied to
CIN or DIN/DIN only when selected as the reference clock.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
160
MHz
VCC
V
LVCMOS/LVTTL OUTPUT (QCC)
Output Frequency
Output High Voltage
IOH = -12mA
Output Low Voltage
IOL = 12mA
0.4
V
Output Rise/Fall Time
20% to 80% (Note 9)
150
400
850
ps
PLL enabled
42
50
58
Output Duty-Cycle Distortion
2.6
PLL bypassed (Note 7)
50
Output Impedance
15
%
I
PLL SPECIFICATIONS
VCO Frequency Range
fVCO
Phase-Frequency Detector
Compare Frequency
fPFD
Low VCO (DP1 = 0 or NC)
3600
3750
3830
High VCO (DP1 = 1)
3830
3932
4025
15
PLL Jitter Transfer Bandwidth
Integrated Phase Jitter
42
130
RJ
25MHz crystal
input (Note 9)
12kHz to 20MHz
0.34
1.875MHz to 20MHz
0.14
MHz
MHz
kHz
1.0
psRMS
25MHz LVCMOS or differential input
(Notes 10, 11)
0.34
Supply-Noise Induced Phase
Spur at LVPECL/LVDS Output
(Note 12)
-56
dBc
Supply-Noise Induced Phase
Spur at LVCMOS Output
(Note 12)
-45
dBc
Determinisitic Jitter Induced by
Power-Supply Noise
LVPECL or LVDS (Note 12)
6
psP-P
Nonharmonic and Subharmonic
Spurs
(Note 13)
-70
dBc
fOFFSET = 1kHz
-111
SSB Phase Noise at 491.52MHz
SSB Phase Noise at 312.5MHz
fOFFSET = 10kHz
-113
fOFFSET = 100kHz
-119
fOFFSET = 1MHz
-136
fOFFSET R 10MHz
-147
fOFFSET = 1kHz
-115
fOFFSET = 10kHz
-116
fOFFSET = 100kHz
-122
fOFFSET = 1MHz
-139
fOFFSET R 10MHz
-149
dBc/
Hz
dBc/
Hz
4
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.0V to 3.6V, TA = -40°C to +85°C. Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted. Signal applied to
CIN or DIN/DIN only when selected as the reference clock.) (Notes 1, 2)
PARAMETER
SSB Phase Noise at 245.76MHz
SSB Phase Noise at 156.25MHz
SSB Phase Noise at 125MHz
SSB Phase Noise at 100MHz
SYMBOL
CONDITIONS
MIN
TYP
fOFFSET = 1kHz
-117
fOFFSET = 10kHz
-119
fOFFSET = 100kHz
-125
fOFFSET = 1MHz
-142
fOFFSET R 10MHz
-151
fOFFSET = 1kHz
-122
fOFFSET = 10kHz
-123
fOFFSET = 100kHz
-129
fOFFSET = 1MHz
-145
fOFFSET R 10MHz
-152
fOFFSET = 1kHz
-123
fOFFSET = 10kHz
-124
fOFFSET = 100kHz
-130
fOFFSET = 1MHz
-147
fOFFSET R 10MHz
-153
fOFFSET = 1kHz
-126
fOFFSET = 10kHz
-127
fOFFSET = 100kHz
-133
fOFFSET = 1MHz
-148
fOFFSET R 10MHz
-152
MAX
UNITS
dBc/
Hz
dBc/
Hz
dBc/
Hz
dBc/
Hz
Note 1: A series resistor of up to 10.5I is allowed between VCC and VCCA for filtering supply noise when system power-supply
tolerance is VCC = 3.3V Q5%. See Figure 3.
Note 2: Unless otherwise noted, specifications at TA = +25NC and TA = +85NC are guaranteed by production testing.
Specifications at TA = -40NC are guaranteed by design.
Note 3: Measured with all outputs enabled and unloaded.
Note 4: CIN can be AC- or DC-coupled. See Figure 8. Input high voltage must be ≤ VCC + 0.3V.
Note 5: DIN can be AC- or DC-coupled. See Figure 10.
Note 6: Measured with 100I differential load.
Note 7: Measured with crystal input, or with 50% duty cycle LVCMOS or differential input.
Note 8: Measured with output termination of 50I to VCC - 2V or Thevenin equivalent.
Note 9: Measured with a series resistor of 33I to a load capacitance of 3.0pF. See Figure 1.
Note 10: Measured at 156.25MHz.
Note 11: Measured using LVCMOS/LVTTL input with slew rate R 1.0V/ns, or differential input with slew rate R 0.5V/ns.
Note 12: Measured at 156.25MHz output with 200kHz, 50mVP-P sinusoidal signal on the supply using the crystal input and
the power-supply filter shown in Figure 3. See the Typical Operating Characteristics for other supply noise frequencies. Deterministic jitter is calculated from the measured power-supply-induced spurs. For more information, refer to
Application Note 4461: HFAN-04.5.5: Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers.
Note 13: Measured with all outputs enabled and all three banks at different frequencies.
5
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
LVCMOS
33Ω
QCC
499Ω
OSCILLOSCOPE
0.1µF
Z = 50Ω
Z = 50Ω
3pF
50Ω
MAX3636
Figure 1. LVCMOS Output Measurement Setup
Typical Operating Characteristics
(VCC = 3.3V, TA = +25NC, unless otherwise noted.)
PLL NORMAL, ALL OUTPUTS UNLOADED
200
150
PLL NORMAL
350
300
250
200
150
PLL BYPASS
400
300
150
100
50
10
35
60
0
85
QA[2:0] ENABLED
200
50
-15
QA[4:3] AND QA[2:0] ENABLED
250
50
PLL BYPASS, ALL OUTPUTS UNLOADED
QA[4:3], QA[2:0], AND QB[2:0] ENABLED
350
100
-40
QA[4:3], QA[2:0], QB[2:0],
QC, AND QCC ENABLED
450
100
0
ALL OUTPUTS DISABLED
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY CURRENT vs. TEMPERATURE
(LVDS OUTPUTS)
DIFFERENTIAL OUTPUT AT 737.28MHz
(LVPECL)
DIFFERENTIAL OUTPUT AT 312.5MHz
(LVPECL)
MAX3636 toc05
350
QA[4:3], QA[2:0], QB[2:0],
QC, AND QCC ENABLED
300
SUPPLY CURRENT (mA)
500
SUPPLY CURRENT (mA)
PLL BYPASS, ALL OUTPUTS LOADED
250
400
SUPPLY CURRENT (mA)
350
300
450
250
QA[4:3], QA[2:0], AND QB[2:0] ENABLED
200
QA[4:3] AND QA[2:0] ENABLED
150
QA[2:0] ENABLED
100
MAX3636 toc06
MAX3636 toc04
SUPPLY CURRENT (mA)
400
SUPPLY CURRENT vs. TEMPERATURE
(LVPECL OUTPUTS, ALL LOADED)
MAX3636 toc02
PLL NORMAL, ALL OUTPUTS LOADED
450
500
MAX3636 toc01
500
SUPPLY CURRENT vs. TEMPERATURE
(LVDS OUTPUTS, ALL ENABLED)
MAX3636 toc03
SUPPLY CURRENT vs. TEMPERATURE
(LVPECL OUTPUTS, ALL ENABLED)
200mV/div
200mV/div
ALL OUTPUTS DISABLED
50
0
-40
-15
10
35
60
85
200ps/div
500ps/div
TEMPERATURE (°C)
6
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25NC, unless otherwise noted.)
DIFFERENTIAL OUTPUT AT 156.25MHz
(LVPECL)
DIFFERENTIAL OUTPUT AT 156.25MHz
(LVDS)
MAX3636 toc07
MAX3636 toc08
200mV/div
500mV/div
1ns/div
1ns/div
1ns/div
OUTPUT SWING
vs. OUTPUT FREQUENCY
OUTPUT SWING
vs. TEMPERATURE
RISE/FALL TIME vs. TEMPERATURE
(20% TO 80%)
LVDS
1000
LVCMOS
2000
LVPECL
1500
LVDS
1000
0
1000
0
-40
-15
OUTPUT FREQUENCY (MHz)
LVPECL/LVDS
50.2
50.0
49.8
49.6
LVCMOS
49.4
85
-40
MAX3636 toc14
-80
-90
-100
-110
-120
-130
-140
-90
-110
-120
-130
-140
-150
-160
35
60
85
85
-100
-160
10
60
-80
49.0
TEMPERATURE (°C)
35
PHASE JITTER = 0.28psRMS
INTEGRATED 12kHz TO 20MHz
-70
-150
-15
10
PHASE NOISE AT 491.52MHz
-60
49.2
-40
-15
TEMPERATURE (°C)
PHASE NOISE (dBc/Hz)
50.4
60
PHASE JITTER = 0.27psRMS
INTEGRATED 12kHz TO 20MHz
-70
PHASE NOISE (dBc/Hz)
50.6
35
PHASE NOISE AT 622.08MHz
-60
MAX3636 toc13
50.8
10
TEMPERATURE (°C)
DUTY-CYCLE DISTORTION vs. TEMPERATURE
51.0
MAX3636 toc12
LVPECL
0
100
10
LVDS
200
100
500
500
300
MAX3636 toc15
1500
2500
LVCMOS
400
RISE/FALL TIME (ps)
LVPECL
2000
3000
OUTPUT SWING (mVP-P)
LVCMOS
2500
500
MAX3636 toc11
3500
MAX3636 toc10
3000
OUTPUT SWING (mVP-P)
MAX3636 toc09
100mV/div
3500
DUTY-CYCLE DISTORTION (%)
QCC OUTPUT AT 125MHz
(LVCMOS)
1k
10k
100k
1M
10M
OUTPUT FREQUENCY (Hz)
100M
1k
10k
100k
1M
10M
100M
OUTPUT FREQUENCY (Hz)
7
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25NC, unless otherwise noted.)
MAX3636 toc16
PHASE JITTER = 0.32psRMS
INTEGRATED 12kHz TO 20MHz
-70
-90
-100
-110
-120
-130
PHASE JITTER = 0.28psRMS
INTEGRATED 12kHz TO 20MHz
-70
-80
PHASE NOISE (dBc/Hz)
-80
-140
-90
-100
-110
-120
-130
-140
-150
-150
-160
-160
10k
100k
1M
10M
100M
1k
OUTPUT FREQUENCY (Hz)
-90
-80
-100
-110
-120
-130
-140
100M
-90
-100
-110
-120
-130
-140
-150
-150
-160
-160
1k
10k
100k
1M
10M
100M
1k
OUTPUT FREQUENCY (Hz)
1M
10M
-90
-100
-110
-120
-130
-140
PHASE JITTER = 0.40psRMS
INTEGRATED 12kHz TO 20MHz
-70
-80
PHASE NOISE (dBc/Hz)
-80
100k
100M
PHASE NOISE AT 62.5MHz
-60
MAX3636 toc20
PHASE JITTER = 0.36psRMS
INTEGRATED 12kHz TO 20MHz
-70
10k
OUTPUT FREQUENCY (Hz)
PHASE NOISE AT 100MHz
-60
PHASE NOISE (dBc/Hz)
10M
PHASE JITTER = 0.36psRMS
INTEGRATED 12kHz TO 20MHz
-70
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
-80
1M
PHASE NOISE AT 125MHz
-60
MAX3636 toc18
PHASE JITTER = 0.34psRMS
INTEGRATED 12kHz TO 20MHz
-70
100k
OUTPUT FREQUENCY (Hz)
PHASE NOISE AT 156.25MHz
-60
10k
MAX3636 toc19
1k
MAX3636 toc21
PHASE NOISE (dBc/Hz)
PHASE NOISE AT 245.76MHz
-60
MAX3636 toc17
PHASE NOISE AT 312.5MHz
-60
-90
-100
-110
-120
-130
-140
-150
-150
-160
-160
1k
10k
100k
1M
10M
OUTPUT FREQUENCY (Hz)
100M
1k
10k
100k
1M
10M
100M
OUTPUT FREQUENCY (Hz)
8
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25NC, unless otherwise noted.)
INTEGRATED PHASE JITTER (12kHz TO 20MHz)
vs. TEMPERATURE
0
-5
JITTER TRANSFER (dB)
0.50
LVCMOS
0.40
0.35
0.30
LVPECL
0.25
-10
-15
-20
-25
-30
-35
-40
LVDS
-45
-50
0.20
-40
-15
10
35
60
1k
85
10k
100k
1M
10M
SPURS INDUCED BY POWER-SUPPLY NOISE
vs. NOISE FREQUENCY
DETERMINISTIC JITTER INDUCED BY POWER
SUPPLY NOISE vs. NOISE FREQUENCY
fC = 156.25MHz, NOISE = 50mVP-P
-20
LVCMOS
-30
-40
-50
-60
LVDS
-70
LVPECL
-80
40
fC = 156.25MHz, NOISE = 50mVP-P
35
DETERMINISTIC JITTER (psP-P)
0
30
LVCMOS
25
20
LVPECL
15
10
5
-90
LVDS
0
10
100
NOISE FREQUENCY (kHz)
1000
MAX3636 toc25
JITTER FREQUENCY (Hz)
MAX3636 toc24
TEMPERATURE (°C)
-10
SPUR AMPLITUDE (dBc)
MAX3636 toc23
OUTPUT FREQUENCY = 156.25MHz
0.55
0.45
JITTER TRANSFER
5
MAX3636 toc22
INTEGRATED PHASE JITTER (psRMS)
0.60
10
100
1000
NOISE FREQUENCY (kHz)
9
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
QA0
QA1
QA1
QA2
QA2
QA3
QA3
QA4
QA4
VCCQA
36
QA0
TOP VIEW
VCCQA
Pin Configuration
35
34
33
32
31
30
29
28
27
26
25
VCCQB
37
24
VCCQC
QB0
38
23
QC
QB0
39
22
QC
QB1
40
21
QCC
QB1
41
20
VCCQCC
QB2
42
19
QA_CTRL2
QB2
43
18
DC0
QA_CTRL1
44
17
DC1
QB_CTRL
45
16
DA0
DIN
46
15
DA1
14
DB0
13
DB1
8
9
10
11
12
DP1
DP0
7
VCCA
6
DF0
VCC
5
QC_CTRL
4
DF1
3
IN_SEL
2
PLL_BP
1
XIN
48
XOUT
47
CIN
*EP
+
DM
DIN
MAX3636
THIN QFN
(7mm × 7mm × 0.8mm)
*THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION.
Pin Description
PIN
NAME
1
DM
LVCMOS/LVTTL Input. Three-level control for input divider M. See Table 3.
FUNCTION
2
XIN
Crystal Oscillator Input
3
XOUT
4
VCC
Crystal Oscillator Output
Core Power Supply. Connect to 3.3V.
5
IN_SEL
LVCMOS/LVTTL Input. Three-level control for input mux. See Table 1.
6
PLL_BP
LVCMOS/LVTTL Input. Three-level control for PLL bypass mode. See Table 2.
7, 8
DF1, DF0
9
QC_CTRL
10
VCCA
LVCMOS/LVTTL Inputs. Three-level controls for feedback divider F. See Table 4.
LVCMOS/LVTTL Input. Three-level control input for C-bank output interface. See Table 10.
Power Supply for Internal Voltage-Controlled Oscillators (VCOs). See Figure 3.
11, 12
DP1, DP0
LVCMOS/LVTTL Inputs. Three-level controls for VCO select and prescale divider P. See Table 7.
13, 14
DB1, DB0
LVCMOS/LVTTL Inputs. Three-level controls for output divider B. See Table 5.
10
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Pin Description (continued)
PIN
NAME
FUNCTION
15, 16
DA1, DA0
LVCMOS/LVTTL Inputs. Three-level controls for output divider A. See Table 5.
17, 18
DC1, DC0
LVCMOS/LVTTL Inputs. Three-level controls for output divider C. See Table 6.
19
QA_CTRL2
LVCMOS/LVTTL Input. Three-level control for QA[4:3] output interface. See Table 8.
20
VCCQCC
21
QCC
22, 23
QC, QC
C-Bank Differential Output. Configured as LVPECL or LVDS with the QC_CTRL pin.
24
VCCQC
Power Supply for C-Bank Differential Output. Connect to 3.3V.
25, 36
VCCQA
Power Supply for A-Bank Differential Outputs. Connect to 3.3V.
Power Supply for QCC Output. Connect to 3.3V.
C-Bank LVCMOS Clock Output
26, 27
QA4, QA4
A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL2 pin.
28, 29
QA3, QA3
A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL2 pin.
30, 31
QA2, QA2
A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL1 pin.
32, 33
QA1, QA1
A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL1 pin.
34, 35
QA0, QA0
A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL1 pin.
37
VCCQB
38, 39
QB0, QB0
B-Bank Differential Output. Configured as LVPECL or LVDS with the QB_CTRL pin.
40, 41
QB1, QB1
B-Bank Differential Output. Configured as LVPECL or LVDS with the QB_CTRL pin.
42, 43
QB2, QB2
B-Bank Differential Output. Configured as LVPECL or LVDS with the QB_CTRL pin.
44
QA_CTRL1
LVCMOS/LVTTL Input. Three-level control for QA[2:0] output interface. See Table 8.
45
QB_CTRL
LVCMOS/LVTTL Input. Three-level control for B-bank output interface. See Table 9.
46, 47
DIN, DIN
Differential Clock Input. Operates up to 350MHz. This input can accept DC-coupled LVPECL signals, and is internally biased to accept AC-coupled LVDS, CML, and LVPECL signals.
48
CIN
LVCMOS Clock Input. Operates up to 160MHz.
—
EP
Exposed Pad. Connect to supply ground for proper electrical and thermal performance.
Power Supply for B-Bank Differential Outputs. Connect to 3.3V.
11
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Detailed Description
LVCMOS input, or differential input), PLL with on-chip
VCO, pin-programmable dividers and muxes, and three
banks of clock outputs. See Figure 2. The output banks
include nine pin-programmable LVDS/LVPECL output
buffers and one LVCMOS output buffer. The frequency,
The MAX3636 is a low-jitter clock generator designed to
operate over a wide range of frequencies. It consists of
a selectable reference clock (on-chip crystal oscillator,
IN_SEL
VCC
DM
DP[1:0]
VCCA
2
DA[1:0]
PLL_BP
VCCQA
QA_CTRL1
2
QA0
VCO
SELECT
XOUT
CRYSTAL
OSCILLATOR
1
0
XIN
fREF
LVCMOS
CIN
QA0
QA1
NC
÷M
PFD
VCO
CP
fVCO
÷P
÷A
fQA
QA1
QA2
0/NC
QA2
fPFD
15MHz TO 42MHz
3600MHz TO 3830MHz
OR
3830MHz TO 4025MHz
QA3
QA3
LVPECL
DIN
DIN
QA4
÷F
QA4
1
QA_CTRL2
VCCQB
QB_CTRL
QB0
MAX3636
QB0
QB1
1
÷B
fQB
QB1
QB2
0/NC
QB2
DIVIDER A: 1, 2, 4, 5, 6, 8, 10, 16, 25
DIVIDER B: 1, 2, 4, 5, 6, 8, 10, 16, 25
DIVIDER C: 2, 3, 4, 5, 6, 8, 10, 16, 25
DIVIDER F: 16, 20, 24, 25, 28, 30, 32, 40, 48
DIVIDER M: 1, 4, 5
DIVIDER P: 4, 5, 6, 7, 8, 9, 10
QC_CTRL
QC
1/NC
÷C
2
EP
DF[1:0]
2
DB[1:0]
fQC
QC
0
QCC
2
DC[1:0]
VCCQC
VCCQCC
Figure 2. Detailed Functional Diagram
12
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
enabling, and output interface of each output bank can
be individually programmed. In addition the A-bank is
split into two banks with programmable enabling and
output interface. A PLL bypass mode is also available for
system testing or clock distribution.
DC-coupled LVPECL signals, and is internally biased to
accept AC-coupled LVDS, CML, and LVPECL signals
(see the Applications Information section). No signal
should be applied to DIN if not used.
Crystal Oscillator
The PLL takes the signal from the crystal oscillator,
LVCMOS clock input, or differential clock input and synthesizes a low-jitter, high-frequency clock. The PLL contains a phase-frequency detector (PFD), a charge pump
(CP), and two low phase noise VCOs that combined
give a wide 3.60GHz to 4.025GHz frequency range.
The high-frequency VCO output is divided by prescale
divider P and then is connected to the PFD input through
a feedback divider F. The PFD compares the reference
frequency to the divided-down VCO output and generates a control signal that keeps the VCO locked to the
reference clock. The high-frequency VCO/P output clock
is sent to the output dividers. To minimize noise-induced
jitter, the VCO supply (VCCA) is isolated from the core
logic and output buffer supplies.
The on-chip crystal oscillator provides the low-frequency
reference clock for the PLL. This oscillator requires an
external crystal connected between XIN and XOUT. See
the Crystal Selection and Layout section for more information. The XIN and XOUT pins can be left open if not
used.
LVCMOS Clock Input
An LVCMOS-compatible clock source can be connected
to CIN to serve as the PLL reference clock. The input is
internally biased to allow AC- or DC-coupling (see the
Applications Information section). It is designed to operate from 15MHz to 160MHz. No signal should be applied
to CIN if not used.
Phase-Locked Loop (PLL)
Differential Clock Input
A differential clock source can be connected to DIN
to serve as the PLL reference clock. This input operates from 15MHz to 350MHz and contains an internal
100ω differential termination. This input can accept
Dividers and Muxes
The dividers and muxes are set with three-level control
inputs. Divider settings and routing information are given
in Table 1 to Table 7. See Table 11 for example divider
configurations used in various applications.
Table 1. PLL Input
IN_SEL
INPUT
0
Crystal Input. XO circuit is disabled when not selected.
1
Differential Input. No signal should be applied to DIN if not selected
NC
LVCMOS Input. No signal should be applied to CIN if not selected.
Table 2. PLL Bypass
PLL_BP
PLL OPERATION
0
PLL Enabled for Normal Operation. All outputs from the A, B, and C banks are derived from the VCO.
1
PLL Bypassed. Selected input passes directly to the outputs. Both VCOs are disabled to minimize power consumption and intermodulation spurs. Used for system testing or clock distribution.
NC
The outputs from A-bank and B-bank are derived from the VCO, but the C-bank outputs are directly driven from
the input signal for purposes of daisy chaining.
13
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Table 3. Input Divider M
Table 7. VCO Select and Prescale Divider P
DM
M DIVIDER RATIO
0
÷1
1
÷5
NC
÷4
DP1
Note: When the on-chip XO is selected (IN_SEL = 0), the setting DM = 0 is required.
DF0
F DIVIDER RATIO
0
0
÷25
0
1
÷20
1
0
÷16
1
1
÷32
1
NC
÷24
NC
1
÷30
0
NC
÷40
NC
0
÷48
NC
NC
÷28
DA0/DB0
÷5
720 to 766
÷6
600 to 638.33
÷9
400 to 425.50
0
÷7
547.14 to 575
1
÷10
383 to 402.50
÷8
1
NC
NC
NC
1
÷5
478.75 to 503.12
957.50 to
1006.25
766 to 805
NC
÷6
638.33 to 670.83
0
1
Low
(3600 to
3830)
High
(3830 to
4025)
÷4
Table 8. A-Bank Output Interface
QA_CTRL1
QA[2:0] OUTPUT
0
QA[2:0] = LVDS
1
QA[2:0] = LVPECL
NC
QA[2:0] disabled to high impedance
A, B DIVIDER RATIO
QA_CTRL2
QA[4:3] OUTPUT
0
QA[4:3] = LVDS
Table 5. Output Divider A, B
DA1/DB1
(VCO/P)
FREQUENCY
RANGE (MHz)
0
Table 4. PLL Feedback Divider F
DF1
P
DIVIDER
RATIO
DP0
0
VCO
FREQUENCY
RANGE
(MHz)
0
0
÷2
0
1
÷4
1
QA[4:3] = LVPECL
1
0
÷5
NC
QA[4:3] disabled to high impedance
1
1
÷6
1
NC
÷8
NC
1
÷10
0
NC
÷16
NC
0
÷25
NC
NC
÷1
Table 6. Output Divider C
DC1
DC0
C DIVIDER RATIO
0
0
÷2
0
1
÷3
1
0
÷4
1
1
÷5
÷6
1
NC
NC
1
÷8
0
NC
÷10
NC
0
÷16
NC
NC
÷25
Table 9. B-Bank Output Interface
QB_CTRL
QB[2:0] OUTPUT
0
QB[2:0] = LVDS
1
QB[2:0] = LVPECL
NC
QB[2:0] disabled to high impedance
Table 10. C-Bank Output Interface
QC_CTRL
QC AND QCC OUTPUT
0
QC = LVDS, QCC = LVCMOS
1
QC = LVPECL, QCC = LVCMOS
NC
QC and QCC disabled to high impedance
LVDS/LVPECL Clock Outputs
The differential clock outputs (QA[4:0], QB[2:0], QC)
operate up to 800MHz and have a pin-programmable
LVDS/LVPECL output interface. See Table 8 to Table 10.
14
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
When configured as LVDS, the buffers are designed
to drive transmission lines with a 100ω differential termination. When configured as LVPECL, the buffers are
designed to drive transmission lines terminated with 50ω
to VCC - 2V. Unused output banks can be disabled to high
impedance and unused outputs can be left open.
LVCMOS Clock Output
The LVCMOS clock output operates up to 160MHz and is
designed to drive a single-ended high-impedance load.
If unused, this output can be left open or the C-bank can
be disabled to high impedance.
3600MHz ≤ fVCO ≤ 3830MHz (when DP1 = 0) (5)
3830MHz ≤ fVCO ≤ 4025MHz (when DP1 = 1 or NC) (6)
The prescale divider P is set by pins DP1 and DP0 as
given in Table 7.
In addition, the reference clock frequency and input
divider M must also be selected so the PFD compare frequency (fPFD) falls within the specified range of 15MHz to
42MHz. If applicable, the higher fPFD should be selected
for optimal jitter performance.
f
f
fPFD = REF = VCO
M
P ×F
Internal Reset
During power-on, a power-on reset (POR) signal is generated to synchronize all dividers. A reset signal is also
generated if any control pin is changed. Outputs within a
bank are phase aligned, but outputs bank-to-bank may
not be phase aligned.
Applications Information
Output Frequency Configuration
(7)
15MHz ≤ fPFD ≤ 42MHz (8)
Note that the reference clock frequency is not limited by
the fPFD range when the PLL is in bypass mode.
Example Frequency Configuration
The following is an example of how to find divider ratios
for a valid PLL configuration, given a requirement of input
and output frequencies.
The MAX3636 output frequencies (fQA, fQB, fQC) are
functions of the reference frequency (fREF) and the pinprogrammable dividers (A, B, C, F, M). The relationships
can be expressed as:
f
F
fQA = REF ×
(1)
M
A
1) S
elect input and output frequencies for an Ethernet
application.
f
F
fQB = REF ×
M
B
(2)
f
F
fQC = REF ×
M
C
2) F
ind the input divider M for a valid PFD compare frequency. Using Table 3 and equations (7) and (8), it is
determined that M = ÷1 is the only valid option.
(3)
3) F
ind the feedback divider F and prescale divider P
for a valid fVCO. Using Table 4 and Table 7 along
with equations (4), (5), and (6), it is determined that
F = ÷25 and P = ÷6 results in fVCO = 3750MHz, which
is within the valid range of the low VCO.
The frequency ranges for the selected reference clocks
are 18MHz to 33.5MHz for the crystal oscillator input,
15MHz to 160MHz for the LVCMOS input, and 15MHz to
350MHz for the differential input. The available dividers
are given in Table 3 to Table 6.
For a given reference frequency fREF, the input divider
M, the PLL feedback divider F, and VCO prescale divider
P must be configured so the VCO frequency (fVCO) falls
within the specified ranges. Invalid PLL configuration
leads to VCO frequencies beyond the specified ranges
and can result in loss of lock. An expression for the VCO
frequency along with the specified ranges is given by:
f
fVCO = REF × F × P
M
fREF = 25MHz
fQA = 312.5MHz
fQB = 156.25MHz
fQC = 125MHz
4) F
ind the output dividers A, B, C for the required output
frequencies. Using Table 5 and Table 6 and equations
(1), (2), and (3), it is determined that A = ÷2 gives
fQA = 312.5MHz, B = ÷4 gives fQB = 156.25MHz, and
C = ÷5 gives fQC = 125MHz.
Table 11 provides input and output frequencies along
with valid divider ratios for a variety of applications.
(4)
15
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Table 11. Reference Frequencies and Divider Ratios for Various Applications
fREF
(MHz)
INPUT
DIVIDER
(M)
PLL
FEEDBACK
DIVIDER
(F)
19.44
1
32
38.88
1
16
VCO
FREQUENCY
(MHz)
3732.48
VCO
PRESCALE
DIVIDER
(P)
OUTPUT
DIVIDER
(A, B, C)
OUTPUT
FREQUENCY
(MHz)
6
1
622.08
6
2
311.04
6
4
155.52
6
8
77.76
155.52
4
16
6
16
38.88
25
1
25
6
1
625
31.25
1
20
6
2
312.5
62.5
4
40
6
4
156.25
125
5
25
6
5
125
156.25
5
20
6
10
62.5
26.04166
1
24
6
25
25
25
1
30
5
1
750
31.25
1
24
5
2
375
62.5
4
48
5
4
187.5
125
4
24
5
5
150
5
6
125
156.25
5
24
5
10
75
5
25
30
15.36
1
48
5
1
737.28
30.72
1
24
5
2
368.64
61.44
4
48
5
4
184.32
122.88
4
24
5
6
122.88
5
8
92.16
3750
3750
3686.4
15.36
1
40
6
1
614.4
19.2
1
32
6
2
307.2
30.72
1
20
6
4
153.6
38.4
1
16
6
5
122.88
102.4
3686.4
61.44
4
40
6
6
76.8
4
32
6
8
76.8
122.88
4
20
6
10
61.44
30.72
1
16
8
1
491.52
61.44
2
32
8
2
245.76
8
4
122.88
8
8
61.44
8
16
30.72
122.88
4
16
3932.16
APPLICATIONS
SONET/SDH, STM-N
Ethernet
Various
Wireless Base Station:
WCDMA, cdma2000®,
LTE, TD_SCDMA,
WiMAX™, GSM
cdma2000 is a registered trademark of the Telecommunications Industry Association.
WiMAX is a trademark of WiMAX Forum.
16
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Table 11. Reference Frequencies and Divider Ratios for Various Applications (continued)
fREF
(MHz)
INPUT
DIVIDER
(M)
PLL
FEEDBACK
DIVIDER
(F)
26
1
16
VCO
FREQUENCY
(MHz)
3744
52
26.5625
4
1
26.5625
1
33.3
1
133.33
4
166.67
5
25
1
100
4
125
5
33.3
1
133.33
4
166.67
5
25
1
100
4
125
5
31.25
1
125
4
156.25
5
15.625
1
62.5
4
78.125
24
16
4
33.3
1
133.33
4
166.67
5
1
3825
3825
24
4000
32
30
40
4000
32
32
5
66.67
32.76
32
4000
30
20
20
4000
3931.2
VCO
PRESCALE
DIVIDER
(P)
OUTPUT
DIVIDER
(A, B, C)
OUTPUT
FREQUENCY
(MHz)
9
1
416
9
4
104
9
8
52
9
16
26
6
2
318.75
6
4
159.375
6
6
106.25
9
2
212.5
9
4
106.25
9
8
53.125
5
2
400
5
4
200
5
6
133.333
5
8
100
5
16
50
4
2
500
4
4
250
4
5
200
4
6
166.67
4
8
125
4
10
100
4
25
40
8
2
250
8
4
125
8
5
100
8
8
62.5
8
10
50
8
25
20
6
2
333.33
6
4
166.67
6
5
133.33
6
8
83.33
6
10
66.67
6
5
131.04
6
10
65.52
APPLICATIONS
GSM
FC-SAN
Server, FB-DIMM,
Network Processor,
DDR/QDR Memory,
PCIe, SATA
Server, FB-DIMM,
Network Processor,
DDR/QDR Memory,
PCIe, SATA
Various
Microwave Radio Link
17
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Power-Supply Filtering
The MAX3636 is a mixed analog/digital IC. The PLL
contains analog circuitry susceptible to random noise.
To take full advantage of on-board filtering and noise
attenuation, in addition to excellent on-chip power-supply
rejection, this part provides a separate power-supply
pin, VCCA, for the VCO circuitry. Figure 3 illustrates the
recommended power-supply filter network for VCCA.
The purpose of this design technique is to ensure clean
input power supply to the VCO circuitry and to improve
the overall immunity to power-supply noise. This network
requires that the power supply is +3.3V ±5%. Decoupling
capacitors should be used on all other supply pins for
best performance. All supply connections should be
driven from the same source.
+3.3V ±5%
VCC
0.1µF
10.5Ω
MAX3636
VCCA
0.1µF
10µF
Figure 3. Power-Supply Filter
Table 12. Crystal Selection Parameters
PARAMETER
Ground Connection
The 48-pin TQFN package features an exposed pad
(EP), which provides a low resistance thermal path for
heat removal from the IC and also the electrical ground.
For proper operation, the EP must be connected to the
circuit board ground plane with multiple vias.
Crystal Selection and Layout
The IC features an integrated on-chip crystal oscillator to
minimize system implementation cost. The crystal oscillator is designed to drive a fundamental mode, AT-cut
crystal resonator. See Table 12 for recommended crystal
specifications. See Figure 4 for the crystal equivalent circuit and Figure 5 for the recommended external capacitor connections. The crystal, trace, and two external
capacitors should be placed on the board as close as
possible to the XIN and XOUT pins to reduce crosstalk of
active signals into the oscillator.
The total load capacitance for the crystal is a combination of external and on-chip capacitance. The layout
shown in Figure 6 gives approximately 1.7pF of trace
plus footprint capacitance per side of the crystal. Note
the ground plane is removed under the crystal to
minimize capacitance. There is approximately 2.5pF of
on-chip capacitance between XIN and XOUT. With an
external 27pF capacitor connected to XIN and a 33pF
capacitor connected to XOUT, the total load capacitance
for the crystal is approximately 18pF. The XIN and XOUT
pins can be left open if not used.
SYMBOL
MIN
fOSC
18
TYP
MAX
UNITS
25
33.5
MHz
Shunt Capacitance
C0
2.0
7.0
pF
Load Capacitance
CL
18
Equivalent Series Resistance (ESR)
RS
10
Crystal Oscillation Frequency
pF
Maximum Crystal Drive Level
XTAL
50
I
200
FW
27pF
XIN
CRYSTAL
(CL = 18pF)
C0
RS
LS
Figure 4. Crystal Equivalent Circuit
CS
MAX3636
XOUT
33pF
Figure 5. Crystal, Capacitor Connections
18
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Interfacing with LVCMOS Input
The equivalent LVCMOS input circuit for CIN is given in
Figure 7. This input is internally biased to allow AC- or
DC-coupling, and has 180kI input impedance. See
Figure 8 for the interface circuit. No signal should be
applied to CIN if not used.
Interfacing with Differential Input
The equivalent input circuit for DIN is given in Figure 9.
This input operates up to 350MHz and contains an
internal 100I differential termination as well as a 35I
common-mode termination. The common-mode termination ensures good signal integrity when connected to a
source with large common-mode signals. The input can
accept DC-coupled LVPECL signals, and is internally
biased to accept AC-coupled LVDS, CML, and LVPECL
signals (Figure 10). No signal should be applied to DIN
if not used.
Figure 6. Crystal Layout
1.4V
VCC
VBIAS
180kΩ
VCC
CIN
VCC
ESD
STRUCTURES
Figure 7. Equivalent CIN Circuit
ESD
STRUCTURES
DIN
50Ω
20kΩ
10Ω
DC-COUPLED
VCC
MAX3636
CIN
XO
VCC - 1.3V
16pF
50Ω
20kΩ
DIN
ESD
STRUCTURES
AC-COUPLED
MAX3636
0.1µF
XO
Figure 9. Equivalent DIN Circuit
CIN
Figure 8. Interface to CIN
19
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Interfacing with LVPECL Outputs
LVPECL SOURCE DRIVING MAX3636
DIFFERENTIAL INPUT DC-COUPLED
MAX3636
150Ω
+3.3V
+3.3V
DIN
Z = 50Ω
LVPECL
100Ω
LVPECL
DIN
Z = 50Ω
The equivalent LVPECL output circuit is given in
Figure 11. These outputs are designed to drive a
pair of 50ω transmission lines terminated with 50ω
to V TT = V CC - 2V. If a separate termination voltage
(VTT) is not available, other terminations methods can
be used, as shown in Figure 12. For more information
on LVPECL terminations and how to interface with other
logic families, refer to Application Note 291: HFAN-01.0:
Introduction to LVDS, PECL, and CML.
150Ω
VCC_ _
LVPECL SOURCE DRIVING MAX3636
DIFFERENTIAL INPUT AC-COUPLED
+3.3V
MAX3636
150Ω
0.1µF
Z = 50Ω
LVPECL
0.1µF
Z = 50Ω
Q_ _
+3.3V
DIN
100Ω
LVPECL
Q_ _
DIN
150Ω
ESD
STRUCTURES
LVDS OR CML SOURCE DRIVING MAX3636
DIFFERENTIAL INPUT AC-COUPLED
Figure 11. Equivalent LVPECL Output Circuit
MAX3636
VDD
0.1µF
Z = 50Ω
LVDS OR
CML
0.1µF
Z = 50Ω
+3.3V
DIN
100Ω
LVPECL
DIN
Figure 10. Interfacing to DIN
20
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
DC-COUPLED LVPECL DRIVING THEVENIN EQUIVALENT TERMINATION
3.3V
3.3V
3.3V
130Ω
MAX3636
Q_ _
3.3V
130Ω
HIGH IMPEDANCE
WITH/WITHOUT
DC BIAS
Z = 50Ω
LVPECL
LVPECL
Q_ _
Z = 50Ω
82Ω
82Ω
AC-COUPLED LVPECL DRIVING INTERNAL 100Ω DIFFERENTIAL TERMINATION
3.3V
VDD
150Ω
MAX3636
Q_ _
ON-CHIP
TERMINATION
WITH DC BIAS
0.1µF
Z = 50Ω
LVPECL
100Ω
0.1µF
Q_ _
LVPECL
Z = 50Ω
150Ω
AC-COUPLED LVPECL DRIVING EXTERNAL 50Ω WITH COMMON-MODE TERMINATION
3.3V
VDD
150Ω
MAX3636
Q_ _
0.1µF
HIGH IMPEDANCE
WITH
DC BIAS
Z = 50Ω
LVPECL
LVPECL
0.1µF
Q_ _
Z = 50Ω
150Ω
50Ω
50Ω
0.1µF
Figure 12. Interface to LVPECL Outputs
21
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
VREG
Interfacing with LVDS Outputs
VCC_ _
50Ω
Q_ _
50Ω
The equivalent LVDS output circuit is given in Figure 13.
These outputs provide 100ω differential output impedance designed to drive a 100ω differential transmission
line terminated with a 100ω differential load. Example
interface circuits are shown in Figure 14. For more information on LVDS terminations and how to interface with
other logic families, refer to Application Note 291: HFAN01.0: Introduction to LVDS, PECL, and CML.
Interfacing with LVCMOS Output
Q_ _
ESD
STRUCTURES
The equivalent LVCMOS output circuit is given in
Figure 15. This output provides 15ω output impedance
and is designed to drive a high-impedance load. A
series resistor of 33ω is recommended at the LVCMOS
output before the transmission line. An example interface circuit is shown in Figure 16.
Figure 13. Equivalent LVDS Output Circuit
VCCQCC
DC-COUPLED LVDS OUTPUT DRIVING LVDS INPUT
3.3V
MAX3636
+3.3V
10Ω
Q_ _
Z = 50Ω
LVDS
QCC
LVDS*
Q_ _
10Ω
Z = 50Ω
ESD
STRUCTURES
Figure 15. Equivalent LVCMOS Output Circuit
AC-COUPLED LVDS OUTPUT DRIVING LVDS INPUT
3.3V
MAX3636
VDD
Q_ _
LVDS
Q_ _
0.1µF
Z = 50Ω
LVCMOS
QCC
33Ω
Z = 50Ω
LVDS*
0.1µF
HIGH
IMPEDANCE
Z = 50Ω
MAX3636
Figure 16. Interface to LVCMOS Output
*100Ω DIFFERENTIAL INPUT IMPEDANCE ASSUMED.
Figure 14. Interface to LVDS Outputs
22
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Layout Considerations
• The crystal, trace, and two external capacitors should
be placed on the board as close as possible to the
XIN and XOUT pins to reduce crosstalk of active signals into the oscillator.
The inputs and outputs are the most critical paths for the
MAX3636; great care should be taken to minimize discontinuities on the transmission lines. Here are some suggestions for maximizing the performance of the IC:
• Maintain 100ω differential (or 50ω single-ended)
transmission line impedance into and out of the part.
• An uninterrupted ground plane should be positioned
beneath the clock outputs. The ground plane under the
crystal should be removed to minimize capacitance.
• Provide space between differential output pairs to
reduce crosstalk, especially if the outputs are operating at different frequencies.
• Supply decoupling capacitors should be placed close
to the supply pins, preferably on the same side of the
board as the IC.
• Use multilayer boards with an uninterrupted ground
plane to minimize EMI and crosstalk.
• Take care to isolate input traces from the IC outputs.
Refer to the MAX3636 Evaluation Kit for more information.
Typical Application Circuits
+3.3V
10.5Ω
10µF
0.1µF
0.1µF
VCCA
27pF
VCC
0.1µF
VCCQA
VCCQB
XIN
0.1µF
VCCQC
0.1µF
0.1µF
VCCQCC
150Ω
312.5MHz
LVPECL
Z = 50Ω
QA[4:0]
0.1µF
25MHz
XOUT
NC
CIN
NC
DIN
NC
DIN
100Ω
0.1µF
Z = 50Ω
QA[4:0]
33pF
ASIC WITH LVPECL
TERMINATION
150Ω
156.25MHz
LVDS
Z = 50Ω
IN_SEL
MAX3636
PLL_BP
QB[2:0]
ASIC WITH LVDS
TERMINATION
100Ω
DM
DF1
QB[2:0]
Z = 50Ω
QC
125MHz
LVDS
Z = 50Ω
DF0
DA1
+3.3V
DA0
DB1
ASIC WITH LVDS
TERMINATION
100Ω
DB0
DC1
Z = 50Ω
QC
DC0
DP1
DP0
33Ω
QA_CTRL1
QCC
QA_CTRL2
125MHz
LVCMOS
Z = 50Ω
ASIC WITH LVCMOS
TERMINATION
HIGH
IMPEDANCE
QB_CTRL
QC_CTRL
EP
23
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Typical Application Circuits (continued)
CLOCK GENERATOR FOR ETHERNET
XIN
QA[4:0]
312.5MHz
LVPECL OR LVDS
BACKPLANE
TRANSCEIVER
QB[2:0]
156.25MHz
LVPECL OR LVDS
10GbE PHY
QC
125MHz
LVPECL OR LVDS
1GbE PHY
QCC
125MHz
LVCMOS
ASIC
25MHz
XOUT
MAX3636
FREQUENCY SYNTHESIZER FOR SONET LINE CARD
19.44MHz
QA[4:0]
622.08MHz
LVPECL OR LVDS
OC-192 PHY
QB[2:0]
155.52MHz
LVPECL OR LVDS
OC-48 PHY
QC
155.52MHz
LVPECL OR LVDS
ASIC
QCC
38.88MHz
LVCMOS
ASIC
DIN
MAX3636
CLOCK GENERATOR FOR SYSTEM CLOCKING
XIN
QA[4:0]
100MHz
LVPECL OR LVDS
PCIe
QB[2:0]
133.33MHz
LVPECL OR LVDS
DDR/QDR
MEMORY
QC
200MHz
LVPECL OR LVDS
NETWORK
PROCESSOR
QCC
100MHz
LVCMOS
ASIC
25MHz
XOUT
MAX3636
24
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Typical Application Circuits (continued)
CLOCK GENERATOR FOR FIBRE CHANNEL
XIN
QA[4:0]
212.5MHz
LVPECL OR LVDS
8G PHY
QB[2:0]
106.25MHz
LVPECL OR LVDS
4G PHY
QC
106.25MHz
LVPECL OR LVDS
ASIC
26.5625MHz
XOUT
MAX3636
QCC
NC
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX3636ETM+
-40NC to +85NC
48 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to http://www.microsemi.com . Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
48 TQFN-EP
T4877+4
21-0144
90-0130
25
MAX3636
Low-Jitter, Wide Frequency Range,
Programmable Clock Generator with 10 Outputs
Revision History
REVISION
NUMBER
REVISION
DATE
0
9/11
DESCRIPTION
Initial release
PAGES
CHANGED
—
26
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