ZL38004QCG1

ZL38004 Dedicated Voice Processor with Dual Channel Codec Data Sheet A full Design Manual is available to qualified customers. To register, please send an email to November 2012 Ordering Information VoiceProcessing@Zarlink.com. Features • 100 MHz (200 MIPs) Microsemi voice processor with Butterfly hardware accelerator and breakpoint/interrupt controller • On-board Data (26 Kbytes), Instruction (24 Kbytes RAM and Boot (3 Kbytes) ROM • Dual  ADCs with input buffer gain selection programmable to either 8 or 16 kHz sampling • ZL38004QCG1 100 Pin LQFP ZL38004GGG2 96 Pin VFBGA* Trays, Bake & Drypack Trays, Bake & Drypack *Pb Free Matte Tin -40C to +85C • Watchdog and 2 auxiliary timers • 11 General Purpose Input/Output (GPIO) pins • General purpose UART port Dual DACs with output sampling of 8, 16, 44.1 and 48 kHz and internal output driver • Bootloadable for future Microsemi software upgrades • 2048 tap Filter co-processor shared across up to 16 separate functions in 128 tap increments • External oscillator or crystal/ceramic resonator Dual function Inter-IC Sound (I2S) or Secondary TDM port • 1.2 V Core; 3.3 V IO with 5 V-tolerant inputs • • IEEE-1149.1 compatible JTAG port • Primary PCM port supports TDM (ST BUS, GCI or McBSP framing) or SSI modes at bit rates of 128, 256, 512, 1024, 2048, 4096, 8192 or 16384 Kb/sec Applications • Hands-free car kits Separate slave (microcontroller) and master (Flash) SPI ports, maximum clock rate = 25 MHz • Full duplex speaker-phone for digital telephone • Buffer CODEC[0] IRQ[15:0] DAC IRQ ButterFly Hardware Accelerator IRQ IRQ 27K Bytes I2 S IRQ PCM P1 IRQ Filter Co-processor APLL MCLK Watchdog AUX Timer1 AUX Timer2 IRQ CODEC[1:0] Device Clocks Master SPI 5 / IRQ Slave SPI 4 / IRQ IRQ Figure 1 - Functional Block Diagram 1 Copyright 2012, Microsemi Corporation. All Rights Reserved. 5 / IRQ PCM P0 IRQ 5 / Timing Generator JTAG Data RAM DAC 5 / Boot ROM 3K Bytes ADC IRQ PCM_LBCi PCM P0 Clock Chain CODEC[1] Driver OSC OSCi PCM_CLKi 24K Bytes DSP Core OSCo APLL Instruction RAM Interrupt Controller ADC Driver Buffer 100 MHz MCLK IRQ UART 2 / GPIO 11 / ZL38004 • Echo cancellation for video conferences • Intercom Systems • Security Systems Data Sheet Change Summary Changes from August 2011 issue to November 2012 issue. Page, section, figure and table numbers refer to this current issue. Page Item Change Multiple Zarlink logo and name reference Updated to Microsemi logo and name. Changes from March 2006 issue to August 2011 issue. Page, section, figure and table numbers refer to this current issue. Page Item Change 1 Ordering Information Added VFBGA package. 7 Package Drawing Updated 96L VFBGA package drawing. 1.0 Functional Description The ZL38004 is a hardware platform designed to support advanced acoustic echo canceller (with noise reduction) firmware applications available from Microsemi. These applications are resident in external memory and are downloaded by the ZL38004 resident boot code during initialization. The firmware products and manuals available at the release of this data sheet are: ZLS38500: Acoustic Echo Canceller with Noise Reduction for Hands-Free Car Kits; ZLS38501 Speakerphone. If these applications do not meet your requirements, please contract your local Microsemi CMPG Sales Office for the latest firmware releases. The ZL38004 Advanced Acoustic Echo Canceller with Noise Reduction platform integrates Microsemi’s Voice Processor (ZVP) DSP Core with a number of internal peripherals. These peripherals include the following: • Two independent  CODECs • Two PCM ports - ST BUS, GCI, McBSP or SSI operation • An I2S interface port • A 2048 tap Filter Co-processor • Two Auxiliary Timers and a Watchdog Timer • 11 GPIO pins • A UART interface • A Slave SPI port and a Master SPI port • A timing block that supports master and slave operation • An IEEE - 1149.1 compatible JTAG port The DSP Core can process up to four 8-bit audio channels, two 16-bit audio channels or two 8-bit and one 16-bit audio channel. These audio channels may originate and terminate with the  CODECs, or be communicated to and from the DSP Core through the PCM ports or the I2S port. 2 Microsemi Corporation ZL38004 2.0 Data Sheet Core DSP Functional Block The ZL38004 DSP Core functional block, illustrated in Figure 1, is made up of a DSP Core, Interrupt Controller, Data RAM, Instruction RAM, BOOT ROM and a ButterFly Hardware Accelerator. This block controls the timing (APLL and Timing Generator), peripheral interfaces and Filter Co-processor through a peripheral address/data/control bus and 16 prioritized interrupts. The ZL38004 implementation of DSP core and Filter Co-processor have been optimized to efficiently support voice processing applications. These applications are described in detail in the firmware manuals associated with this hardware platform. When an interrupt occurs the DSP core saves its current status and jumps to the address of the associated interrupt service routine. 3.0 Codec[1:0] The ZL38004 has two 16-bit fully differential  CODECs (CODEC 0/1) that can be programmed for 48 kHz or 44.1 kHz sampling, or to meet G.712 requirements at 8 kHz sampling or G.722 at 16 kHz sampling, see Figure 2. The ADC path consists of input signal pins C0/1_ADCi+ and C0/1_ADCi- (buffer output pins C0/1_BF0+ and C0/1_BFo-), which feed selectable Microphone Amplifier or Line Amplifier options. Once past the buffer the analog signal goes through a low pass antialiasing filter and to a 4th order feed-forward  Modulator that produces a Pulse Density Modulated (PDM) signal. Next the PDM signal goes through a Low Pass Decimation Filter and then is converted into a 16-bit parallel word that can be read by the ZL38004 DSP (ADCout[15:0], Figures 2). The ZL38004 DSP will send 16-bit parallel word samples (DACin[15:0], Figure 2) to the DAC where they are converted to serial data and passed through an interpolation filter followed by a digital  Modulator. The  Modulator generates PDM data, which then passes through a 32-tap FIR reconstruction filter. The reconstructed analog signal is then passed to a unity voltage gain differential output driver and to pins C0/1_DACo+ and C0/1_DACo-. The CODEC bias voltages are generated by an internal bandgap circuit (BIAS_VCM, BIAS_RF+ and BIAS_RF-). Each ZL38004 CODEC has two loopbacks. When activated, the input analog signal on pins C0/1_ADC+/- is looped around to C0/1_DAC+/-. Pulse Density Modulated (PDM) serial data from the ADC Analog  Modulator output is looped around to the input of the DAC Reconstruction Filter. At the same time 16-bit parallel data is looped around from DACin[15:0] to ADCout[15:0]. PDM serial data from the DAC Digital  Modulator is looped around to the input of the ADC Digital Low Pass Decimation Filter. When the Parallel Loopback is activated the input analog signal on pins C0/1_ADC+/- is looped around to the C0/1_DAC+/- output. 16-bit parallel data from the ADC Digital Low Pass Decimation Filter is looped around to the DAC Digital Low Pass Interpolation Filter. This data may be read by the DSP, but parallel data written to the DAC by the DSP will be lost. CODEC0 and CODCE1 of the ZL38004 may be powered down if they are not required. See firmware manual. 3 Microsemi Corporation ZL38004 Data Sheet ZL38004 Analog Clock Select 3.0720 MHz 2.8224 MHz Analog Clock Buffer C0/1_BFo+ C0/1_ADCiC0/1_ADCi+ C0/1_BFo- Antialiasing Filter BIAS_VCM BIAS_RF+ BIAS_RF- Bias Generation C0/1_DACo+ C0/1_DACo- Digital LP Decimation Filter Analog  Modulator CODEC PDM Loopback Digital  Modulator Reconstruction Filter & Driver CODEC PDM Loopback Digital LP Interpolation Filter Analog Clock 16 ADCout [15:0] 16 16 DACin [15:0] CODEC Parallel Loopback Figure 2 - CODEC Block Diagram 4.0 PCM / I2S Ports The PCM ports 0 and 1 support data communication between an external peripheral device and the ZL38004 DSP Core using separate input (P0/1PCMi) and output (P0/1PCMo) serial streams with TDM (i.e., ST-BUS, GCI or McBSP) or SSI interface timing in both master or slave timing modes. Both PCM Ports 0 and 1 support the same functionality and modes of operation. PCM Port 1 pin functions are shared with the I2S Port pin functions. The I2S (Inter-IC Sound) port and PCM Port One share the same physical pins of the ZL38004. Selection of either I2S port operation or PCM Port One operation is done through the Port One PCM/I2S Select Register. See firmware manual. The I2S port can be used to connect external Analog-to-Digital Converters or CODECs to the internal DSP. This port can operate in master mode, where the ZL38004 is the source of the port clocks, or slave mode, where the bit and sampling clocks (I2S_SCK and I2S_ LRCK) are inputs to the ZL38004. In I2S port master mode the clock signal at output pin I2S_LRCK is the sampling frequency (fS), the clock signal at output I2S_SCK is 32 x fS, and the clock signal at output I2S_MCLK is 256 x fS. In I2S port slave mode the relationship between the clock signal at input pin I2S_LRCK and the clock signal at input I2S_SCK must be 32 x fS. In slave mode the 256 x fS relationship between fS and the I2S_MCLK is not mandatory, and the I2S_MCLK output pin will be in a high impedance state. Access to the control and status registers associated with these ports is through the Slave SPI port or UART. 4 Microsemi Corporation ZL38004 5.0 Data Sheet Host Microprocessor and Peripheral Interfaces The ZL38004 provides 1 master SPI port (with 2 chip selects), 1 slave SPI ports and an UART. The master SPI port’s primary function is to access and external FLASH memory to download firmware to the ZL38004. The control/status registers and memory of the ZL38004 can be accessed (R/W) by an external host through the Slave SPI and the UART ports. Register/Memory read and write accesses are carried out through a series of port read and write accesses as follows: 5.1 Master SPI (FLASH Port) The Master SPI port is used by the ZL38004 to access one or two peripheral devices (chip select signals SPIM_CS[1:0]). It supports both SPI and MICROWIRE modes of operation and can write up to 40 bits or read up to 32 bits in a single access. The Chip Select output signals may be programmed for a single access or burst access. All communication is MSB first and all pins of the master SPI port are outputs controlled by the ZL38004, except SPIM_MISO. 5.2 Slave SPI (Host Port) The slave SPI port may be used by an external host microprocessor to access (Read/Write) the ZL38004 internal control/status registers and memory. Access is initiated when the external host makes signal SPIS_CS low and is ended when this signal goes high. The host will then apply a clock (maximum 25 MHz) to signal SPIS_CLK to clock data out of SPIS_MISO and in on SPIS_MOSI. 5.3 UART The UART (Universal Asynchronous Receiver Transmitter) port may be used by an external host microprocessor to access (Read/Write) the ZL38004 internal control/status registers and memory. The ZL38004 DSP will set up the initial parameters of this port (i.e., master/slave, baud rate, stop bits, parity bit...) during the Boot process. After the device has been booted these port options can be changed as per the firmware manual. The UART port will support 8-bit data only with any combination of 1 start bit, 0 or 1 parity bit(s) and 1, 1.5 or 2 stop bit(s). The ZL38004 has 11 GPIO (General Purpose Input/Output) pins that can be individually configured as either input or output. These pins are intended for low frequency signalling. When a GPIO pin is defined as an input the state of that input pin is sampled with the internal master clock (Mclk = 100 MHz) and latched into the GPIO Read Register. This sampling can be stopped (Freeze) on an individual GPIO pin. Individual pins of GPIO[4:0] may have an internal pull-down resistor activated/deactivated and individual pins of GPIO[10:5] may have an internal pull-up activated/deactivated. Immediately after a power-on reset (RST pin) the GPIO pins are defined as inputs and their state is captured in the GPIO Start-Up Status Register. The state of this register is used by the Boot program to determine the base functionality and programming options of the device. Individual GPIO pins may also be defined as outputs with associated enable/disable (active/high impedance) control. 5 Microsemi Corporation ZL38004 Mechanical Drawings Microsemi Corporation, 2002. All rights reserved. 6 Microsemi Corporation Data Sheet ZL38004 Data Sheet Microsemi 7 Microsemi Corporation ZL38004 8 Microsemi Corporation Data Sheet Information relating to products and services furnished herein by Microsemi Corporation or its subsidiaries (collectively “Microsemi”) is believed to be reliable. However, Microsemi assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Microsemi or licensed from third parties by Microsemi, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Microsemi, or non-Microsemi furnished goods or services may infringe patents or other intellectual property rights owned by Microsemi. This publication is issued to provide information only and (unless agreed by Microsemi in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Microsemi without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical and other products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Microsemi’s conditions of sale which are available on request. For more information about all Microsemi products visit our website at www.microsemi.com TECHNICAL DOCUMENTATION – NOT FOR RESALE Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 © 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.