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BD809G

BD809G

  • 厂商:

    MURATA-PS(村田)

  • 封装:

    TO-220-3

  • 描述:

    晶体管类型:NPN;集射极击穿电压(Vceo):80V;集电极电流(Ic):10A;功率(Pd):90W;直流电流增益(hFE@Ic,Vce):15@4A,2V;

  • 数据手册
  • 价格&库存
BD809G 数据手册
BD809(NPN), BD810(PNP) Plastic High Power Silicon Transistors These devices are designed for use in high power audio amplifiers utilizing complementary or quasi complementary circuits. Features www.onsemi.com 10 AMPERE POWER TRANSISTORS 80 VOLTS 90 WATTS • High DC Current Gain • These Devices are Pb−Free and are RoHS Compliant* MAXIMUM RATINGS Rating Symbol Value Unit Collector−Emitter Voltage VCEO 80 Vdc Collector−Base Voltage VCBO 80 Vdc Emitter−Base Voltage VEBO 5.0 Vdc Collector Current IC 10 Adc Base Current IB 6.0 Adc Total Device Dissipation @ TC = 25°C Derate above 25°C PD 90 0.72 W W/°C −55 to +150 °C Operating and Storage Junction Temperature Range TJ, Tstg PNP NPN COLLECTOR 2, 4 COLLECTOR 2, 4 1 BASE 1 BASE EMITTER 3 4 TO−220 CASE 221A STYLE 1 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1 2 THERMAL CHARACTERISTICS Characteristics Thermal Resistance, Junction−to−Case Symbol Max Unit RqJC 1.39 °C/W EMITTER 3 3 MARKING DIAGRAM BD8xxG AY WW BD8xx = A Y WW G = = = = Device Code x = 09 or 10 Assembly Location Year Work Week Pb−Free Package ORDERING INFORMATION Device *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2014 November, 2014 − Rev. 8 1 Package Shipping BD809G TO−220 (Pb−Free) 50 Units/Rail BD810G TO−220 (Pb−Free) 50 Units/Rail Publication Order Number: BD809/D BD809 (NPN), BD810 (PNP) ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Symbol Characteristic Collector−Emitter Sustaining Voltage (Note 1) (IC = 0.1 Adc, IB = 0) Min Max 80 − − 1.0 − 2.0 30 15 − − − 1.1 − 1.6 1.5 − Unit BVCEO Collector Cutoff Current (VCB = 80 Vdc, IE = 0) ICBO Emitter Cutoff Current (VBE = 5.0 Vdc, IC = 0) IEBO DC Current Gain (IC = 2.0 A, VCE = 2.0 V) (IC = 4.0 A, VCE = 2.0 V) hFE Collector−Emitter Saturation Voltage (Note 1) (IC = 3.0 Adc, IB = 0.3 Adc) VCE(sat) Base−Emitter On Voltage (Note 1) (IC = 4.0 Adc, VCE = 2.0 Vdc) VBE(on) Current−Gain Bandwidth Product (IC = 1.0 Adc, VCE = 10 Vdc, f = 1.0 MHz) Vdc mAdc mAdc − Vdc Vdc fT MHz Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2.0%. 3 .5 ms 1 ms 1 ms 5 ms 10 PD, POWER DISSIPATION (WATTS) IC, COLLECTOR CURRENT (AMP) 90 dc 1 0.3 0.1 1 3 10 30 VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) 80 70 60 50 40 30 20 10 0 100 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (°C) Figure 1. Active Region DC Safe Operating Area Figure 2. Power−Temperature Derating Curve (see Note on page 3) BD809 (NPN) BD810 (PNP) 500 500 TJ = 150°C 100 -55°C 50 20 VCE = 2.0 V 10 5.0 0.2 0.5 1.0 2.0 5.0 IC, COLLECTOR CURRENT (AMP) TJ = 150°C 200 25°C hFE, DC CURRENT GAIN hFE, DC CURRENT GAIN 200 25°C 100 -55°C 50 20 10 10 5.0 20 VCE = 2.0 V 0.2 Figure 3. DC Current Gain www.onsemi.com 2 0.5 1.0 2.0 5.0 IC, COLLECTOR CURRENT (AMP) 10 20 VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS) VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS) BD809 (NPN), BD810 (PNP) 2.0 TJ = 25°C 1.8 1.6 1.4 1.2 1.0 IC = 1.0 A 0.8 4.0 A 8.0 A 0.6 0.4 0.2 0 5.0 10 20 50 100 200 500 1000 IB, BASE CURRENT (mA) 2000 5000 2.0 TJ = 25°C 1.8 1.6 1.4 1.2 IC = 1.0 A 1.0 4.0 A 8.0 A 0.8 0.6 0.4 0.2 0 5.0 20 10 50 100 200 500 1000 IB, BASE CURRENT (mA) 2000 5000 Figure 4. Collector Saturation Region 2.8 2.8 V, VOLTAGE (VOLTS) V, VOLTAGE (VOLTS) 2.0 1.6 1.2 VBE(sat) = IC/IB = 10 0.8 2.0 1.6 1.2 VBE(sat) @ IC/IB = 10 0.8 VBE @ VCE = 2.0 V 0.4 TJ = 25°C 2.4 TJ = 25°C 2.4 VBE @ VCE = 2.0 V 0.4 VCE(sat) @ IC/IB = 10 0 VCE(sat) @ IC/IB = 10 0 0.2 0.5 1.0 2.0 5.0 10 0.2 20 0.5 IC, COLLECTOR CURRENT (AMP) 1.0 2.0 5.0 10 20 IC, COLLECTOR CURRENT (AMP) r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE Figure 5. “On” Voltages 1.0 0.7 0.5 D = 0.5 0.2 0.3 0.2 0.1 0.07 0.05 0.1 qJC(t) = r(t) qJC 0.02 0.03 0.02 0.01 0.01 SINGLE P(pk) PULSE 0.05 D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) qJC(t) SINGLE PULSE 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 t, PULSE WIDTH (ms) 20 30 50 t1 t2 DUTY CYCLE, D = t1/t2 100 200 300 500 1000 Figure 6. Thermal Response Note: The data of Figure 1 is based on TJ(pk) = 150°C; TC is variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided TJ(pk) ≤ 150°C. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC − VCE limits of the transistor that must be observed for reliable operation, i.e., the transistor must not be subjected to greater dissipation than the curves indicate. www.onsemi.com 3 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AJ DATE 05 NOV 2019 SCALE 1:1 STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. BASE EMITTER COLLECTOR EMITTER STYLE 3: PIN 1. 2. 3. 4. CATHODE ANODE GATE ANODE STYLE 4: PIN 1. 2. 3. 4. MAIN TERMINAL 1 MAIN TERMINAL 2 GATE MAIN TERMINAL 2 STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 6: PIN 1. 2. 3. 4. ANODE CATHODE ANODE CATHODE STYLE 7: PIN 1. 2. 3. 4. CATHODE ANODE CATHODE ANODE STYLE 8: PIN 1. 2. 3. 4. CATHODE ANODE EXTERNAL TRIP/DELAY ANODE STYLE 9: PIN 1. 2. 3. 4. GATE COLLECTOR EMITTER COLLECTOR STYLE 10: PIN 1. 2. 3. 4. GATE SOURCE DRAIN SOURCE STYLE 11: PIN 1. 2. 3. 4. DRAIN SOURCE GATE SOURCE STYLE 12: PIN 1. 2. 3. 4. MAIN TERMINAL 1 MAIN TERMINAL 2 GATE NOT CONNECTED DOCUMENT NUMBER: DESCRIPTION: 98ASB42148B TO−220 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 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