CAV93C56YE-GT3

CAV93C56 EEPROM Serial 2-Kb Microwire - Automotive Grade 1 Description The CAV93C56 is an EEPROM Serial 2−Kb Microwire Automotive Grade 1 device, which is organized as either 128 registers of 16 bits (ORG pin at VCC) or 256 registers of 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAV93C56 features sequential read and self−timed internal write with auto−clear. On−chip Power−On Reset circuitry protects the internal logic against powering up in the wrong state. www.onsemi.com SOIC−8 V SUFFIX CASE 751BD TSSOP−8 Y SUFFIX CASE 948AL Features • • • • • • • • • • • • Automotive AEC−Q100 Grade 1 (−40°C to +125°C) Qualified High Speed Operation: 2 MHz 2.5 V to 5.5 V Supply Voltage Range Selectable x8 or x16 Memory Organization Sequential Read Software Write Protection Power−up Inadvertant Write Protection Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention 8−pin SOIC and TSSOP Packages These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant VCC ORG CS SK CAV93C56 DO PIN CONFIGURATIONS CS SK DI DO 1 VCC NC ORG GND SOIC (V), TSSOP (Y) (Top View) PIN FUNCTION Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output VCC Power Supply GND Ground ORG Memory Organization NC No Connection DI GND ORDERING INFORMATION Figure 1. Functional Symbol See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. NOTE: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization. © Semiconductor Components Industries, LLC, 2013 April, 2019 − Rev. 2 1 Publication Order Number: CAV93C56/D CAV93C56 Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature −65 to +150 °C Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter NEND (Note 3) TDR Endurance Min Units 1,000,000 Program / Erase Cycles 100 Years Data Retention 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Block Mode, VCC = 5 V, 25°C Table 3. D.C. OPERATING CHARACTERISTICS (VCC = +2.5 V to +5.5 V, TA=−40°C to +125°C unless otherwise specified.) Parameter Symbol Test Conditions Min Max Units ICC1 Power Supply Current (Write) VCC = 5.0 V 2 mA ICC2 Power Supply Current (Read) fSK = 2 MHz, VCC = 5.0 V, DO open 500 mA ISB1 Power Supply Current (Standby) (x8 Mode) VIN = GND or VCC, CS = GND ORG = GND 5 mA ISB2 Power Supply Current (Standby) (x16 Mode) VIN = GND or VCC, CS = GND ORG = Float or VCC 3 mA VIN = GND to VCC 2 mA ILI Input Leakage Current ILO Output Leakage Current 2 mA VIL1 Input Low Voltage VOUT = GND to VCC, CS = GND 4.5 V v VCC < 5.5 V −0.1 0.8 V VIH1 Input High Voltage 4.5 V v VCC < 5.5 V 2 VCC + 1 V VIL2 Input Low Voltage 2.5 V v VCC < 4.5 V 0 VCC x 0.2 V VIH2 Input High Voltage 2.5 V v VCC < 4.5 V VCC x 0.7 VCC + 1 V VOL1 Output Low Voltage 4.5 V v VCC < 5.5 V, IOL = 3 mA 0.4 V VOH1 Output High Voltage 4.5 V v VCC < 5.5 V, IOH = −400 mA VOL2 Output Low Voltage 2.5 V v VCC < 4.5 V, IOL = 1 mA VOH2 Output High Voltage 2.5 V v VCC < 4.5 V, IOH = −100 mA 2.4 V 0.2 VCC − 0.2 V V Table 4. PIN CAPACITANCE (TA = 25°C, f = 1 MHz, VCC = 5 V) Symbol COUT (Note 4) CIN (Note 4) Test Conditions Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG) Min Typ Max Units VOUT = 0 V 5 pF VIN = 0 V 5 pF 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. www.onsemi.com 2 CAV93C56 Table 5. A.C. CHARACTERISTICS (Note 5) (VCC = +2.5V to +5.5V, TA = −40°C to +125°C, unless otherwise specified.) Limits Symbol Min Parameter tCSS CS Setup Time tCSH tDIS Max Units 50 ns CS Hold Time 0 ns DI Setup Time 100 ns tDIH DI Hold Time 100 ns tPD1 Output Delay to 1 0.25 ms tPD0 Output Delay to 0 0.25 ms Output Delay to High−Z 100 ns 5 ms tHZ (Note 6) tEW Program/Erase Pulse Width tCSMIN Minimum CS Low Time 0.25 ms tSKHI Minimum SK High Time 0.25 ms tSKLOW Minimum SK Low Time 0.25 ms tSV Output Delay to Status Valid SKMAX Maximum Clock Frequency DC 0.25 ms 2000 kHz Table 6. A.C. TEST CONDITIONS Input Rise and Fall Times ≤ 50 ns Input Pulse Voltages 0.4 V to 2.4 V 4.5 V v VCC v 5.5 V Timing Reference Voltages 0.8 V, 2.0 V 4.5 V v VCC v 5.5 V Input Pulse Voltages 0.2 VCC to 0.7 VCC 2.5 V v VCC v 4.5 V Timing Reference Voltages 0.5 VCC 2.5 V v VCC v 4.5 V Output Load Current Source IOLmax/IOHmax; CL=100 pF Table 7. POWER−UP TIMING (Notes 6 and 7) Parameter Symbol Max Units tPUR Power−up to Read Operation 1 ms tPUW Power−up to Write Operation 1 ms 5. Test conditions according to “A.C. Test Conditions” table. 6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. www.onsemi.com 3 CAV93C56 Device Operation The CAV93C56 is a 2048−bit nonvolatile memory intended for use with industry standard microprocessors. The CAV93C56 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 11−bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 12−bit instructions control the reading, writing and erase operations of the device. The CAV93C56 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The serial communication protocol follows the timing shown in Figure 2. The ready/busy status can be determined after the start of internal write cycle by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical “1” start bit, a 2−bit (or 4−bit) opcode, 8−bit address (an additional bit when organized X8) and for write operations a 16−bit data field (8−bit for X8 organizations). The instruction format is shown in Instruction Set table. Table 8. INSTRUCTION SET (Note 8) Address Data Instruction Start Bit Opcode x8 x16 READ 1 10 A8−A0 A7−A0 ERASE 1 11 A8−A0 A7−A0 WRITE 1 01 A8−A0 A7−A0 EWEN 1 00 11XXXXXXX 11XXXXXX Write Enable EWDS 1 00 00XXXXXXX 00XXXXXX Write Disable ERAL 1 00 10XXXXXXX 10XXXXXX Clear All Addresses WRAL 1 00 01XXXXXXX 01XXXXXX x8 x16 Comments Read Address AN–A0 Clear Address AN–A0 D7−D0 D7−D0 D15−D0 D15−D0 Write Address AN–A0 Write All Addresses 8. Address bit A8 for 256x8 organization and A7 for 128x16 organization are “Don’t Care” bits, but must be kept at either a “1” or “0” for READ, WRITE and ERASE commands. tSKHI tSKLOW tCSH SK tDIH tDIS VALID VALID DI tCSS CS tDIS tPD0, tPD1 DO DATA VALID Figure 2. Synchronous Data Timing www.onsemi.com 4 tCSMN CAV93C56 Read data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. The READ instruction timing is illustrated in Figure 3. Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAV93C56 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). For the CAV93C56, after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial Erase/Write Enable and Disable The CAV93C56 powers up in the write disable state. Any writing after power−up or after an EWDS (erase/write disable) instruction must first be preceded by the EWEN (erase/write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAV93C56 write and erase instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. The EWEN and EWDS instructions timing is shown in Figure 4. SK CS AN DI 1 1 AN−1 Don’t Care A0 0 tPD0 HIGH−Z DO Dummy 0 D15 . . . D0 or D7 . . . D0 Address + 1 D15 . . . D0 or D7 . . . D0 Address + 2 D15 . . . D0 or D7 . . . D0 Figure 3. READ Instruction Timing SK STANDBY CS DI 1 0 0 * * ENABLE = 11 DISABLE = 00 Figure 4. EWEN/EWDS Instruction Timing www.onsemi.com 5 Address + n D15 . . . or D7 . . . CAV93C56 Write Erase After receiving a WRITE command (Figure 5), address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAV93C56 can be determined by selecting the device and polling the DO pin. Since this device features Auto−Clear before write, it is NOT necessary to erase a memory location before it is written into. Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN (Figure 6). The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SaK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAV93C56 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical “1” state. SK tCSMIN CS STATUS VERIFY AN DI 1 0 AN−1 A0 DN STANDBY D0 1 tSV BUSY HIGH−Z DO READY tHZ HIGH−Z tEW Figure 5. Write Instruction Timing SK CS STATUS VERIFY AN DI 1 1 AN−1 tCS A0 1 tSV DO STANDBY HIGH−Z tHZ BUSY tEW Figure 6. Erase Instruction Timing www.onsemi.com 6 READY HIGH−Z CAV93C56 Erase All Write All Upon receiving an ERAL command (Figure 7), the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAV93C56 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical “1” state. Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN (Figure 8). The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAV93C56 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed. SK CS STATUS VERIFY STANDBY tCS DI 1 0 1 0 0 tSV tHZ HIGH−Z DO BUSY READY HIGH−Z tEW Figure 7. ERAL Instruction Timing SK CS STATUS VERIFY STANDBY tCSMIN DI 1 0 0 0 1 DN D0 tSV tHZ BUSY DO tEW Figure 8. WRAL Instruction Timing www.onsemi.com 7 READY HIGH−Z CAV93C56 ORDERING INFORMATION Device Order Number Specific Device Marking Package Type Temperature Range Lead Finish CAV93C56VE−GT3 93C56D SOIC−8 −40°C to +125°C NiPdAu Tape & Reel, 3,000 Units / Reel M56D TSSOP−8 −40°C to +125°C NiPdAu Tape & Reel, 3,000 Units / Reel CAV93C56YE−GT3 Shipping† †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 9. All packages are RoHS−compliant (Lead−free, Halogen−free). 10. The standard lead finish is NiPdAu. 11. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com www.onsemi.com 8 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 DATE 19 DEC 2008 E SYMBOL MIN A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 MAX 1.27 BSC e PIN # 1 IDENTIFICATION NOM h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 A θ c e b SIDE VIEW L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. DOCUMENT NUMBER: DESCRIPTION: 98AON34272E SOIC 8, 150 MILS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP8, 4.4x3.0, 0.65P CASE 948AL ISSUE A DATE 20 MAY 2022 q q GENERIC MARKING DIAGRAM* XXX YWW AG XXX Y WW A G = Specific Device Code = Year = Work Week = Assembly Location = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON34428E TSSOP8, 4.4X3.0, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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