DATA SHEET
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Synchronous Buck
Regulator with PMBUSt,
15 A
WQFN34 5x7, 0.5P
CASE 510CL
FAN251015
Description
The FAN251015 is a highly efficient synchronous buck regulator
with digital interface, capable of operating with an input range from
4.5 V to 18 V and supporting up to 15 A load currents.
The FAN2510xx utilizes a fixed−frequency voltage−mode control
architecture to provide a synchronized constant switching frequency
while ensuring fast transient response.
Switching frequency and over−current protection can be
programmed to provide a flexible solution for various applications.
Output over−voltage, under−voltage, over−current, and thermal
shutdown protections help prevent damage to the device during fault
conditions.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
VIN Range: 4.5 V to 18 V
PMBUS 1.3.1 Compatible
Accurate Voltage, Current and Thermal Telemetry Reporting
High Efficiency: Over 96% Peak
Continuous Output Current: 15 A
Internal Linear Bias Regulator
Output Voltage Range: 0.5 V to 5.5 V
Adjustable Frequency: 200 kHz to 2.2 MHz
Programmable Soft−Start
Low Shutdown Current
Internal Boot Diode
Thermal Shutdown
This Device is Pb−Free, Halogen Free/BFR Free, and is RoHS
Compliant
MARKING DIAGRAM
$Y
FAN25
1015
AWLYYWW
FAN251015
$Y
A
WL
YY
WW
= Specific Device Code
= onsemi Logo
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information on page 49 of
this data sheet.
Typical Applications
• Server and Desktop Computers, Notebooks, Gaming
• Telecommunications
• High Density Power Solutions
© Semiconductor Components Industries, LLC, 2020
September, 2021 − Rev. 3
1
Publication Order Number:
FAN251015MN/D
FAN251015
VIN
0
0.1μF
2.2μF
2.2μF
VCC
VIN
PVCC
PVIN
BOOT
PGOOD
0.1μF
EN
PH
SALRT
PMBus
CIN
0.1μF
SW
SCL
FAN2510xx
VOUT
L
VOUT+
COUT
SDA
VOUT−
SYNC
VDIFF
RT
ADDR GND PGND GL GH
COMP
FB
Figure 1. Application Circuit
AGND
SYNC
IHS
Current
Monitoring
ILS
EN
Sleep Mode/
UVLO
SYNC
VIN
Freq
Oscillator
Ramp
E/A
DAC
IHS
BOOT
UVLO
PH
PWM
Comparator
Level Shift
PWM
Control
VREF
PVIN
GH
EN
Logic core
BOOT
VCC
Ramp Generator
FB
Bandgap
GND
PVCC
LDO
VIN
Feed−forward
IMON ILIM
VCC
VCC
SW
ILIM
Freq
PVCC
Diff Amp
Deadtime
Control
VIn
VDIFF
IMON
Logic core
ILS
Vdiff
PGND
VREF
Temp Sensor
ILIM
VSEN− VSEN+
COMP
SDA SCL SALERT ADDR VSET PG
Figure 2. Block Diagram
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2
GL
FAN251015
PIN CONNECTIONS
PVIN
PVIN
PGND
PGND
SW
34
33
32
31
30 SW
1
29 SW
SW
PVIN
2
28 SW
27 SW
PVIN
26 SW
PVIN
3
PH
4
GH
5
23 VIN
BOOT
6
22 VCC
GND
7
FB
8
20 SCL
COMP
9
19 SDA
25 GL
GL
24 PVCC
PGND
10
11
13
12
VDIFF VSEN− VSEN+
PG
21 EN
14
15
ADDR VSET
16
GND
17
18
SYNC SALRT
Figure 3. Pin Assignment, Top Transparent View (5x7 mm, 0.5 mm Pin Pitch)
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3
FAN251015
PIN FUNCTION DESCRIPTION
Pad/Pin
Name
Type
1, 2, 3, 34
PVIN
Power
Power Input for the Power stage (High−side MOSFET Drain Connection). Apply Vin
voltage always with Vcc capacitor
4
PH
Power
Return connection for the boot capacitor, internally connected to SW
5
GH
I/O
6
BOOT
Power
Supply for high−side MOSFET gate driver. A capacitor from BOOT to PH supplies the
charge to turn on the N−channel high−side MOSFET. During the freewheeling interval
(low−side MOSFET on), the high−side capacitor is recharged by an internal diode
connected to PVCC
7, 16
GND
Ground
Analog Ground
8
FB
I/O
Inverting input to the voltage error amplifier
9
COMP
I/O
Output of the voltage error amplifier
10
VDIFF
I/O
Output of the VOUT sensing differential amplifier
11
VSEN−
I/O
Negative Input of the VOUT sensing differential amplifier
VSEN+
I/O
Positive Input of the VOUT sensing differential amplifier
13
PG
I/O
Power GOOD; open−drain output indicating VOUT is within set limits
14
ADDR
I/O
PMBUS address programming pin. Use a resistor (with up to 1% tolerance) to set the
address
15
VSET
I/O
VOUT pre−setting pin. Use a resistor (with up to 1% tolerance) to pre−set the output
voltage (PMBUS command can override)
17
SYNC
I/O
Synchronization input or output
18
SALRT
I/O
PMBUS Alert pin
19
SDA
I/O
PMBUS Data pin
20
SCL
I/O
PMBUS Clock pin
21
EN
I/O
Enable input (and PMBUS Control pin)
22
VCC
Power
Output of the linear regulator; Supply pin for the controller. Can NOT be separated from
PVCC. The capacitor should be always connected to this pin
23
VIN
Power
Power input to the linear regulator; also used in the modulator for input voltage
feed−forward. Must always be connected even if the LDO is not used
24
PVCC
Power
Directly supplies power for the low−side gate driver and boot diode. This pin and VCC
can NOT be separated, or connected to the external power supply
12
Description
High−side MOSFET gate monitor (do not connect anything to this pin)
25
GL
I/O
26−31
SW
Power
Low−side MOSFET gate monitor (do not connect anything to this pin)
Switching Node; Internally Connected to the High−side MOSFET Source and Low−side
MOSFET Drain
32, 33
PGND
Ground
Power Ground (Low−side MOSFET Source Connection), internally connected to GND
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4
FAN251015
MAXIMUM RATINGS
All voltages with respect to GND, unless otherwise specified.
Rating (Note 1)
Symbol
Value
Unit
Input Voltage Range
referenced to GND (Note 2)
VPVIN, VIN
−0.3 to 25
V
BOOT voltage range:
referenced to PVCC
referenced to PVCC, < 20 ns
referenced to SW, PH
referenced to PGND
VBOOT
−0.3 to 26
−0.3 to 30
−0.3 to 6
−0.3 to 30
V
SW voltage range:
referenced to PGND
referenced to PGND, 300 mV)
Default TON−Rise
TON−Rise Range (Note 5)
Default TON Delay
TON Delay Range (Note 5)
Default TOFF−Fall
TOFF Delay Range (Note 5)
Default TON MAX FAULT LIMIT
TON MAX FAULT LIMIT Range (Note 5)
CYCLE−BY−CYCLE CURRENT LIMIT
Peak (High−Side) Current Limit Accuracy
ILIMPK = 25 A
Low− Side Current Limit Blanking Time
(Note 5)
AVERAGE OUTPUT CURRENT
ENABLE
Enable Threshold
EN voltage rising
VEN
1.12
1.22
1.32
V
Disable Threshold
EN voltage falling
VDIS
1.00
1.105
1.195
V
VEN,HYS
−
115
−
mV
REN
−
900
−
kW
RENCLMP
−
250
−
kW
Hysteresis
EN Pin Internal Pull−down Resistor
EN Pin Internal Clamp Resistance
VEN = 5 V
VCC UVLO
VCC UVLO Enable Threshold
VCC voltage rising
VCC,EN
−
4
4.35
V
VCC UVLO Disable Threshold
VCC voltage falling
VCC,DIS
3.58
3.8
−
V
VCCHYS
−
175
−
mV
VCC UVLO Hysteresis
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FAN251015
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V, VOUT = 3.3 V, for typical values TA = 25°C, for min/max values TA = TJ = −40°C to 125°C; unless otherwise specified.
Parameter
Test Conditions
Symbol
Min
Typical
Max
Unit
VON
−
6
−
V
VIN Turn−on Threshold Range
VON,RNG
3
−
10.5
V
VIN Turn−on Threshold Accuracy
VON,ACC
−8
−
8
%
VOFF
−
5.5
−
V
VOFF,RNG
2.5
−
10
V
VOFF,ACC
−10
−
8
%
VINOV
−
20
−
V
VIN Overvoltage Threshold Range
VINOV,RNG
18
−
24
V
VIN Overvoltage Threshold Accuracy
VINOV,ACC
−8
−
5
%
VOOV
−
116
−
%
VOOV,RNG
110
−
124
%
−
2
−
%
VOWRN
−
108
−
%
VOWRN,RNG
106
−
116
%
−
2
−
%
VOUV
−
75
−
%
VOUV,RNG
55
−
90
%
−
5
−
%
−
90
−
%
INPUT VOLTAGE PROTECTIONS
Default VIN Turn−on Threshold
Default VIN Turn−off Threshold
VIN rising
VIN falling
VIN Turn−off Threshold Range
VIN Turn−off Threshold Accuracy
Default VIN Overvoltage Threshold
VIN rising
OUTPUT VOLTAGE PROTECTIONS (as a percentage of VOUT)
Default VOUT Overvoltage Threshold
VOUT rising
VOUT Overvoltage Threshold Setting
Range
VOUT Overvoltage Threshold Setting Step
Default VOUT Warning Threshold
VOUT rising
VOUT Warning Threshold Setting Range
VOUT Overvoltage Threshold Setting Step
Default VOUT Under−voltage Threshold
VOUT falling
VOUT Under−voltage Threshold Setting
Range
VOUT Under−voltage Threshold Setting
Step
OUTPUT POWER GOOD (AS A PERCENTAGE OF VOUT)
Default PG Asserting Threshold
VOUT rising
VPGON
PG Asserting Threshold Range (Note 5)
VPGON,RNG
84
−
98
%
PG Asserting Threshold Accuracy
VPGON,ACC
−2
−
2
%
VPGOF
−
84
−
%
PG De−asserting Threshold Range
VPGOF,RNG
82
−
96
%
PG De−asserting Threshold Accuracy
VPGOF,ACC
−2
−
2
%
IPG,LEAK
−
−
1
mA
tPG_FLT
−
5
−
ms
PG Rising Delay
−
560
−
ms
PG Falling Delay
−
10
−
ms
−
6
12
mV
Default PG de−asserting Threshold
VOUT falling
PG Leakage Current
PG De−glitch Filter Duration
PG Output Low Voltage
VPG_L
VOUT = 70% VOUTREF,
IPG = −1 mA
INTERNAL BOOTSTRAP DIODE
Forward Voltage
IF = 10 mA
VFBOOT
−
−
0.3
V
Bootstrap Voltage UVLO
VBOOT falling
VBTUV
2.9
3.2
−
V
Bootstrap Voltage UVLO Hysteresis
VBOOT rising
VBTUVHYS
−
0.35
−
V
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FAN251015
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12 V, VOUT = 3.3 V, for typical values TA = 25°C, for min/max values TA = TJ = −40°C to 125°C; unless otherwise specified.
Parameter
Test Conditions
Symbol
Min
Typical
Max
Unit
TOFF
−
140
−
°C
TOFF,RNG
80
−
160
°C
TOFF
−
115
−
°C
TOFF,RNG
70
−
150
°C
TSHDN
−
160
−
°C
TSHDN,HYS
−
15
−
°C
ttelemetry
−
900
−
ms
VIN,ACC
−5
−
5
%
THERMAL PROTECTION
Default Thermal Fault Threshold
TJ rising
Thermal Fault Threshold Setting Range
Default Thermal Warning Threshold
TJ rising
Thermal Warning Threshold Range
Thermal Shutdown Threshold Umbrella
TJ rising
Thermal Shutdown Hysteresis
TELEMETRY REPORTING
Telemetry Refresh Time Interval (Note 5)
VIN Voltage Accuracy
EN = 0
VOUT Voltage Accuracy
G = 1, VSET = AGND
VOUT,ACC
−2
−
2
%
Output Current Accuracy
IOUT = 3 A to 15 A
IOUT,ACC
−
±10
−
%
Input Current Accuracy
FSW = 600 kHz,
For IOUT = 3 A to 15 A
IOUT,ACC
−
±10
−
%
Temperature Accuracy (Note 5)
0°C − 125°C
TACC
−5
−
5
°C
Pin Capacitance (SCL, SDA)
−
−
10
pF
PMBUS Operating Frequency Range
10
−
400
kHz
Bus Free Time between START and Stop
1.3
−
−
ms
Hold Time after Repeated START
0.6
−
−
ms
Repeated START Setup Time
0.6
−
−
ms
−
ns
PMBUS INTERFACE (Note 5)
0
−
Data Setup Time
100
−
−
ns
Detect Clock Low Timeout
25
−
35
ms
Cumulative Clock Low Master Extend Time
−
−
10
ms
Cumulative Clock Low Slave Extend Time
−
−
25
ms
Clock Low Time
1.3
−
−
ms
Clock High Time
0.6
−
50
ms
−
−
120
ns
Data Hold Time (receive & transmit modes)
SCL/SDA Fall Time
−
−
120
ns
SCL/SDA High/Rising Threshold
1.95
−
−
V
SCL/SDA Low/Falling Threshold
−
−
0.8
V
SCL/SDA Threshold Hysteresis
−
0.6
−
V
Noise Spike Suppression Time
0
−
50
ns
SCL/SDA Rise Time
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at TJ = TA = 25°C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
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FAN251015
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12 V, VOUT = 3.3 V, Fsw = 600 kHz, L = 1 mH (Note 6), COUT = 1000 mF, TA = 25°C, unless otherwise indicated.
0.6
100
0.4
VOUT Error (%)
Efficiency (%)
95
90
85
5.0 VOUT
0.2
0.0
− 0.2
5.0 VOUT
3.3 VOUT
3.3 VOUT
1.8 VOUT
80
− 0.4
1.2 VOUT
1.8 VOUT
1.0 VOUT
1.0 VOUT
0.8 VOUT
− 0.6
75
0
3
6
9
12
15
0
Load Current (A)
3
6
9
12
15
Load Current (A)
Figure 4. Efficiency
Figure 5. Load Regulation
16
Output Current (A)
14
12
10
8
6
4
5.0 VOUT
3.3 VOUT
2
1.0 VOUT
0
25
45
65
85
105
125
Ambient Temperature, TA (5C)
Figure 6. Thermal Safe Operating Area,
No Airflow, PCB: 2 oz. Cu
Figure 7. Thermal Image, No Airflow, IOUT = 15 A
Figure 8. 5 ms Start−Up, No Load
Figure 9. 5 ms Start−Up with 50% Pre−Bias
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FAN251015
Figure 10. Load Transient 0−7.5 A, 10 A/ms
Figure 11. Load Transient 7.5−15 A, 10 A/ms
6. Tests conducted using L = 1.0 mH (Pulse PA4343.102NLT)
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FAN251015
APPLICATION INFORMATION
The FAN251015 is a high−efficiency synchronous buck
converter with integrated controller, driver and two power
MOSFETs. It can operate over a 4.5 V to 18 V input voltage
range, and delivers up to 15 A continuous load current.
FAN2510xx uses a voltage mode PWM control scheme
with input voltage feed−forward feature for wide input
voltage range. A differential amplifier monitors the output
voltage and feeds the high bandwidth error amplifier that
generates the control signal for the pulse width modulation
block. By adjusting the external compensation network, the
system performance can be optimized based on the
application parameters. The Low−Side FET turns ON after
VOUT > 300 mV.
The switching frequency is set by PMBUS programming
and can be synchronized to an external clock signal.
The high−side MOSFET current is sensed for the peak
current limiting function and the output voltage is reduced
in current limiting condition. Other protection functions
include over temperature warning and shut−down, output
voltage under− and over−voltage protections and warning,
output over−current warning, and input over−voltage (all
adjustable by PMBUS).
At the beginning of each switching cycle, the clock signal
initiates a PWM signal to turn on the high−side MOSFET,
and at the same time, the ramp signal starts to rise up. A reset
pulse is generated by the comparator when the ramp signal
intercepts the COMP signal. This reset pulse turns off the
high−side MOSFET and turns on the low−side MOSFET
until the next clock cycle comes. If the current limit is hit, the
high− side MOSFET is turned off until the next PWM signal
(cycle by cycle current limit protection). When certain fault
conditions are met, the device can enter a protection mode
(hiccup or latch−off) to further protect itself.
Table 1. PMBUSTM ADDRESS SETTING
ADDR Resistor
Value (kW)
Offset Address (h) PMBUS Address (h)
0 (short)
−
0F
0.845
00
Base+00
1.3
01
Base+01
1.78
02
Base+02
2.32
03
Base+03
2.87
04
Base+04
3.48
05
Base+05
4.12
06
Base+06
4.75
07
Base+07
5.49
08
Base+08
6.19
09
Base+09
6.98
0A
Base+0A
7.87
0B
Base+0B
8.87
0C
Base+0C
10
0D
Base+0D
≥12.4
−
0F
VOUT Voltage Pre−set
A resistor between the VSET pin and GND (with up to 1%
tolerance) sets the output voltage without having to program
it through PMBUS. It offers 15 different values (see table 2
for details). The VOUT setting can be overridden through
PMBUS programming. The VOUT Voltage Pre−set feature
can be enabled/disabled using MFR MODE (C8h) bit 0,
which is enabled (0) by default.
Table 2. VOUT PRESET SETTING
PMBUS Address
A resistor between the ADDR pin and GND (with up to
1% tolerance) sets the PMBUS offset address, enabling
14 different possible addresses (see Table 1 for details). The
offset address is added to an adjustable base address with
PMBUS. The base section is programmable through MTP.
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VSET Resistor
Value (kW)
VOUT preset value (V)
Short
0.6
0.845
0.6
1.3
0.9
1.78
0.95
2.32
1
2.87
1.05
3.48
1.2
4.12
1.25
4.75
1.5
5.49
1.8
6.19
2.1
6.98
2.5
7.87
3.3
8.87
5
10 & greater value
0.8
FAN251015
Under−voltage Protection
Output Over−current Protection
The FAN2510xx monitors the current in both the
high−side and low−side MOSFETs, and offers several
different sets of protections and warning:
• The threshold is adjustable as a percentage of the
•
High−side FET Positive Cycle−by−cycle Peak Current
Limit with Programmable Delay and Response
• Limits the peak current in the high−side FET at each cycle
to a level adjustable between 1 A and 31 A (using the
IOUT_OC_FAULT_LIMIT command)
• The duration during which it is allowed to run in
cycle−by− cycle current limitation before going into fault
protection mode is adjustable from 0 to 10 ms (using the
IOUT_OC_FAULT_RESPONSE command)
• The fault protection mode is programmable, and can be
chosen between “ignore without VOUT UVLO”, “ignore
with VOUT UVLO”, “1−second hiccup” or “latch−off”
(using the IOUT_OC_FAULT_RESPONSE command)
• An additional limit equal to 130% of the level set by
IOUT_OC_FAULT_LIMIT immediately terminates
switching if reached. This fault can be ignored:
the FAN2510xx is latched off if IOUT_OC_FAULT_
RESPONSE is “latch−off”, otherwise a 1−second hiccup
is applied.
regulated output voltage, between 55% and 90% (using
the PCT_VOUT_LIMIT command)
The amount of filtering is adjustable (between 5 ms and
10 ms) and the fault response is programmable (between
“ignore”, “1−second hiccup” or “latch−off”) using the
VOUT_UV_FAULT_RESPONSE command
Under−voltage Warning
• Based on the output voltage measured by the telemetry
• The threshold is adjustable between 0.1 V and 5.5 V
(using the VOUT_UV_WARN_LIMIT command)
Over−voltage Protection
• The threshold is adjustable as a percentage of the
regulated output voltage, between 110% and 124% (using
the PCT_VOUT_LIMIT command)
• The amount of filtering is adjustable (between 5 ms and
10 ms) and the fault response is programmable (between
“ignore”, “1−second hiccup” or “latch−off”) using the
VOUT_OV_FAULT_RESPONSE command
Over−voltage Warning
• Switching stops when VOUT goes above this warning
Average Output Current Fault with Programmable Delay
and Response
• Based on the output current measured by the telemetry
• Does not limit the cycle−by−cycle current
• The threshold is adjustable between 1 A and 64 A (using
the IOUT_AVG_FAULT_LIMIT command)
• The duration during which the FAN2510xx is allowed to
run above the threshold before going into fault protection
mode is adjustable from 0 to 10ms (using the
IOUT_AVG_FAULT_RESPONSE command)
• The fault protection mode is programmable, and can be
chosen between “ignore”, “1−second hiccup” or
“latch−off”
(using
the
IOUT_AVG_FAULT_
RESPONSE command)
•
•
threshold, and resumes when back in regulation
The threshold is adjustable as a percentage of the
regulated output voltage, between 106% and 116% (using
the PCT_VOUT_LIMIT command), and should be
always set to the less than over−voltage protection
threshold
The behavior can be changed to turn on the low−side FET
to actively pull VOUT down (by using
MFR_MODE_SETTINGS).
Power GOOD Signal and Pin
• The PGOOD signal is held low during soft−start and
•
•
Average Output Current Warning
• Based on the output current measured by the telemetry
• The threshold is adjustable between 1 A and 64 A (using
the IOUT_OC_WARN_LIMIT command)
•
Low−side FET Negative Cycle−by−cycle Current Limit
• Limits the negative low−side FET peak current at each
•
cycle to a level adjustable between 5 A and 12 A (using
the IOUT_UC_FAULT_LIMIT command)
soft−shutdown.
The power good signal is high whenever VOUT is in
regulation, after the end of soft−start
The rising threshold is adjustable as a percentage of the
regulated output voltage, between 84% and 98% (using
the PCT_VOUT_PGOOD command)
The falling threshold is adjustable as a percentage of the
regulated output voltage, between 82% and 96% (using
the PCT_VOUT_ PGOOD command)
The power Good signal also goes low when VOUT is
above the over−voltage protection threshold
Output Voltage Monitoring and Protection
The FAN2510xx monitors the output voltage and offers
several different sets of protections and warnings:
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FAN251015
Output Voltage Margining
FAN2510xx can be set for output voltage margin by
applying positive (margin_high) or negative (margin_low)
offset commands during operation.
Scale loop changes and back to back margining for the
output changes are not supported in FAN2510xx. New offset
can be applied long enough until the previous margining is
completed. In the same scale loop, the big output voltage
changes with the highest slew rate is not recommended if
OVP option is enabled during the margining.
Turn−off Threshold
The FAN2510xx shuts down if VIN is below this
threshold, adjustable between 4 V and 10 V (using the
VIN_OFF command). For less than 4 V, down to 3 V,
external VCC should be used.
Temperature Monitoring and Protection
The FAN2510xx monitors its die temperature and offers
several different sets of protections and warnings:
Over−temperature Protection
• Based on the temperature measured by the telemetry
• The threshold is adjustable between 80°C and 160°C
(using the OT_FAULT_LIMIT command)
• The fault protection mode is programmable, and can be
chosen between “ignore”, “recovery”, “1−second hiccup”
or “latch−off”
(using the OT_FAULT_RESPONSE command)
• In case the die temperature reaches TSHDN (based on the
analog sensor reading), the FAN2510xx immediately
shuts of (including the LDO regulator), even if the fault
response is set to “ignore”
Input SYNC Function
Two parts can be synchronized from an input source as
master/slave with 0° (in phase) or 180° (out phase) phase
shift. When device acts as master, it sends out a 45% duty
cycle clock through SYNC pin with rising edge sync’d with
its own switching cycle. Slave device switching node’s
rising edge lags behind either SYNC CLK’s rising edge (in
phase) or falling edge (out of phase) by 200 ns.
The slave is synchronized to SYNC CLK after it’s
validated over 64 clock cycles. Then, SYNC_CLK is
compared to the internal clock. If outside the ±20%
frequency window when compared to the internal clock, the
device exits slave mode and relies on its internal clock rate.
Refer to INTERLEAVE (Reg37h) section for additional
setting details.
Over−temperature Warning
• Based on the temperature measured by the telemetry
• The threshold is adjustable between 70°C and 150°C
(using the OT_WARN_LIMIT command)
Input Voltage Monitoring and Protection
The FAN2510xx monitors the input voltage and offers
several different sets of protections and warnings:
Protection Summary
The FAN2510xx includes various protection features,
with different behaviors and options. See Table 3 for
a summary, and dedicated sections for more details about
each one.
Over−voltage protection
• The threshold is adjustable between 18 V and 24 V (using
the VIN_OV_FAULT_LIMIT command)
• The amount of filtering is adjustable (between 5 ms and
10 ms) and the fault response is programmable (between
“ignore”, “recovery”, “1−second hiccup” or “latch−off”)
using the VIN_OV_FAULT_RESPONSE command
Turn−on Threshold
The FAN2510xx only starts switching if VIN is above this
threshold, adjustable between 4.5 V and 10.5 V (using the
VIN_ON command). For less than 4.5 V, down to 3 V,
external VCC should be used.
www.onsemi.com
15
FAN251015
Table 3. SUMMARY OF PROTECTION FUNCTIONS
Protection name
Adjustability
Default Behavior
Options
Output overvoltage warning
PMBUS
HS FET and LS FET both turn off
until back in regulation
HS FET turns off but LS FET turns
on until back in regulation
Output overvoltage fault
PMBUS
Switching stops, then enters
protection mode
Ignore, hiccup or latch−off; delay
Output under−voltage fault
PMBUS
Switching stops, then enters
protection mode
Ignore, hiccup or latch−off; delay
Input overvoltage fault
PMBUS
Switching stops until back in range
Ignore, resume when back in range,
hiccup or latch−off
Input under−voltage
PMBUS
Switching stops, part is reset
no
VCC under−voltage
no
Switching stops, part is reset
no
BOOT under−voltage
no
HS FET turns off, LS FET turns on
regularly to refresh VBOOT, until the
fault clears
no
Average output current fault
PMBUS
Switching stops, then enters
protection mode
Ignore, hiccup or latch−off; delay
Peak HS FET current fault
PMBUS
Cycle−by−cycle current limit, enters
protection mode after delay
Ignore, hiccup or latch−off; delay
Peak HS FET current extreme fault
PMBUS
Enters protection mode
Ignore, hiccup or latch−off
Peak negative LS FET current fault
PMBUS
Cycle−by−cycle current limit
no
no
Switching stops, then enters
protection mode
Trim option to change to latch off
Switching stops until back in range
Ignore, resume when back in range
or latch−off
Switch node fault
Over temperature Fault
Umbrella Thermal shutdown
Start−up fault (VOUT UV not met at
the end of timer)
PMBUS
no
PMBUS
Switching stops and VCC LDO turns no
off, until back in range
Switching stops, then enters
protection mode
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16
Ignore, hiccup or latch−off
FAN251015
Telemetry
The FAN2510xx constantly measures its input voltage,
input current, output voltage, output current and die
temperature and reports it in dedicated PMBUS registers.
Each measured value is refreshed every 900 ms.
PMBUS General Description
The PMBUS specification can be found at
www.pmbus.org. FAN2510xx support both the 100 kHz and
400 kHz bus timing requirements. Communication over the
PMBUS interface supports Packet Error Checking (PEC). If
the master provides the clock pulses for the PEC byte, PED
is used. If the additional clock pulses are not present before
a STOP, the PEC is not used. PMBUS has several transaction
formats. The formats that are supported in FAN2510xx are
listed below:
20
15
Accuracy (%)
10
5
PMBUS Send Byte
The send byte transaction is used to send a simple
command to the device. A send byte transaction transfers
a command with no data. The CLEAR_FAULTS command
that clears the current fault flags present in the system is an
example of such a command. A start bit, followed by the
7−bit slave address and finished by a write bit (0−value) to
indicate a write make up the first stage of the transaction. If
the slave ACKs the address, then the host sends the 8−bit
command followed by a stop condition. The format is given
below.
0
−5
−10
−15
−20
0
3
6
9
12
15
Load Current (A)
Figure 12. Typical IOUT Telemetry Accuracy
PMBUS Send Byte
1
7
1
1
8
1
1
S
SLAVE ADDRESS
WR
A
COMMAND_CODE
A
P
transaction. Similar to the send byte transaction above, the
series of start bit, 7−bit slave address with write bit
(0−value), command byte, and finally the 8−bit data byte.
The format is given below.
PMBUS Write Byte
The write byte transaction is used to send single byte data
to the chip. The OPERATION command that configures the
operation of the device is an example of this type of
PMBUS Write Byte
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS
WR
A
COMMAND_CODE
A
DATA_BYTE
A
P
command, the only difference is that after the third
acknowledge (the low data byte) the high byte is sent in
addition.
PMBUS Write Word
The write word transaction is used to send a single word
of data (two bytes) to the chip. The TON_DELAY command
is an example of such a transaction. Similar to the write byte
PMBUS Write Word
1
7
1
1
8
1
8
1
1
1
1
S
SLAVE ADDRESS
WR
A
COMMAND_CODE
A
DATA_BYTE LOW
A
DATA_BYTE HIGH
A
P
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17
FAN251015
following that is the address and read bit send the signal to
the device to return data for the specified command code.
The slave responds by transmitting the byte value requested.
PMBUS Read Byte
The read byte starts out like a normal I2C write transaction
by sending the address and the write bit. The second byte
contains the command code, then a repeated start is sent, and
PMBUS Read Byte
1
7
1
1
8
1
1
7
1
1
8
1
1
S
SLAVE ADDRESS
WR
A
COMMAND_CODE
A
Sr
SLAVE ADDRESS
Rd
A
DATA BYTE
N
P
a repeated start is sent, and following that is the address and
read bit signaling the device to return data for the specified
command code. The slave responds by transmitting the
value requested low byte first and high byte last.
PMBUS Read Word
The read word transaction also starts out like a normal I2C
write transaction by sending the address and the write bit.
The second byte contains the command code, then
PMBUS Read Word
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS
WR
A
COMMAND_CODE
A
Sr
SLAVE ADDRESS
RD
A
DATA BYTE
N
DATA BYTE HIGH
N
P
the message. FAN2510xx allows only 1 byte. The byte count
field can only have the value 01, followed by the one byte of
data.
PMBUS Block Write
The Block Write begins with a slave address and a write
condition. After the command code the host issues a byte
count which describes how many more bytes will follow in
PMBUS Block Write
7
1
S
SLAVE ADDRESS
1
1
WR
A
8
1
COMMAND_CODE
8
A
1
BYTE COUNT = 1
8
A
DATA BYTE
1
1
A
P
preceding the STOP condition signifies the end of the read
transfer.
FAN2510xx allows only 1 byte. The byte count field can
only have the value 01, followed by the one byte of data.
PMBUS Block Read
A Block Read differs from a block write in that the
repeated START condition exists to satisfy the requirement
for a change in the transfer direction. A NACK immediately
PMBUS Block Read
1
S
7
1
1
SLAVE ADDRESS
WR
A
8
COMMAND_CODE
1
1
7
1
A
Sr
SLAVE ADDRESS
RD
1
A
8
1
8
1
1
BYTE COUNT = 1
A
DATA BYTE
A
P
the input bit stream with a fixed CRC polynomial. The PEC
byte is calculated on all bytes in the I2C transaction
including device address and read/write. PEC does not
include start, stop, ACK/NACK, and repeated start bits.
Packet Error Checking (PEC)
PEC is optionally implemented in PMBUS devices, but is
highly recommended due to the critical nature of data
validity in power−management systems. Packet Error Code
(also PEC) bytes are generated using the popular CRC−8
algorithm that is based on performing XOR operations on
PMBUS Send byte with PEC:
PMBUS Send Byte with PEC
7
1
S
SLAVE ADDRESS
1
1
WR
A
8
COMMAND_CODE
1
8
1
1
A
PEC BYTE
A
P
PMBUS Write Byte with PEC:
PMBUS Write Byte with PEC
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS
WR
A
COMMAND_CODE
A
DATA_BYTE
A
PEC BYTE
A
P
www.onsemi.com
18
FAN251015
PMBUS Write Word with PEC:
PMBUS Write Word with PEC
1
7
1
S
SLAVE ADDRESS
WR
1
8
1
8
1
A COMMAND_CODE A DATA_BYTE LOW A
8
1
8
1
1
DATA_BYTE HIGH
A
PEC BYTE
A
P
PMBUS Read Byte with PEC:
PMBUS Read Byte with PEC
1
7
1
1
S SLAVE ADDRESS WR
8
1
1
7
1
1
8
1
8
1
1
A COMMAND_CODE A
Sr
SLAVE ADDRESS
RD
A
DATA BYTE
A
PEC BYTE
A
P
PMBUS Read Word with PEC:
PMBUS Read Word with PEC
1
7
1
1
S SLAVE ADDRESS WR
8
A
1
1
COMMAND_CODE A
Sr
7
1
SLAVE ADDRESS RD
1
8
1
8
1
8
1
1
A
DATA BYTE LOW
A
DATA BYTE
HIGH
A
PEC
BYTE
A
P
PMBUS Block Write with PEC:
PMBUS Block Write with PEC
1
7
1
1
8
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS
WR
A
COMMAND_CODE
A
BYTE COUNT =1
A
DATA BYTE
A
PEC BYTE
A
P
PMBUS Block Read with PEC:
PMBUS Block Read with PEC
1
7
1
1
8
1
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE
ADDRESS
WR
A
COMMAND_CODE
A
Sr
SLAVE
ADDRESS
RD
A
BLOCK COUNT = 1
A
DATA
BYTE
A
PEC BYTE
A
P
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19
FAN251015
PMBUS COMMAND LIST (Note 7)
Address
Default
Value
Default
−
0
Immediate off
−
8’h 17
Turn on with
enable pin
PMBUS Command Name
Type
Range
Step
01h
OPERATION
R/W
−
02h
ON_OFF_CONFIG
R/W
−
03h
CLEAR_FAULTS
Write
−
−
10h
WRITE_PROTECT
R/W
−
−
15h
STORE_USER_ALL
Write
−
−
−
16h
RESTORE_USER_ALL
Write
−
−
−
19h
CAPABILITY
Read
−
−
B0h
1Bh
SMBALERT_MASK
Write
−
−
No alert
masked
20h
VOUT_MODE
Read
−
1.953 mV
17h
21h
VOUT_COMMAND
R/W
0.5 V to 5.5 V
1.953 mV
24h
VOUT_MAX
R/W
0.5 V to 5.5 V
1.953 mV
16’h 0B00
5.5 V
25h
VOUT_MARGIN_ HIGH
0.5 V to 5.5 V
1.953 mV
16’h 06CD
3.4 V
26h
VOUT_MARGIN_ LOW
0.5 V to 5.5 V
1.953 mV
16’h 0667
3.2 V
27h
VOUT_TRANSITION_RATE
R/W
0.203 to 9.375 mV/ms
1.953 mV
16’h D00D
29h
VOUT_SCALE_LOOP
R/W
0.25 to 1
0.25
16’h F002
33h
FREQUENCY_SWITCH
R/W
200 kHz to 2.2 MHz
35h
VIN_ON
R/W
3 V to 10.5 V
0.5 V
16’h F80C
6V
36h
VIN_OFF
R/W
2.5 V to 10 V
0.5 V
16’h F80B
5.5 V
37h
INTERLEAVE
R/W
4 options
16’h 0000
Standalone
41h
VOUT_OV_FAULT_
RESPONSE
R/W
ignore, latch−off, hiccup
−
8’h 40
Latch−off
43h
VOUT_UV_WARN_LIMIT
R/W
0.1 V to 5.5 V
1.953 mV
16’h 0067
0.2 V
45h
VOUT_UV_FAULT_ RESPONSE
R/W
Ignore, latch−off, hiccup
−
8’h 40
Latch−off
46h
IOUT_OC_FAULT_LIMIT
R/W
1 A to 31 A
1A
16’h 0019
25 A
47h
IOUT_OC_FAULT_ RESPONSE
R/W
4 options
−
8’h 80
Latch−off
4Ah
IOUT_OC_WARN_LIMIT
R/W
1 A to 64 A
62.5 mA
16’h E0D0
13 A
Sets average output current warn
4Bh
IOUT_UC_FAULT_LIMIT
R/W
5 A to 12 A
1A
16’h 0008
8A
Sets negative cycle−by−cycle
peak current limit in LSFET
4Fh
OT_FAULT_LIMIT
R/W
80°C to 160°C
1°C
16’h 008C
140°C
50h
OT_FAULT_RESPONSE
R/W
Ignore, hiccup,
latch−off, recovery
−
8’h C0
recovery
51h
OT_WARN_LIMIT
R/W
70°C to 150°C
1°C
16’h 0073
115°C
55h
VIN_OV_FAULT_LIMIT
R/W
18 V to 24 V
2V
16’h 080A
20 V
56h
VIN_OV_FAULT_
RESPONSE
R/W
ignore, hiccup, latch−off,
recovery
−
8’h C0
recovery
60h
TON_DELAY
R/W
1 ms to 10 ms
1 ms
16’h 0001
1 ms
61h
TON_RISE
R/W
1 ms to 20 ms
1 ms
16’h 0005
5 ms
62h
TON_MAX_FAULT_LIMIT
R/W
0 ms to 50 ms
2 ms
16’h 0806
12 ms
R/W
R/W
20
−
8’h 00
Enable all
writes
PEC supported, 400 kHz max,
SMBALERT# supported, linear
formats, AVSBUS not supported
All faults can be individually
masked
−
50−100 kHz 16’h 092C
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Comments
0.203 mV/ms 4 options allowed: 0.203, 1.953,
2.9218, 9.375 mV/ms
0.5
3 options allowed: 0.25, 0.5, 1
600 kHz
Standalone, Master, Slave 0°,
Slave 180°
Adjustable filter
Adjustable filter
Sets cycle−by−cycle peak current
limit in HSFET
Ignore w/o VOUT uv, ignore with
VOUT uv, latch−off, hiccup
Adjustable filter
Adjustable filter
FAN251015
PMBUS COMMAND LIST (Note 7) (continued)
Default
Value
Default
8’h 80
Latch−off
1 ms
16’h 0000
0 ms
1 ms to 20 ms
1 ms
16’h 0005
5 ms
Read
−
−
−
STATUS_WORD
Read
−
−
−
7Ah
STATUS_VOUT
Read
−
−
−
7Bh
STATUS_IOUT
Read
−
−
−
7Ch
STATUS_INPUT
Read
−
−
−
7Dh
STATUS_TEMPERATURE
Read
−
−
−
7Eh
STATUS_CML
Read
−
−
−
80h
STATUS_MFR_SPECIFIC
Read
−
−
−
88h
READ_VIN
Read
0 to 25 V
31.25 mV
−
89h
READ_IIN
Read
0 to 64 A
62.5 mA
−
8Bh
READ_VOUT
Read
0 to 5.5 V
1.953 mV
−
8Ch
READ_IOUT
Read
0 to 64 A
62.5 mA
−
8Dh
READ_TEMPERATURE
Read
−40°C to 175°C
1°C
−
95h
READ_FREQ
Read
200 kHz to 2.5 MHz
1 kHz
98h
PMBUS_REVISION
Read
−
−
8’h 33
33h
99h
MFR_ID
Block R/W
−
−
16’h 1501
1501h
Block R/W format,
The LSB byte can only be 01(h)
9Ah
MFR_MODEL
Block R/W
−
−
16’h 1501
1501h
Block R/W format,
The LSB byte can only be 01(h)
9Bh
MFR_REVISION
Block
Read
−
−
16’h 4X01
4X01h
Block R/W format,
The LSB byte can only be 01(h)
9Eh
MFR_SERIAL
Block R/W
−
−
16’h 0001
0001h
Block R/W format,
The LSB byte can only be 01(h)
A4h
MFR_VOUT_MIN
Read
−
−
16’h 0100
0.5
A5h
MFR_VOUT_MAX
Read
−
−
16’h 0B01
5.5
ADh
IC_DEVICE_ID
Block
Read
−
−
16’h 4001
4001h
Block R format,
The LSB byte can only be 01(h)
AEh
IC_DEVICE_REV
Block
Read
−
−
16’h 4001
4001h
Block R format,
The LSB byte can only be 01(h)
C4h
IOUT_AVG_FAULT_
RESPONSE
R/W
ignore, hiccup, latch−off
8’h 80
Latch−off
C5h
IOUT_AVG_FAULT_LIMIT
R/W
1 A to 64 A
62.5 mA
16’h E140
20 A
Sets OCP average current limit
C6h
PCT_VOUT_LIMIT
R/W
110% to 124%
2%
16’h 06E0
116%
Replaces
VOUT_OV_FAULT_LIMIT
R/W
106% to 116%
2%
108%
Replaces
VOUT_OV_WARN_LIMIT
R/W
55% to 90%
5%
75%
Replaces
VOUT_UV_FAULT_LIMIT
R/W
84% to 98%
2%
90%
Replaces POWER_GOOD_ON
R/W
82% to 96%
2%
84%
Replaces POWER_GOOD_OFF
Address
PMBUS Command Name
Type
Range
63h
TON_MAX_FAULT_
RESPONSE
R/W
ignore, latch−off, hiccup
64h
TOFF_DELAY
R/W
0 ms to 10 ms
65h
TOFF_FALL
R/W
78h
STATUS_BYTE
79h
C7h
PCT_VOUT_PGOOD
Step
www.onsemi.com
21
8’h 19
Comments
PMBUS rev 1.3
Adjustable delay
FAN251015
PMBUS COMMAND LIST (Note 7) (continued)
PMBUS Command Name
Type
Range
Step
Default
Value
C8h
MFR_MODE_SETTINGS
R/W
CCM/DCM,
Enable/Disable VSET pin,
turn on/off LS FET at
OV_WARN
−
8’h A0
C9h
MFR_PMBUS_BASE
R/W
CAh
MFR_ID2
R/W
Address
Default
Comments
CCM, Enable
VSET pin, LS
FET OFF at
OV_WARN
Enables VSET pin setting for
VOUT, and enables LSFET
turn−on at OV_WARN.
Bits 7:4 are used for IMON HSD
RIIN programmability.
7’h10
10h
Sets the PMBUS base address
16’h 4F4E
4F4Eh
R/W Word format,
MFR_ID2 register is added for
customers who need 16 bits of
MFR ID. MTP bits allocated for all
16 bits
7. The regulation should be always disabled when:
− Writing commands that change device settings.
− Accessing the MTP using STORE_USER_ALL & RESTORE_USER_ALL commands.
− The device should be discarded, If #ALERTB pad is pulled low during startup and indicates the MTP programming Fault (Bit#1 of
STATUS_MFR_SPECIFIC).
PMBUS Commands Details
OPERATION (01h)
• Select whether fault conditions caused by margining are
The OPERATION command is one byte command used
to configure the operational state of the converter, in
conjunction with input from the ENABLE pin.
The OPERATION command is used to:
• Turn the PMBUS device output on and off with
commands sent over the PMBUS
• Select the margin state of the device (margin off, margin
high, margin low)
ignored or acted upon
• Select whether the converter powers down immediately
or follows the programmed TOFF_DELAY and
TOFF_FALL commands when commanded to turn off
the output
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command.
Operation Command Bit Number
Bit 7 ON/
OFF
Behavior
Bit
Device State/Response
Bit
Margin
Bit 6 Turn Voltage
Command
Fault
OFF
Bit < 1:0>
Source Response Not Used
Behavior
On/Off
Power OFF Behavior
Output Voltage
Command
Source
Device Response
R/W
R/W
R/W
R/W
R
(reads 00
only)
0
0
XX
XX
XX
Off
Immediate Off
N/A
Immediate OFF
0
1
XX
XX
XX
Off
Power down sequencing
N/A
Use TOFF_DELAY &
TOFF_FALL for shutdown
1
X
01
01
XX
On
1
X
01
10
XX
On
N/A
1
X
10
01
XX
On
N/A
1
X
10
10
1
X
00
XX
VOUT_MAR
GIN_LOW
VOUT_MAR
GIN_LOW
Ignore faults when margined
Act on faults when margined
VOUT_MAR
GIN_HIGH
Ignore faults when margined
XX
VOUT_MAR
GIN_HIGH
Act on faults when margined
XX
VOUT_CO
MMAND
List if all Invalid Data Operation Bits
100100
www.onsemi.com
22
Regulate to VOUT commanded value
FAN251015
110100
100111
110111
101000
111000
101011
111011
NOTE: Invalid data fault flag gets set if invalid data is sent. Any data other than the data listed above is accepted.
ON_OFF_CONFIG (02h)
The ON_OFF_CONFIG command is one byte command.
This command configures the combination of ENABLE pin
input and serial bus commands needed to turn the unit on and
off. This includes how the unit responds when power is
applied. The default response for any PMBUS device is
specified by the device manufacturer.
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command.
GENERIC STRADDLE TABLE
Default
R/W
access
Bit
Number
000
R/W
[7:5]
1
R/W
4
0
1
1
1
R/W
R/W
R/W
R/W
3
2
1
0
Purpose
Bit Value
Meaning
0
Reserved
Sets the default to either operate any
time power is present or for the on/off
to be controlled by ENABLE pin and
serial bus commands
0
Chip turns on when VCC is present
1
Chip does not turn on until commanded by the
ENABLE pin and OPERATION command
(as programmed in bits [3:0])
Controls how the unit responds to
commands received via the serial bus
0
Bit [7] of OPERATION command is ignored
1
Bit[7] of the OPERATION command needs to be
high and depending on Bit [2] of ON_OFF_
CONFIG, the unit may also require the ENABLE
pin to be asserted for the chip to start.
Controls how the unit responds to the
ENABLE pin
0
Unit ignores the ENABLE pin (on/off controlled
only by the OPERATION command)
1
The ENABLE pin needs to be asserted to start
the unit.
Depending on Bit [3] of ON_OFF_CONFIG, the
OPERATION command may also be required to
instruct the chip to start
0
Active low (Pull pin low to turn on the chip)
– Not Supported
1
Active high (Pull high to turn on the chip)
0
Use the programmed turn off delay
(TOFF_DELAY) and fall time (TOFF_FALL)
1
Turn off the output immediately
Polarity of the ENABLE pin
ENABLE pin action when commanding
the unit to turn off
ON_OFF_CONFIG Valid
data Bits
Turn on behavior
0XX1
Turn on any time power is up
1011
Turn on with ENABLE pin ( Default setting)
1101
Turn on with the PMBus bit
(Bit 7 OPERATION command)
1111
Tunr on when both ENABLE pin and PMBus bit
#7 of OPERATION command are high
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23
FAN251015
CLEAR_FAULTS (03h)
• 00010000b indicates that bit [4] is to be cleared and all
The CLEAR_FAULTS command is used to clear any fault
bits that have been set. This command clears all bits in all
status registers simultaneously. At the same time, the device
negates (clears, releases) its SMBALERT# signal output if
the device is asserting the SMBALERT# signal.
The CLEAR_FAULTS command does not cause a unit
that has latched off for a fault condition to restart. Any
device that has shut down due to a fault condition remains
off until:
• A RESET signal (if one exists) is asserted,
• The output is commanded through the CONTROL pin,
the OPERATION command, or the combined action of
the CONTROL pin and OPERATION command, to turn
off and then to turn back on, or
• Bias power (VCC) is removed from the PMBUS device
other bits are to be unchanged,
• 01100010b indicates that bits [6], [5], and [1] are to be
cleared and all other bits are to be unchanged
• 11111111b, or FFh, indicates all bits are to be cleared
WRITE_PROTECT (10h)
The WRITE_PROTECT command is used to control
writing to the PMBUS device. The intent of this command
is to provide protection against accidental changes. This
command is not intended to provide protection against
deliberate or malicious changes to a device’s configuration
or operation. All supported commands may have their
parameters read, regardless of the WRITE_PROTECT
settings. This command has one data byte, described in
below table.
If a device receives a data byte that is not listed in the table,
then the device shall treat this as invalid data, declare a
communications fault. If a PMBUS device receives
unsupported data, the response is that the device shall:
• Flush or ignore the received command code and any
received data,
• Set the CML bit in the STATUS_BYTE,
• Set the Invalid or Unsupported Data Received bit in the
STATUS_CML register
If the fault is still present when the bit is cleared, the fault
bit shall immediately be set again and the host notified by the
usual means.
Clearing Individual Bits
Any or all of the bits in any status register except
STATUS_BYTE and STATUS_WORD can be directly
cleared by issuing the status command with one data byte
that is written. The data byte is a binary value. A 1 in any bit
position indicates that bit is to be cleared, if set, and
unchanged if not set. Examples of data bytes:
Data Byte Value
Meaning
1000_0000
Disable all writes except to the WRITE_PROTECT command
0100_0000
Disable all writes except to the WRITE_PROTECT and OPERATION commands
0010_0000
Disable all writes except to the WRITE_PROTECT, OPERATION,
ON_OFF_CONFIG and VOUT_COMMAND commands
0000_0000
Enable writes to all commands (default)
Any other data other than given in the above table will
cause an invalid data fault. The contents of this register can
be stored to nonvolatile memory using the
STORE_USER_ALL command.
Store memory (MTP). It is permitted to use the
STORE_USER_ALL command while the device is
operating. However, the device may be unresponsive during
the copy operation with unpredictable, undesirable or even
catastrophic results. This command is not allowed until the
initial MTP reading is done during startup. This command,
once received, takes ~110 ms to complete successfully.
This command has no data bytes, and it is write only.
STORE_USER_ALL (15h)
The STORE_USER_ALL command instructs the
PMBUS device to copy the entire contents of the Operating
Memory to the matching locations in the non−volatile User
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FAN251015
RESTORE_USER_ALL (16h)
initial MTP reading is done during startup. This command
once received takes ∼2.5 ms to complete successfully.
This command has no data bytes, and it is write only.
The RESTORE_USER_ALL command instructs the
PMBUS device to copy the entire contents of the
non−volatile User Store memory (MTP) to the matching
locations in the Operating Memory. The values in the
Operating Memory are overwritten by the value retrieved
from the User Store. This command is allowed only when
output is disabled. This command is not allowed until the
CAPABILITY (19h)
This command provides a way for a host system to
determine some key capabilities of a PMBUS device. There
is one data byte formatted as shown in the below Table. This
command is read only and returns 1011_0000.
Bits
R/W Access
Default
Description
Value
7
Read only
1
Packet Error
Checking
0
Packet Error Checking not supported
1
Packet Error Checking is supported
Maximum Bus
Speed
00
Maximum supported bus speed is 100 kHz
01
Maximum supported bus speed is 400 kHz
10
Maximum supported bus speed is 1 MHz
11
Reserved
0
The device does not have a ALERT# pin and does
not support the PMBus Alert Response Protocol
1
The device does have a ALERT# pin and supports
the PMBus Alert Response Protocol and ARA if base
address ≥40h. With multiple slaves responding during arbitration, the device does not release the SDA
signal if a lower address slave responds.
0
Numeric data is in LINEAR11, ULINEAR16,
SLINEAR16 or DIRECT format
1
Numeric data is in IEEE Half precision Floating Point
Format
0
AVS Bus not supported
1
AVS Bus supported
6:5
4
3
2
1:0
Read only
01
Read only
1
Read only
ALERT#
0
Read only
Numeric Format
0
Read only
AVS Bus
Support
00
Reserved
Reserved
SMBALERT_MASK (1Bh)
the mask byte 01000000b, then an Over temperature
Warning condition would be blocked from asserting
SMBALERT#.
The SMBALERT_MASK command may be used to
prevent a warning or fault condition from asserting the
SMBALERT# signal. The command format used to block a
status bit or bits from causing the SMBALERT# signal to be
asserted. The bits in the mask byte align with the bits in the
corresponding status register. For example if the
STATUS_TEMPERATURE command code were sent with
Mode
Bit[7]
Bit[6:5]
ULINEAR16
X
00b
Meaning
VOUT_MODE (20h)
Supports Linear Mode only: ULINEAR16 Format. The
ULINEAR16 format is given below
Bit[4:0] (Parameter)
Five bit two’s compliment exponent for the mantissa delivered as the
data bytes for an output voltage related command
VOUT_MODE
command
is
used
for
VOUT_COMMAND,
VOUT_MAX,
VOUT_MARGIN_HIGH,
VOUT_MARGIN_LOW,
VOUT_UV_WARN_LIMIT,
commands.
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25
and
READ_VOUT
FAN251015
VOUT_MODE, Data Byte for
Linear Mode
7 6 5 4 3 2 1 0
Mode = 00b
Exponent N
VOUT COMMAND, VOUT_MAX Data Bytes
For Linear Mode
Data B yte High
Data Byte Low
6 5 4 3 2 1 0 7 6 5 4 3 2
Mantissa V
7
Sets the maximum allowed VOUT target regardless of
any other commands or combinations. The VOUT_MAX
follows the ULINEAR16 format. If mantissa is not within
the range 256 to 2817(d), it flags an invalid data fault. The
contents of this register can be stored to nonvolatile memory
using the STORE_USER_ALL command.
Range
Resolution
Default
0.5−5.5 V
1.953 mV
5.5 V
VOUT_COMMAND (21h)
Sets the value of VOUT when the OPERATION
command is configured for PMBUS nominal operation. The
VOUT_COMMAND follows the ULINEAR16 format. The
contents of this register can be stored to nonvolatile memory
using the STORE_USER_ALL command.
Resolution
Default
0.5−5.5 V
1.953 mV
−V
VOUT_MARGIN_HIGH (25h)
Sets the value of VOUT when the OPERATION
command is configured for margin high. The
VOUT_MARGIN_HIGH follows the ULINEAR16 format.
If the data is lower or equal to VOUT_MARGIN_LOW
setting, it flags an invalid data fault. Also if mantissa is not
within the range 256 to 2816, it flags an invalid data fault.
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command.
RECOMMENDED VOUT_SCALE_LOOP SETTING
VOUT Range
VOUT_SCALE_LOOP
0.5−1.99 V
F004
1.992−3.99 V
F002
4.0−5.5 V
F001
0
VOUT_MAX (24h)
The Mode bits are set to 000b. The Voltage, in Volts is
calculated from the equation: Voltage = V X 2 N
Where, Voltage is the parameter of interest in Volts; V is
a 16 bit unsigned binary integer, and N is a 5 bit two’s
compliment binary integer. The exponent N is fixed −9,
VOUT step size = 1.953 mV with 10 bit DAC. Attempt to
write to VOUT_MODE command will cause an invalid data
fault. VOUT_MODE Read back is 17(hex).
Range
1
Range
Resolution
Default
0.5−5.5 V
1.953 mV
3.4 V
VOUT_MARGIN_LOW (26h)
Sets the value of VOUT when the OPERATION
command is configured for margin low. The
VOUT_MARGIN_LOW follows the ULINEAR16 format.
If the data is higher or equal to VOUT_MARGIN_HIGH
setting, it flags an invalid data fault. Also if mantissa is not
within the range 256 to 2816, it flags an invalid data fault.
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command.
Exponent is FIXED −9 and Mantissa Range is 256 to
2816. Any data outside this range flags is an invalid data
fault. If MFR_MODE(C7hex) Bit#0 is set low the VSET pin
sets the default value of this register. Some Examples for
setting the VOUT are given below.
VOUT Voltage
PMBUS DATA
0.8 V
019A(hex)
1.0 V
0200(hex)
Range
Resolution
Default
1.5 V
0300(hex)
0.5−5.5 V
1.953 mV
3.2 V
2.0 V
0400(hex)
3.3 V
069A(hex)
5.0 V
0A00(hex)
5.5 V
0B00(hex)
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26
FAN251015
VOUT_TRANSITION_RATE (27h)
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command. The
VOUT_TRANSITION_RATE command has two data
bytes encoded in LINEAR11 format as shown below (5bits
signed exponent and 11 bits mantissa)
When a PMBUS device receives either a
VOUT_COMMAND or OPERATION (Margin High,
Margin Low, Margin Off) that causes the output voltage to
change, this command sets the rate in mV/ms at which the
output should change voltage. This commanded rate of
change does not apply when the unit is commanded to turn
on or to turn off.
LINEAR11 Format
Data Byte High
7
6
5
4
3
Data Byte Low
2
1
0
N
7
6
5
4
3
2
1
0
Y
The relation between Y, N and the real world value is
X = Y 2N
Where X is the real world value; Y is the 11 bit, two’s
compliment integer, and N is a 5 bit, two’s compliment
integer Exponent N is Fixed −6 ⇒11010(b) (Equivalent
LSB = 15.625 mV/ms)
Mantissa Y: Only 4 options allowed 00D, 07D, 0BB,
258(hex).
All the options allowed are given below. The default is
0.203 mV/ms. Attempting to write a value other than the
values listed in the below table will cause an invalid data
fault.
Transition Rate in mV/ms
PMBUS Data(hex)
0.203
D00D
1.953
D07D
2.9218
D0BB
9.375
D258
PMBUS Data(hex)
Gain
F001
0.25
F002
0.5
F004
1
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command. The
VOUT_SCALE_LOOP command has two data bytes
encoded in LINEAR11 format:
• Exponent N is Fixed 11110(b) (Equivalent LSB = 0.25)
• Mantissa Y: Only 3 options allowed 01, 02, 04(hex)
FREQUENCY_SWITCH (33h)
The FREQUENCY_SWITCH command sets the
switching frequency in kHz. This command has two data
bytes encoded in LINEAR11 format. Exponent N is Fixed
00001(b) (Equivalent LSB = 2 kHz)
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command.
VOUT_SCALE_LOOP (29h)
The VOUT_SCALE_LOOP sets the output sense scaling
ratio for the main control loop. FAN2510xx supports only 3
options/ratios: 1, 0.5, 0.25. Attempting to write a value other
than the values listed in the below table will cause an invalid
data fault.
Range
Resolution
Default
200−2200 kHz
2 kHz
600 kHz
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FAN251015
All the options supported are given in the Table below.
Any data other than the data given in the table below will flag
an invalid data fault.
Frequency (kHz)
PMBUS Data (hex)
200
0864
250
087D
300
0896
350
08AF
400
08C8
450
08E1
500
08FA
550
0913
600
092C
650
0945
700
095E
750
0977
800
0990
850
09A9
900
09C2
950
09DB
1000
09F4
1050
0A0D
1100
0A26
1150
0A3F
1200
0A58
1300
0A8A
1400
0ABC
1500
0AEE
1600
0B20
1700
0B52
1800
0B84
1900
0BB6
2000
0BE8
2100
0C1A
2200
0C4C
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28
FAN251015
VIN_ON (35h)
is unsigned binary. The contents of this register can be stored
to nonvolatile memory using the STORE_USER_ALL
command. The format, supported range and resolution are
given in the below table.
The VIN_ON command sets the value of VIN in Volts at
which the chip should start the power conversion. The two
data bytes are encoded in LINEAR11 format as shown
below. Exponent is in 2’s compliment format and mantissa
Data Byte High
Data Byte Low
5 Bit Exponent
11 Bit Unsigned Mantissa
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
1
0
0
0
Default Exponent
1
1
1
1
Default Mantissa
1
0
0
0
0
VIN ON Threshold (V)
F806
3
F807
3.5
F808
4
F809
4.5
F80A
5
F80B
5.5
F80C
6
F80D
6.5
F80E
7
F80F
7.5
F810
8
F811
8.5
F812
9
F813
9.5
F814
10
F815
10.5
0
0
compliment format and mantissa is unsigned binary. The
contents of this register can be stored to nonvolatile memory
using the STORE_USER_ALL command. The format is
same as VIN_ON command. The range and resolution are
given in the below table.
Default VIN UVLO Rising Threshold: 6 V
VIN UVLO Rising Threshold Range: 3.0 V to 10.5 V
VIN_IN Exponent: Fixed −1 (Equivalent LSB = 0.5 V)
All the options supported are given in the Table below.
Any data other than the data given in the table below will flag
an invalid data fault. If VIN “on” data is lower or equal to VIN
“off”; the invalid data flag is set. If the input voltage does not
reach the rising VIN UVLO Threshold after the VCC Enable
Threshold is crossed, a VIN UVLO Fault will trigger.
PMBUS data
0
Range
Resolution
Default
2.5−10.0 V
0.5 V
6 V(F80C (hex))
All the options supported are given in the Table below.
Any data other than the data given in the table below will flag
an invalid data fault. If Vin_off data is higher than Vin_on
the invalid data flag is set.
VIN_OFF (36h)
The VIN_OFF command sets the value of the input
voltage in volts at which the unit once operation has started
should stop power conversion. The two data bytes are
encoded in LINEAR11 format. Exponent is in 2’s
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29
PMBUS data
VIN OFF Threshold (V)
F805
2.5
F806
3
F807
3.5
F808
4
F809
4.5
F80A
5
F80B
5.5
F80C
6
F80D
6.5
F80E
7
F80F
7.5
F810
8
F811
8.5
F812
9
F813
9.5
F814
10
FAN251015
INTERLEAVE (37h)
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command. The
default is set to standalone.
The INTERLEAVE command is used to arrange multiple
units to facilitate paralleling of multiple units. The
Interleave is a 16− bit command with 3 components (plus 4
unused bits in front):
• Group ID (4 bits)
• Number of units in the group (4 bits)
• Interleave order of the unit in the group (4 bits)
The following options are supported by FAN251015:
Standalone:
Group ID = 0, Number of units = 0, Interleave order = 0
[0000 0000 0000 0000] ⇒ unit is neither master nor slave,
does not drive the SYNC pin and ignores any clock on
SYNC pin.
For synchronization
Description
5:3
2:0
Retry Setting
(Latchoff or
Hiccup)
Delay Time
16’b0000_0000_0000_0000
Standalone
16’b0000_0001_0000_0000
Master Sync
16’b0000_0001_0010_0000
Sync Slave − In Phase
16’b0000_0001_0010_0001
Sync Slave − Out of Phase
VOUT_OV_FAULT_RESPONSE command Instructs
the device on what action to take in response to an output
over voltage fault set based on the manufacture specific
command PCT_VOUT_LIMIT(C6h), Bits.
•
•
•
•
Slave:
• Group ID = 1, Number of units = 2, Interleave order = 0
[0000 0001 0010 0000] ⇒ the unit operates in−phase to
the clock applied on its SYNC (or operates on its own
internal clock if no clock on SYNC)
• Group ID = 1, Number of units = 2, Interleave order = 1
[0000 0001 0010 0001] ⇒ the unit operates out−of−phase
to the clock applied on its SYNC (or operates on its own
internal clock if no clock on SYNC).
7:6
Mode
VOUT_OV_FAULT_RESPONSE (41h)
Master:
Group ID = 1, Number of units = 0, Interleave order = 0
[0000 0001 0000 0000] ⇒ unit is master, and sends its
internal clock out on the SYNC pin.
Bits
PMBUS Data
The device also sets
Sets the VOUT_OV bit in the STATUS_BYTE
Sets the VOUT bit in the STATUS_WORD
Sets the VOUT OV Fault bit in the STATUS_VOUT
Notifies the host by asserting the ALERTB
The fault bit once set is cleared only in accordance with
Clear Faults section and not when the fault condition is
removed. The contents of this register can be stored to
nonvolatile memory using the STORE_USER_ALL
command.
The default of this register is set to 40(hex) ⇒ latch off
behavior The data byte is encoded in the format shown
below
Value
Meaning
00
Chip continues operation without interruption
01
Chip continues operation for the delay time specified by bits[2:0].
If the fault condition is still present at the end of the delay time,
the chip responds as programmed in the Retry setting (bits[5:3])
10
Not Supported – The chip shuts down (disables the output) and responds according
to the retry setting bits[5:3]
11
Not Supported – The chip’s output is disabled while the fault is present. Operation
resumes and the output is enabled when the fault condition no longer exists
000
001−110
A zero value for the retry setting means that the chip does not attempt to restart.
The output remains disabled until the faulty is cleared
Not Supported
111
The chip attempts to restart continuously without limitation, until it is commanded
OFF (by the ENABLE pin or OPERATION command or both), VIN/VCC is removed
or another fault condition causes the unit to shut−down. Hiccup time is 1 s
XXX
X00− 6.25 ms
X01 – 7.5 ms
X10 – 8.75 ms
X11 − 10 ms
For 0 V warning the FETs are turned off immediately. An
option is provided to turn off the high side FET and turn on
the low side FET. MFR_MODE _SETTINGS(C8) Bit
is used for this purpose. An attempt to write “Not supported”
data given in the table above will flag an invalid data fault.
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30
FAN251015
VOUT_UV_WARN_LIMIT (43h)
under voltage fault set based on the manufacture specific
command PCT_VOUT_LIMIT(C6h) Bits.
The device also
• Sets the VOUT bit in the STATUS_WORD
• Sets the VOUT UV Fault bit in the STATUS_VOUT
• Notifies the host by asserting the ALERTB
The VOUT_UV_WARN_LIMIT command specifies the
VOUT UV warn limit threshold. The command follows the
ULINEAR16 format. The contents of this register can be
stored
to
nonvolatile
memory
using
the
STORE_USER_ALL command. The range, resolution and
default value is given in the table below.
Range
Resolution
Default
0.5−5.5 V
1.9535 mV
0.2 V (0067 (hex))
The fault bit once set is cleared only in accordance with
Clear Faults section and not when the fault condition is
removed. The contents of this register can be stored to
nonvolatile memory using the STORE_USER_ALL
command.
The default of this register is set to 40(hex) ⇒ latch off
behavior The data byte is encoded in the format shown
below
When VOUT crosses the VOUT UV threshold the
STATUS _VOUT(7A) Bit#6 is flagged.
VOUT_UV_FAULT_RESPONSE (45h)
VOUT_UV_FAULT_RESPONSE command Instructs
the device on what action to take in response to an output
Bits
Description
7:6
5:3
2:0
Retry Setting
(Latchoff or
Hiccup)
Delay Time
Value
Meaning
00
Chip continues operation without interruption
01
Chip continues operation for the delay time specified by bits[2:0]. If the fault condition is still present at the end of the delay time, the chip responds as programmed in
the Retry setting (bits[5:3])
10
Not Supported – The chip shuts down (disables the output) and responds according
to the retry setting bits[5:3]
11
Not Supported – The chip’s output is disabled while the fault is present. Operation
resumes and the output is enabled when the fault condition no longer exists.
000
001−110
A zero value for the retry setting means that the chip does not attempt to restart.
The output remains disabled until the faulty is cleared
Not Supported
111
The chip attempts to restart continuously without limitation, until it is commanded
OFF (by the ENABLE pin or OPERATION command or both), VIN/VCC is removed
or another fault condition causes the unit to shutdown. Hiccup time is 1 s
XXX
X00 – 6.25 ms
X01 – 7.5 ms
X10 – 8.75 ms
X11 – 10 ms
(5 bits un−signed exponent and 11 bits mantissa). The range,
resolution and default are shown in the below table.
An attempt to write “Not supported” data given in the
table above will flag an invalid data fault.
IOUT_OC_FAULT_LIMIT (46h)
This command sets the value of the peak output current in
amperes for the high side FET and causes an over current
peak detection fault. The IOUT_OC_FAULT_LIMIT
command has two data bytes encoded in LINEAR11 format
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31
Range
Resolution
Default
1−31 A
1
25 A (0019(hex))
FAN251015
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command. The
exponent is read only and if an exponent other than 1 is
written, an invalid data fault is flagged. All the options
supported are given in the Table below. Any data other than
the data given in the table below will flag an invalid data
fault.
PMBUS Data(hex)
OC Peak Fault Limit(A)
0001
1
0002
2
0003
3
0004
4
0005
5
0006
6
0007
7
0008
8
0009
9
000A
10
000B
11
000C
12
000D
13
000E
14
000F
15
0010
16
0011
17
0012
18
0013
19
0014
20
0015
21
0016
22
0017
23
0018
24
0019
25
001A
26
001B
27
001C
28
001D
29
001E
30
001F
31
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FAN251015
IOUT_OC_FAULT_RESPONSE (47h)
The fault bit once set is cleared only in accordance with
“Clear Faults” section and not when the fault condition is
removed. The contents of this register can be stored to
nonvolatile memory using the STORE_USER_ALL
command.
The default of this register is set to 80(hex) ⇒ latch off
behavior.
The data byte is encoded in the format shown below.
This command instructs the device on what action to take
in response to an output over current peak fault The device
also
• Sets the IOUT bit in the STATUS_WORD
• Sets the IOUT bit in the STATUS_BYTE
• Sets the OCP Peak Fault Bit #7 in the STATUS_IOUT
• Notifies the host by asserting the ALERTB
Bits
Description
7:6
5:3
2:0
NOTE:
Retry Setting
(Latchoff or
Hiccup)
Delay Time
Value
Meaning
00
Chip continues operation without interruption while maintaining the output current at
the values set by IOUT_OC_FAULT_LIMIT without regard to the output voltage
01
Chip continues operating indefinitely except if VOUT_UV is detected
10
The chip continues to operate, maintaining the output current at the value set by
IOUT_OC_FAULT_LIMIT without regard to the output voltage. For the delay time
set by bits[2:0]. If the chip is still operating in current limiting at the end of the delay
time , the chip responds as programmed by the Retry Setting in bits[5:3]
11
The chip shuts down and responds as programmed by the Retry setting in bits[5:3]
000
001−110
A zero value for the retry setting means that the chip does not attempt to restart.
The output remains disabled until the faulty is cleared
Not Supported
111
The chip attempts to restart continuously without limitation, until it is commanded
OFF (by the ENABLE pin or OPERATION command or both), VIN/VCC is removed
or another fault condition causes the unit to shutdown. Hiccup time is 1 s
XXX
000 – 160−320 ms
001 – 320−480 ms
010 – 640−800 ms
011 – 1.28−1.44 ms
100 – 2.56−2.72 ms
101 – 5.12−5.28 ms
110 – 9.6−9.76 ms
111 – 10.08−10.24 ms
An attempt to write “Not supported” data given in the table above will flag an invalid data fault.
IOUT_OC_WARN_LIMIT (4Ah)
Few examples are given in the Table below. The exponent
is read only and if an exponent other than −4(11100b) is
written, an invalid data fault is flagged. There is no range
check on this command.
This command sets the value of the output current in
amperes that causes a over current detection warn flag.
The IOUT_OC_WARN_LIMIT command has two data
bytes encoded in LINEAR11 format (5 bits signed exponent
and 11 bits mantissa). The range, resolution and default are
shown in the below table.
Range
Resolution
Default
1−64 A
62.5 mA
13 A (E0D0(hex))
Examples
IOUT OC WARN Limit
PMBUS Data
10 A
E0A0(hex)
15 A
E0F0(hex)
20 A
E140(hex)
25 A
E190(hex)
30 A
E1E0(hex)
35 A
E230(hex)
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command.
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33
FAN251015
IOUT_UC_FAULT_LIMIT (4Bh)
The fault bit once set is cleared only in accordance with
Clear Faults section and not when the fault condition is
removed.
This command sets the value of the output negative
current limit in amperes that causes a under current detection
fault flag. The IOUT_UC_FAULT_LIMIT command has
two data bytes encoded in LINEAR11 format (5 bits
un−signed exponent and 11 bits mantissa). The range,
resolution and default are shown in the below table.
Range
Resolution
Default
5−12 A
1A
8 A (0008(hex))
OT_FAULT_LIMIT (4Fh)
This command sets the temperature in degrees Celsius at
which chip should indicate an over temperature fault. The
OT_FAULT_LIMIT command has two data bytes encoded
in LINEAR11 format (5 bits unsigned exponent and 11 bits
mantissa). The range, resolution and default are shown in the
below table.
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command. The
exponent is read only and if an exponent other than
0(00000b) is written, an invalid data fault is flagged. All the
options supported are given in the Table below. Any data
other than the data given in the table below will flag an
invalid data fault.
•
•
•
•
IOUT UC FAULT Limit
PMBUS Data
5A
0005(hex)
6A
0006(hex)
7A
0007(hex)
8A
0008(hex)
9A
0009(hex)
10 A
000A(hex)
11 A
000B(hex)
12 A
000C(hex)
Range
Resolution
Default
80−160°C
1°C
140°C
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command. The
exponent is read only and if an exponent other than
0(00000b) is written, an invalid data fault is flagged. The
mantissa range is 80°C to 160°C. Any mantissa outside this
range will assert invalid data fault. Also if the OT fault limit
is set lower or equal to OT warn limit then an invalid data
fault is flagged. Few examples are given in the Table below.
When this fault happens the device sets
Sets the None of the above bit in the STATUS_BYTE
Sets the IOUT bit in the STATUS_WORD
Sets the IOUT UC Fault bit in the STATUS_IOUT
Notifies the host by asserting the ALERTB
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34
OT Fault Limit
PMBUS Data
80°C
0050(hex)
90°C
005A(hex)
100°C
0064(hex)
105°C
0069(hex)
120°C
0078(hex)
160°C
00A0(hex)
FAN251015
OT_FAULT_RESPONSE (50h)
The fault bit once set is cleared only in accordance with
Clear Faults section and not when the fault condition is
removed. The contents of this register can be stored to
nonvolatile memory using the STORE_USER_ALL
command.
The default of this register is set to C0(hex) ⇒ recovery
The data byte is encoded in the format shown below
OT_FAULT_RESPONSE command Instructs the device
on what action to take in response to an over temperature
fault set by OT_FAULT_LIMIT command. The device also:
• Sets the Temp bit in the STATUS_BYTE
• Sets the Over Temp Fault bit in the STATUS_TEMP
• Notifies the host by asserting the ALERTB
Bits
Description
Value
7:6
Ignore/latchoff
or recovery
00
Chip continues operation without interruption
01
Not Supported − Chip continues operation for the delay time specified by bits[2:0].
If the fault condition is still present at the end of the delay time, the chip responds
as programmed in the Retry setting (bits[5:3])
10
The chip shuts down (disables the output) and responds according to the retry
setting bits[5:3]
11
The chip’s output is disabled while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists
5:3
Retry Setting
(Latchoff )
000
001−110
2:0
Delay Time
Meaning
A zero value for the retry setting means that the chip does not attempt to restart.
The output remains disabled until the faulty is cleared
Not Supported
111
Not Supported The chip attempts to restart continuously without limitation, until it is
commanded OFF (by the ENABLE pin or OPERATION command or both), VIN/
VCC is removed or another fault condition causes the unit to shut−down. Hiccup
time is 1 s
XXX
Not Supported
is set higher or equal to OT fault limit then an invalid data
fault is flagged. Few examples are given in the Table below.
An attempt to write “Not supported” data given in the
table above will flag an invalid data fault.
OT_WARN_LIMIT (51h)
This command sets the temperature in degrees Celsius at
which chip should indicate an over temperature warn flag.
The OT_WARN_LIMIT command has two data bytes
encoded in LINEAR11 format (5 bits unsigned exponent
and 11 bits mantissa). The range, resolution and default are
shown in the below table.
Range
Resolution
Default
70−150°C
1°C
115°C
OT Warn Limit
PMBUS Data
80°C
0050(hex)
90°C
005A(hex)
100°C
0064(hex)
105°C
0069(hex)
120°C
0078(hex)
160VC
00A0(hex)
When over temperature warn flag is asserted, the device:
• Sets the Temp bit in the STATUS_BYTE
• Sets the Over Temp Warn bit in the STATUS_TEMP
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command. The
exponent is read only and if an exponent other than
0(00000b) is written, an invalid data fault is flagged. The
mantissa range is 70°C to 150°C. Any mantissa outside this
range will assert invalid data fault. Also if the OT warn limit
The warn bit once set is cleared only in accordance with
Clear Faults section and not when the warn condition is
removed.
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35
FAN251015
VIN_OV_FAULT_LIMIT (55h)
VIN_OV_FAULT_RESPONSE (56h)
This command sets the value of the input voltage VIN in
volts that causes an input over voltage fault.
The VIN_OV_FAULT_LIMIT command has two data
bytes encoded in LINEAR11 format (5 bits unsigned
exponent and 11 bits mantissa). The range, resolution and
default are shown in the below table.
VOUT_OV_FAULT_RESPONSE command Instructs
the device on what action to take in response to an input over
voltage
fault
set
based
on
the
VIN_OV_FAULT_LIMIT(55h) . The device also sets
• Sets the None of the above bit in the STATUS_BYTE
• Sets the VIN OVP bit in the STATUS_WORD
• Sets the VIN OV Fault bit in the STATUS_INPUT
• Notifies the host by asserting the ALERTB
Range
Resolution
Default
18−24 V
2V
20 V
The fault bit once set is cleared only in accordance with
Clear Faults section and not when the fault condition is
removed. The contents of this register can be stored to
nonvolatile memory using the STORE_USER_ALL
command.
The default of this register is set to C0(hex) ⇒ Recovery
behavior The data byte is encoded in the format shown
below.
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command. The
exponent is read only and if an exponent other than
1(00001b) is written, an invalid data fault is flagged. All the
options supported are given in the Table below. Any data
other than the data given in the table below will flag an
invalid data fault.
VIN Fault Limit
PMBUS Data
18 V
0809(hex)
20 V
080A(hex)
22 V
080B(hex)
24 V
080C(hex)
Bits
Description
7:6
5:3
2:0
Retry Setting
(Latchoff or
Hiccup)
Delay Time
Value
Meaning
00
Chip continues operation without interruption
01
Chip continues operation for the delay time specified by bits[2:0].
If the fault condition is still present at the end of the delay time, the chip responds
as programmed in the Retry setting (bits[5:3])
10
Not Supported – The chip shuts down (disables the output) and responds according
to the retry setting bits[5:3]
11
The chip’s output is disabled while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists.
000
A zero value for the retry setting means that the chip does not attempt to restart.
The output remains disabled until the faulty is cleared
001−110
Not Supported
111
Not Supported
XXX
X00 – 6.25 ms
X01 – 7.5 ms
X10 – 8.75 ms
X11 – 10 ms
For 0 V warning the FETs are turned off immediately. An
option is provided to turn off the high side FET and turn on
the low side FET. MFR_MODE _SETTINGS(C8) Bit
is used for this purpose. An attempt to write “Not supported”
data given in the table will flag an invalid data fault.
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36
FAN251015
TON_DELAY (60h)
This command sets the time, in milliseconds, from when
a start condition is received (as programmed by the
ON_OFF_CONFIG command) until the output voltage
starts to rise. The TON_DELAY command has two data
bytes encoded in LINEAR11 format (5 bits unsigned
exponent and 11 bits mantissa). The range, resolution and
default are shown in the below table.
Range
Resolution
Default
1−10 ms
1 ms
1 ms
TON Rise
PMBUS Data
1 ms
0001(hex)
2 ms
0002(hex)
3 ms
0003(hex)
5 ms
0005(hex)
9 ms
0009(hex)
10 ms
000A(hex)
TON_MAX_FAULT_LIMIT (62h)
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command. The
exponent is read only and if an exponent other than
0(00000b) is written, an invalid data fault is flagged. Any
mantissa Bit if not 00(hex) will assert invalid data
fault. Few examples are given in the Table below.
This command sets an upper limit, in milliseconds, on
how long the unit can attempt to power up the output without
reaching the output under voltage fault limit. The
TON_MAX_FAULT_LIMIT command has two data bytes
encoded in LINEAR11 format (5 bits unsigned exponent
and 11 bits mantissa). The range, resolution and default are
shown in the below table.
TON Delay
PMBUS Data
1 ms
0001(hex)
Range
Resolution
Default
2 ms
0002(hex)
0−50 ms
2 ms
12 ms
3 ms
0003(hex)
5 ms
0005(hex)
9 ms
0009(hex)
10 ms
000A(hex)
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command. The
exponent is read only and if an exponent other than
1(00001b) is written, an invalid data fault is flagged. Any
mantissa Bit if not 00(hex) will assert invalid data
fault. 0ms setting will also set an invalid data fault. Few
examples are given in the Table below.
TON_RISE (61h)
This command sets the time, in milliseconds, from when
the output starts to rise until the voltage has entered the
regulation band. The TON_RISE command has two data
bytes encoded in LINEAR11 format (5 bits unsigned
exponent and 11 bits mantissa). The range, resolution and
default are shown in the below table.
Range
Resolution
Default
1−20 ms
1 ms
5 ms
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command. The
exponent is read only and if an exponent other than
0(00000b) is written, an invalid data fault is flagged. Any
mantissa Bit if not 00(hex) will assert invalid data
fault. 0ms setting will also set an invalid data fault. Few
examples are given in the Table below.
TON Max Fault Limit
PMBUS Data
2 ms
0801(hex)
4 ms
0802(hex)
10 ms
0805(hex)
20 ms
080A(hex)
30 ms
080F(hex)
40 ms
0814(hex)
TON_MAX_FAULT_RESPONSE (63h)
TON_MAX_FAULT_RESPONSE command Instructs
the device on what action to take in response to an Ton−max
fault set by TON_MAX_FAULT_LIMIT command; The
device also:
• Sets the VOUT bit in the STATUS_BYTE
• Sets the TON MAX fault bit in the STATUS_VOUT
• Notifies the host by asserting the ALERTB
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37
FAN251015
The default of this register is set to 80(hex) ⇒ Latchoff
The data byte is encoded in the format shown below
The fault bit once set is cleared only in accordance with
Clear Faults section and not when the fault condition is
removed. The contents of this register can be stored to
nonvolatile memory using the STORE_USER_ALL
command.
Bits
Description
Value
7:6
Ignore/latchoff or
recovery
00
Chip continues operation without interruption
01
Not Supported − Chip continues operation for the delay time specified by bits[2:0]. If
the fault condition is still present at the end of the delay time, the chip responds as
programmed
in the Retry setting (bits[5:3])
10
The chip shuts down (disables the output) and responds according to the retry
setting bits[5:3]
11
Not Supported −The chip’s output is disabled while the fault is present. Operation
resumes and the output is enabled when the fault condition no longer exists.
000
A zero value for the retry setting means that the chip does not attempt to restart.
The output remains disabled until the faulty is cleared
5:3
Retry Setting
(Latchoff )
Meaning
001−110
2:0
NOTE:
Delay Time
Not Supported
111
The chip attempts to restart continuously without limitation, until it is commanded
OFF (by the ENABLE pin or OPERATION command or both), VIN/VCC is removed
or another fault condition causes the unit to shutdown. Hiccup time is 1 s
XXX
Not Supported
An attempt to write “Not supported” data given in the table above will flag an invalid data fault.
TOFF_DELAY (64h)
TOFF_FALL (65h)
This command sets the time, in milliseconds, from when
a stop condition is received (as programmed by the
ON_OFF_CONFIG command) until the unit stops
transferring energy to the output. The TOFF_DELAY
command has two data bytes encoded in LINEAR11 format
(5bits unsigned exponent and 11 bits mantissa). The range,
resolution and default are shown in the below table.
This command sets the time, in milliseconds, from the end
of the turn−off delay time until the voltage is commanded to
zero. The TOFF_FALL command has two data bytes
encoded in LINEAR11 format (5 bits unsigned exponent
and 11 bits mantissa). The range, resolution and default are
shown in the below table.
Range
Resolution
Default
0−10 ms
1 ms
0 ms
Range
Resolution
Default
1−20 ms
1 ms
5 ms
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command. The
exponent is read only and if an exponent other than
0(00000b) is written, an invalid data fault is flagged. Any
mantissa Bit if not 00(hex) will assert invalid data
fault. 0ms setting will also set an invalid data fault. Few
examples are given in the Table below.
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command. The
exponent is read only and if an exponent other than
0(00000b) is written, an invalid data fault is flagged. Any
mantissa Bit if not 00(hex) will assert invalid data
fault. Few examples are given in the Table below.
TOFF Delay
PMBUS Data
TOFF Fall
PMBUS Data
1 ms
0001(hex)
1 ms
0001(hex)
2 ms
0002(hex)
2 ms
0002(hex)
3 ms
0003(hex)
3 ms
0003(hex)
5 ms
0005(hex)
5 ms
0005(hex)
9 ms
0009(hex)
9 ms
0009(hex)
10 ms
000A(hex)
10 ms
000A(hex)
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FAN251015
STATUS_BYTE (78h)
This command returns one byte of information with the
summary of the critical faults. The below table shows all the
bits.
Bit
Function
Support
7
Busy – nonvolatile memory is being accessed either for read or write operation
Yes
6
OFF
Yes
5
VOUT_OVP Fault
Yes
4
IOUT_OC(Peak Fault)
Yes
3
VIN_UV
No
2
Temperature Fault or Warn
Yes
1
CML(PEC Failed, Invalid data or Invalid command)
Yes
0
None of the above (vin_ovp, vin_off, ocp average fault, hsd_ilim2, lsd_ilim,
pgood_fault, vout_uvlo_fault, vout_ uvwarn, ocp_warn, ocp_peak & uvlo fault,
over temp umbrella, sw_fault, boot_uvlo, all STATUS_MFR faults
Yes
STATUS_WORD (79h)
STATUS_WORD is the same register as STATUS_BYTE
command. The below table shows all the bits in the upper
byte.
This command returns two bytes of information with the
summary of the critical faults. The lower byte of
Upper Byte Bit #
Function
Supporting
7
VOUT(all STATUS_VOUT)
Yes
6
IOUT/POUT(Peak OCP Fault or Average OCP Fault or Warn or Neg ILIM Fault)
Yes
5
INPUT(VIN OVP Fault & VIN_OFF Fault)
Yes
4
MFR(all STATUS_MFR)
Yes
3
POWERGOOD#
Yes
2
FANS
No
1
Other
No
0
Unknown
No
If output voltage is valid then POWERGOOD# bit is
cleared. If output voltage is not present POWERGOOD# is
set.
bits. The table also shows SMBALERT_MASK command
support.
STATUS_VOUT (7Ah)
This command returns one byte of information with the
summary of the VOUT faults. The below table shows all the
Status VOUT Reporting
Support
Support Alert Mask
Bit output over voltage fault
Yes
Yes
Bit output over voltage warning
Yes
No
Bit output under voltage warning
Yes
No
Bit output under voltage fault
Yes
Yes
Bitoutput max or min warning
No
No
Bit ton max fault
Yes
Yes
Bit ton max warning
No
No
Bit output voltage tracking error
No
No
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39
FAN251015
STATUS_IOUT (7Bh)
bits. The table also shows SMBALERT_MASK command
support.
This command returns one byte of information with the
summary of the IOUT faults. The below table shows all the
Status IOUT Reporting
Support
Support Alert Mask
Bit output over current peak fault
Yes
Yes
Bit output over current and low voltage fault
Yes
Yes
Bit output over current average warning
Yes
No
Bit output under current fault
Yes
Yes
Bit current share fault
No
No
Bit in power limiting mode
No
No
Bit output overpower fault
No
No
Bit output overpower warning
No
No
STATUS_INPUT (7Ch)
bits. The table also shows SMBALERT_MASK command
support.
This command returns one byte of information with the
summary of the VIN faults. The below table shows all the
Status INPUT Reporting
Support
Support Alert Mask
Bit input over voltage fault
Yes
Yes
Bit input over voltage warning
No
No
Bit input under voltage warning
No
No
Bit input under voltage fault
No
No
Bit unit off for insufficient input voltage
Yes
Yes
Bit input over current fault
No
No
Bit input over current warning
No
No
Bit input overpower warning
No
No
STATUS_TEMPERATURE (7Dh)
all the bits. The table also shows SMBALERT_MASK
command support.
This command returns one byte of information with the
summary of the temperature faults. The below table shows
Status Temperature Reporting
Support
Support Alert Mask
Bit over temperature fault
Yes
Yes
Bit over temperature warning
Yes
No
Bit under temperature warning, reports 0
No
No
Bit under temperature fault
No
No
Bit Reserved, reports 0
No
No
Bit Reserved, reports 0
No
No
Bit Reserved, reports 0
No
No
Bit Reserved, reports 0
No
No
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40
FAN251015
STATUS_CML(7Eh)
This command returns one byte of information with the
summary of the below faults. The table also shows
SMBALERT_MASK command support.
Status CML Reporting
Support
Support Alert Mask
Bit command not supported
Yes
Yes
Bit invalid data
Yes
Yes
Bit PEC fault
Yes
Yes
Bit OTP fault − Not supported, reports 0
No
No
Bit Reserved, reports 0
No
No
Bit other communication fault, reports 0
No
No
Bitother memory or logic fault, reports 0
No
No
STATUS_MFR_SPECIFIC (80h)
This command returns one byte of information with the
summary of the below faults. The table also shows
SMBALERT_MASK command support.
Status MFR Reporting
Support
Support Alert Mask
Bit ocp average fault flag
Yes
Yes
Bit hsd_ilim2
Yes
Yes
Bitsw_fault
Yes
Yes
Bitboot_uvlo
Yes
Yes
Bit over temp analog
Yes
Yes
Bit Lg Pin Fault
Yes
Yes
Yes
Yes
No
No
Bit
MTP
Programming Fault
Bit Not used, reports 0
READ_VIN (88h)
READ_IIN (89h)
The READ_VIN command returns the input voltage in
Volts. The two data bytes are encoded in LINEAR11 format
(5 bits signed exponent and 11 bits mantissa). Exponent is
FIXED −5 (11011b) indicating a LSB of 31.25 mV.
The range and resolution are shown in the below table.
The READ_IIN command returns the input current in
Amps. The two data bytes are encoded in LINEAR11 format
(5 bits signed exponent and 11 bits mantissa). Exponent is
FIXED −4 (11100b) indicating a LSB of 62.5 mA. The range
and resolution are shown in the below table. READ_IIN
acknowledges only if the device is regulating.
Range
Resolution
0−25 V
31.25 mV
Range
Resolution
0−64 A
62.5 mA
Few examples are given in the Table below.
Few examples are given in the Table below.
Read VIN
PMBUS Data
6V
D8C0(hex)
10 V
D940(hex)
6
E060(hex)
12 V
D980(hex)
10
E0A0(hex)
18 V
DA40(hex)
12
E0C0(hex)
18
E120(hex)
Read IIN(Amps)
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41
PMBUS Data
FAN251015
READ_VOUT(8Bh)
format as set by the VOUT_MODE command. The two data
bytes are encoded in LINEAR16 format as shown in below.
The READ_VOUT command returns the actual,
measured (not commanded) output voltage in the same
7
READ_VOUT ULINEAR16 Format
Data Byte High
Data Byte Low
6 5 4 3 2 1 0 7 6 5 4 3 2
1
0
Mantissa V
READ_TEMPERATURE(8Dh)
The exponent is defined by VOUT_MODE command.
Exponent is FIXED −9 (10111b) indicating a LSB of
1.953 mV.
The range and resolution are shown in the below table.
READ_VOUT will only acknowledge if the device is
regulating.
Range
Resolution
0.5 V−5.5 V
1.953 mV (set by VOUT_MODE command)
The READ_TEMPERATURE command returns the
measured temperature in degree Celsius. The two data bytes
are encoded in LINEAR11 format (5 bits unsigned exponent
and 11 bits signed mantissa). Exponent is FIXED 0 (00000b)
indicating a LSB of 1°C.The range and resolution are shown
in the below table.
Few examples are given in the Table below.
Range
Resolution
−40 to 175°C
1°C
Few examples are given in the Table below.
Read VOUT(V)
PMBUS Data
0.8 V
019A(hex)
1.0 V
0200(hex)
1.5 V
0300(hex)
2.0 V
0400(hex)
3.3 V
069A(hex)
5.0 V
0A00(hex)
5.5 V
0B00(hex)
0−64 A
62.5 mA
PMBUS Data
6
E060(hex)
10
E0A0(hex)
12
E0C0(hex)
18
E120(hex)
0019(hex)
50
0032(hex)
100
0064(hex)
−20
07EC(hex)
Range
Resolution
100 Khz – 2.5 MHz
1 KHz
Few examples are given in the Table below.
Few examples are given in the Table below.
Read IOUT(Amps)
25
The READ_ FREQ command returns the switching
frequency in KHz. The two data bytes are encoded in
LINEAR11 format (5bits unsigned exponent and 11 bits
unsigned mantissa). Exponent is FIXED 0 (00000b)
indicating a LSB of 1KHz. The range and resolution are
shown in the below table. READ_FREQ will only
acknowledge if the device is regulating.
The READ_IOUT command returns the measured output
current in Amps. The two data bytes are encoded in
LINEAR11 format (5 bits signed exponent and 11 bits
mantissa). Exponent is FIXED −4 (11100b) indicating a
LSB of 62.5 mA. The range and resolution are shown in the
below table. “READ_IOUT” will not acknowledge if the
device is not regulating.
Resolution
PMBUS Data
READ_FREQ(95h)
READ_IOUT(8Ch)
Range
Read Temp (°C)
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42
Read Freq (KHz)
PMBUS Data
200
00C8(hex)
400
0190(hex)
600
0258(hex)
800
0320(hex)
FAN251015
PMBUS_REVISION(98h)
indicate the revision of PMBUS specification Part I to which
the device is compliant. Bits [3:0] indicate the revision of
PMBUS specification Part II to which the device is
compliant. The permissible values are shown below.
PMBUS_REVISION command stores or reads the
revision of the PMBUS to which the device is compliant.
This command is read only and has one data byte. Bits [7:4]
Bits [7:4]
Part I Revision
Bits[3:0]
Part II
Revision
0000b
1.0
0000b
1.0
0001b
1.1
0001b
1.1
0010b
1.2
0010b
1.2
0011b
1.3
0011b
1.3
FAN2510xx supports Revsion1.3 and therefore reads
back 33(hex) for PMBUS_REVISION command.
MFR_ID(99h)
MFR_ID command is used to either set or read the
manufacture’s ID (name, abbreviation or symbol that
identifies the unit’s manufacturer). This command is
7
Dat a Byte High
6 5 4 3 2
read/write accessible and has two data bytes as shown
below.
MFR_ID Format
Byte Count = 1
1 0 7 6 5 4 3 2
1
0
Block R/W Format
MFR_REVISION (9Bh)
The Block R/W format needs to be used to access this
register for read and write operations. The lower byte
represents the number of bytes and this is fixed to
1(00000001b). The higher byte is used to represent the
MFR_ID.
The higher byte contents of this register can be stored to
nonvolatile memory using the STORE_USER_ALL
command.
MFR_REVISION command is used to either set or read
the manufacture’s revision number. This command is
read/write accessible and has two data bytes. The Block
R/W format needs to be used to access this register for read
and write operations. The lower byte represents the number
of bytes and this is fixed to 1(00000001b). The higher byte
is used to represent the MFR_REVISION.
The higher byte contents of this register can be stored to
nonvolatile memory using the STORE_USER_ALL
command.
MFR_MODEL (9Ah)
MFR_MODEL command is used to either set or read the
manufacture’s model number. This command is read/ write
accessible and has two data bytes. The Block R/W format
needs to be used to access this register for read and write
operations. The lower byte represents the number of bytes
and this is fixed to 1(00000001b). The higher byte is used to
represent the MFR_MODEL.
The higher byte contents of this register can be stored to
nonvolatile memory using the STORE_USER_ALL
command.
MFR_SERIAL (9Eh)
MFR_SERIAL command is used to either set or read the
manufacture’s serial number of the device. This command
is read/write accessible and has two data bytes. The Block
R/W format needs to be used to access this register for read
and write operations. The lower byte represents the number
of bytes and this is fixed to 1(00000001b). The higher byte
is used to represent the MFR_SERIAL. The higher byte
contents of this register can be stored to nonvolatile memory
using the STORE_USER_ALL command.
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43
FAN251015
MFR_VOUT_MIN (A4h)
IC_DEVICE_REV (AEh)
MFR_VOUT_MIN command is used to retrieve the
minimum rated value, in Volts, to which the output voltage
may be set for the device. This command is read accessible
and has two data bytes in UNLINEAR16 format. The
exponent is defined by VOUT_MODE command. Exponent
is FIXED −9 (10111b) indicating a LSB of 1.953 mV. The
read back of this register is set to 0100(hex) to represent
0.5 V.
IC_DEVICE_REV command is used to read the revision
of the IC whose type or part number is read with the
IC_DEVICE_ID command. This command is read
accessible and has two data bytes. The Block Read format
needs to be used to access this register for read operation.
The lower byte represents the number of bytes and this is
fixed to 1(00000001b). The higher byte is used to represent
the IC_DEVICE_REV.
MFR_VOUT_MAX (A5h)
IOUT_AVG_FAULT_RESPONSE (C4h)
MFR_VOUT_MIN command is used to retrieve the
maximum rated value, in Volts, to which the output voltage
may be set for the device. This command is read accessible
and has two data bytes in UNLINEAR16 format The
exponent is defined by VOUT_MODE command. Exponent
is FIXED −9 (10111b) indicating a LSB of 1.953 mV. The
read back of this register is set to 0B01(hex) to represent
5.5 V.
This manufacture specific command instructs the device
on what action to take in response to an output over current
average fault. The device also:
• Sets the IOUT bit in the STATUS_WORD
• Sets the None of the above bit in the STATUS_BYTE
• Sets the OCP Average Fault Bit #7 in the
STATUS_MFR_SPECIFIC
• Notifies the host by asserting the ALERTB
IC_DEVICE_ID (ADh)
The fault bit once set is cleared only in accordance with
“ClearFaults” section and not when the fault condition is
removed. The contents of this register can be stored to
nonvolatile memory using the STORE_USER_ALL
command.
The default of this register is set to 80(hex) ⇒ latch off
behavior The data byte is encoded in the format shown
below
IC_DEVICE_ID command is used to read the type or part
number of the IC embedded within a PMBUS that is used for
the PMBUS interface. This command is read accessible and
has two data bytes. The Block Read format needs to be used
to access this register for read operation. The lower byte
represents the number of bytes and this is fixed to
1(00000001b). The higher byte is used to represent the
IC_DEVICE_ID.
Bits
Description
7:6
5:3
2:0
NOTE:
Retry
Setting(Latchoff
or Hiccup)
Delay Time
Value
Meaning
00
Chip continues operation without interruption while maintaining the output current at
the values set by IOUT_OC_FAULT_LIMIT without regard to the output voltage
01
Chip continues operating indefinitely except if VOUT_UV is detected
10
The chip continues to operate, maintaining the output current at the value set by
IOUT_OC_FAULT_LIMIT without regard to the output voltage. For the delay time set
by bits[2:0]. If the chip is still operating in current limiting at the end of the delay time ,
the chip responds as programmed by the Retry Setting in bits[5:3]
11
The chip shuts down and responds as programmed by the Retry setting in bits[5:3]
000
001−110
A zero value for the retry setting means that the chip does not attempt to restart. The
output remains disabled until the faulty is cleared
Not Supported
111
The chip attempts to restart continuously without limitation, until it is commanded OFF
(by the ENABLE pin or OPERATION command or both), VIN/VCC is removed or another fault condition causes the unit to shutdown. Hiccup time is 1 second
XXX
000 – 160−320 ms
001 – 320−480 ms
010 – 640−800 ms
011 – 1.28−1.44 ms
100 – 2.56−2.72 ms
101 – 5.12−5.28 ms
110 – 9.6−9.76 ms
111 – 10.08−10.24 ms
An attempt to write “Not supported” data given in the table above will flag an invalid data fault.
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44
FAN251015
IOUT_AVG_FAULT_LIMIT (C5h)
Examples
This manufacturer specific command sets the value of the
output current in amperes that causes an average over
current
detection
fault
flag.
The
IOUT_OC_FAULT_LIMIT command has two data bytes
encoded in LINEAR11 format (5 bits signed exponent and
11 bits mantissa). The range, resolution and default are
shown in the below table.
Range
Resolution
Default
1−64 A
62.5 mA
20 A (E140(hex))
IOUT_AVG_FAULT Limit
PMBUS Data
10 A
E0A0(hex)
15 A
E0F0(hex)
20 A
E140(hex)
30 A
E1E0(hex)
40 A
E280(hex)
45 A
E2D0(hex)
PCT_VOUT_LIMIT (C6h)
The contents of this register can be stored to nonvolatile
memory using the STORE_USER_ALL command. Few
examples are given in the Table below. The exponent is read
only and if an exponent other than −4(11100b) is written, an
invalid data fault is flagged. The 0A setting is not allowed
and there is no maximum value range check on this
command.
This manufacturer specific command sets the value of the
output voltage in terms of %, the level that causes an output
under voltage, over voltage 1, over voltage 2 fault.
The PCT_VOUT_LIMIT command has two data bytes
encoded in LINEAR16 format. The contents of this register
can be stored to nonvolatile memory using the
STORE_USER_ALL command. The below table shows all
the options allowed
Bit
OVP2
Thresh(Fault)
Bit
OVP1 Thresh (Warn)
Bit
UVLO
Thresh
000
110%
000
N/A
000
55%
001
112%
001
N/A
001
60%
010
114%
010
106%
010
65%
011
116%
011
108%
011
70%
100
118%
100
110%
100
75%
101
120%
101
112%
101
80%
110
122%
110
114%
110
85%
111
124%
111
116%
111
90%
Default is set to OVP Warn: 108%, OVPFault−116%,
UVLO Fault−75% (Default = 06E0(hex)).
OVP Warn threshold needs to be less than OVP Fault
threshold. UVLO Fault threshold needs to be less than OVP
Fault and Warn threshold.
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FAN251015
PCT_PGOOD_LIMIT (C7h)
This manufacture specific command sets the value of the
good on and off levels in %. The PCT_PGOOD_LIMIT
command has one byte. The contents of this register can be
stored
to
nonvolatile
memory
using
the
STORE_USER_ALL command.
The below table shows all the options allowed
Bit
PGOOD ON
Bit
PGOOD OFF
000
84%
000
82%
001
86%
001
84%
010
88%
010
86%
011
90%
011
88%
100
92%
100
90%
101
94%
101
92%
110
96%
110
94%
111
98%
111
96%
Bit #
Function
Default
0
“1” Disable Select VSET pin
Select VSET(0)
1
2
“1” Enable LS on for OVP1
3
Unused
4
Input IMON
LS off (0)
0
1010
5
6
7
VSET pin resistor (with up to 1% tolerance) is used to set the
initial Vout setting of the device. The table shows the
mapping from various resistors to the selected Vout and gain
setting. A MFR_MODE_SETTINGS bit is used to
select this initial VSET value or not.
The default PGOOD ON level is set to 90% and default
PGOOD OFF level is set to 84% (19(hex)). If PGOOD_ON
level is set to a value which is less than PGOOD_OFF level
an invalid data fault is flagged.
VSET Resistor
Value (kW)
VOUT Preset
Value (V)
Gain
Short
0.6
1
0.845
0.6
1
1.3
0.9
1
1.78
0.95
1
2.32
1
1
2.87
1.05
1
3.48
1.2
1
4.12
1.25
1
4.75
1.5
1
5.49
1.8
1
6.19
2.1
0.5
6.98
2.5
0.5
7.87
3.3
0.5
8.87
5
0.25
10 & greater value
0.8
1
MFR_MODE_SETTINGS (C8h)
•
•
•
•
CCM(0)
This manufacture specific command sets
CCM behavior,
Enable/Disable VSET pin,
Turn on/off LS FET at OV_WARN and
Gain calibration for input current reporting (READ_IIN)
This is a one byte command. The contents of this register
can be stored to nonvolatile memory using the
STORE_USER_ALL command. The below table shows all
the options allowed
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46
FAN251015
MFR_PMBUS_BASE (C9h)
MFR_ID2 (CAh)
This manufacture specific command sets part of the base
part of the PMBUS address. ADDR pin resistor (with up to 1%
tolerance) is used to set the PMBUS address of the device.
This is a one byte command. The contents of this register
can be stored to nonvolatile memory using the
STORE_USER_ALL command.
The table shows the mapping from ADDR pin resistors to
the selected PMBUS address. The base part of the address
comes from the MFR_PMBUS_BASE command. Base
address is added to the offset from the below table to
generate the 7 bit PMBUS address used for all the PMBUS
communication.
To change the base address, use the current base address
(factory default is 7’10h) to write the new/desired address to
this register. All subsequent data transactions use the revised
base address.
When an ARA command is received by the FAN2510XY,
it responds by sending its slave address. This functionality
is supported only when the base address is 7’40h or greater.
The FAN2510XY should not be used with a base address
less than 40h in systems employing ARA functionality, as it
will result in an incorrect device response to the system.
This manufacture specific command provides an option
for customers who need 16 bits of manufacture’s ID (name,
abbreviation or symbol that identifies the unit’s
manufacturer). This is a two byte command accessible for
read and write. The contents of this register can be stored to
nonvolatile memory using the STORE_USER_ALL
command.
ADDR Resistor
Value (kW)
PMBUS Device Fault Management Clearing Warning or
Fault Bits
All of the warning or fault bits (except PGOOD fault) set
in the status registers remain set , even if the fault or warning
condition is removed or corrected until one of the following
occur:
• Bit is individually cleared
• Device receives a CLEAR_FAULTS command
• The output is commanded through the ENABLE pin, the
OPERATION command, or the combined action of
ENABLE pin and OPERATION command to turn OFF
and then turn back on, or
• Bias power is removed from the PMBUS device. This
means that VDD or VIN supply collapses below the level
The two exceptions to the above rule that status bits
remain set are the OFF and POWERGOOD# bits. These bits
always reflect the current state of the device and the
POWER_GOOD signal.
Offset Address (h) PMBUS Address (h)
0 (short)
−
0F
0.845
00
Base+00
1.3
01
Base+01
1.78
02
Base+02
2.32
03
Base+03
2.87
04
Base+04
3.48
05
Base+05
4.12
06
Base+06
4.75
07
Base+07
5.49
08
Base+08
6.19
09
Base+09
6.98
0A
Base+0A
7.87
0B
Base+0B
8.87
0C
Base+0C
10
0D
Base+0D
≥12.4
−
0F
Clearing Individual Bits
Any or all the bits in any status register except
STATUS_BYTE and STATUS_WORD can be directly
cleared by issuing the status command with one data byte
written. The data byte is a binary value. A 1 in any bit
position indicates that bit is to be cleared, if set, and
unchanged if not set. Examples of data bytes:
• 00010000b indicates that bit[4] is to be cleared and all
other bits are to be unchanged,
• 01100010b indicates that bits[6],[5] and [11] are to be
cleared and all other bits are to be unchanged
• 11111111b, or FFh, indicates all bits are to be cleared
Clearing Bits in the STATUS_BYTE and
STATUS_WORD
Most bits in the STATUS_BYTE and STATUS_WORD
are cleared by clearing the bit or all of the bits that cause the
bit in STATUS_BYTE or STATUS_WORD to be set. In
general, STATUS_BYTE and STATUS_WORD are the
logical OR of the bits in a lower level status register. Figure
10 shows this concept.
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FAN251015
Status
Bit output over voltage fault
Bit output over voltage warning
Bit output under voltage
warning
Bit output under voltage fault
OR
Gate
Bitoutput max or min warning
STATUS_WORD(Upper Byte)
Bit VOUT
Bit ton max fault
Bit ton max warning
Bit Not Supported
Figure 13. Conceptual View of Creating Bits in STATUS_BYTE and STATUS_WORD
The output of the latch passes through a gate controlled by
the corresponding SMBALERT_MASK bit. If this bit is set,
the output of the latch is blocked from driving the
SMBALERT# circuit. If the SMBALERT_MASK bit is
cleared, the latch output is allowed to pass and drive the
SMBALERT# circuit. Figure 14 below gives a conceptual
illustration of how the SMBALERT# signal is generated.
When the SMBALERT# circuit detects the rising edge of
the latch output it asserts the SMBALERT# signal output
goes low).
The SMBALERT# signal remains asserted until is
cleared. It is cleared when the device successfully transmits
its address in response to receiving the Alert Response
Address. It is also cleared by a CLEAR_FAULTS command.
The latch can also be cleared by writing a 1 to corresponding
bit in the status register.
Conceptually the bit clearing commands act as pulses,
driving the reset pin on the latch only momentarily. This
means that if the vent is ongoing (the event detector is still
active) the output latch will immediately set again. As
described above, this will cause the SMBALERT# to
reassert if it had been previously cleared (and the
SMBALERT_MASK bit is not set). This also means that
host won’t be able to see the status bit get cleared.
For example, if the VOUT_OV_FAULT bit is
STATUS_VOUT register is set, then the VOUT bit in the
STATUS_WORD
is
also
set.
When
the
VOUT_OCV_FAULT bit in the STATUS_VOUT register is
cleared, the VOUT bit in the STATUS_WORD will be
cleared at the same time provided no other bits in the
STATUS_VOUT are set.
OFF and POWERGOOD# bits cannot be cleared as they
always reflect the current state of the device.
Immediate Reassertion after Clearing if Condition is
still present
If the warning or fault condition is present when the bit is
cleared, the bit is immediately set again. The ALERTB# will
also be asserted again immediately after the status bit is
cleared. The SMBALERT_MASK command can be used to
prevent this behavior.
Conceptual View of How Status Bits and ALERTB#
Work
When some warning or fault event is detected a latch is set.
The output of this latch becomes the status bit in one of the
lower level status register (such as STATUS_VOUT). The
latch output may also be used, either by itself or OR’ed with
other status bits, to create the corresponding bit in
STATUS_BYTE or STATUS_WORD and to affect
SMBALERT#.
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48
FAN251015
Other status bits that can set the
same bit in
STATUS_BYTE/STATUS_WORD
Bit in
STATUS_BYTE/STATUS
_WORD Register
Event Detector
CLEAR_FAULTS Output
SET
Q
LATCH
Bit in STATUS_X
Register
CLR
Write 1 to Status
register bit
SMBAL
ERT#
Circuit
SMBALERT
_MASK Bit
SMBALERT
#
CLEAR_F
AULTS
Device Address
sent in response
to the Alert
Response
Address while
SMBALERT#
asserted
Figure 14. Conceptual Schematic of Status Bits and SMBALERT#
PCB Layout Guideline
Place de−coupling capacitors for PVCC and VCC
adjacent to their respective IC pins and connect with widest
possible trace on the top layer. The other side of the bypass
caps may be connected with vias to the system GND plane,
and PGND.
It is recommended to create a location for a series boot
resistor (RBOOT), in series with CBOOT, between the BOOT
and PH pins. A low value (