FAN3100CSX

Single 2A High-Speed, Low-Side Gate Driver FAN3100T, FAN3100C Description The FAN3100 2 A gate driver is designed to drive an N−channel enhancement−mode MOSFET in low−side switching applications by providing high peak current pulses during the short switching intervals. The driver is available with either TTL (FAN3100T) or CMOS (FAN3100C) input thresholds. Internal circuitry provides an under−voltage lockout function by holding the output LOW until the supply voltage is within the operating range. The FAN3100 delivers fast MOSFET switching performance, which helps maximize efficiency in high−frequency power converter designs. FAN3100 drivers incorporate MillerDrive t architecture for the final output stage. This bipolar−MOSFET combination provides high peak current during the Miller plateau stage of the MOSFET turn−on / turn−off process to minimize switching loss, while providing rail−to−rail voltage swing and reverse current capability. The FAN3100 also offers dual inputs that can be configured to operate in non−inverting or inverting mode and allow implementation of an enable function. If one or both inputs are left unconnected, internal resistors bias the inputs such that the output is pulled LOW to hold the power MOSFET off. The FAN3100 is available in a lead−free finish, 2x2 mm, 6−lead, Molded Leadless Package (MLP) for the smallest size with excellent thermal performance; or industry−standard, 5−pin, SOT23. www.onsemi.com WDFN6 2x2, 065P CASE 511CY PIN ASSIGNMENT • • • • • • • • 3 A Peak Sink/Source at VDD = 12 V 4.5 to 18 V Operating Range 2.5 A Sink/1.8 A Source at VOUT = 6 V Dual−Logic Inputs Allow Configuration as Non−Inverting or Inverting with Enable Function Internal Resistors Turn Driver Off If No Inputs 13 ns Typical Rise Time and 9 ns Typical Fall−Time with 1 nF Load Choice of TTL or CMOS Input Thresholds MillerDrive Technology Typical Propagation Delay Time Under 20 ns with Input Falling or Rising 6−Lead, 2x2 mm MLP or 5−Pin, SOT23 Packages Rated from –40°C to 125°C Ambient These Devices are Pb−Free and Halogen Free Applications • • • • • © Semiconductor Components Industries, LLC, 2007 February, 2021 − Rev. 3 1 6 IN− AGND 2 5 PGND VDD 3 4 OUT VDD 1 GND 2 IN+ 3 5 OUT 4 IN* SOT23−5 (Top View) MARKING DIAGRAM &E&E&Y &O100X&C &.&O&E&V &E &Y &O 100X &C &. &V Switch−Mode Power Supplies (SMPS) High−Efficiency MOSFET Switching Synchronous Rectifier Circuits DC−to−DC Converters Motor Control IN+ 6−Lead MLP (Top View) Features • • • • SOT23−5 CASE 527AH = Designates Space = Binary Calendar Year Coding Scheme = Plant Code identifier = Device Specific Code X = T or C = Single digit Die Run Code = Pin One Dot = Eight−Week Binary Datecoding Scheme ORDERING INFORMATION See detailed ordering and shipping information on page 17 of this data sheet. 1 Publication Order Number: FAN3100T/D FAN3100T, FAN3100C BLOCK DIAGRAMS THERMAL CHARACTERISTICS (Note 1) QJL (Note 2) QJT (Note 3) QJA (Note 4) YJB (Note 5) YJT (Note 6) Unit 6−Lead, 2x2 mm Molded Leadless Package (MLP) 2.7 133 58 2.8 42 °C/W SOT23, 5−Lead 56 99 157 51 5 °C/W Package 1. Estimates derived from thermal simulation; actual values depend on the application. 2. Theta_JL (QJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. 3. Theta_JT (QJT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top−side heatsink. 4. Theta_JA (QJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51−2, JESD51−5, and JESD51−7, as appropriate. 5. Psi_JB (YJB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 4. For the MLP−6 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOT23−5 package, the board reference is defined as the PCB copper adjacent to pin 2. 6. Psi_JT (YJT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 4. PIN DEFINITIONS SOT23 Pin Number MLP Pin Number Name 1 3 VDD 2 AGND ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 2 GND Description Supply Voltage. Provides power to the IC. Analog ground for input signals (MLP only). Connect to PGND underneath the IC. Ground (SOT−23 only). Common ground reference for input and output circuits. 3 1 IN+ Non−Inverting Input. Connect to VDD to enable output. 4 6 IN− Inverting Input. Connect to AGND or PGND to enable output. 5 4 OUT Gate Drive Output: Held LOW unless required inputs are present and VDD is above UVLO threshold. Pad P1 5 PGND Thermal Pad (MLP only). Exposed metal on the bottom of the package, which is electrically connected to pin 5. Power Ground (MLP only). For output drive circuit; separates switching noise from inputs. OUTPUT LOGIC IN+ IN− OUT 0 (Note 7) 0 0 0 (Note 7) 1 (Note 7) 0 1 0 1 1 1 (Note 7) 0 7. Default input signal if no external connection is made. www.onsemi.com 2 FAN3100T, FAN3100C BLOCK DIAGRAMS 1 VDD 5 OUT 2 GND 3 VDD 4 OUT 5 PGND UVLO 100 kW IN+ VDD_OK 3 100 kW 100 kW IN− 4 Figure 1. Simplified Block Diagram (SOT23 Pin−out) UVLO 100 kW IN+ VDD_OK 1 100 kW 100 kW IN− AGND 6 2 0.4 W Figure 2. Simplified Block Diagram (MLP Pin−out) www.onsemi.com 3 FAN3100T, FAN3100C ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Unit −0.3 20.0 V Voltage on IN+ and IN− to GND, AGND or PGND GND −0.3 VDD + 0.3 V Voltage on OUT to GND, AGND or PGND GND −0.3 VDD + 0.3 V GND −2 VDD + 0.3 V +260 °C VDD VDD to GND VIN VOUT Repetitive Voltage on OUT to GND, AGND or PGND (TPULSE < 300 ns) (Note 8) TL Lead Soldering Temperature (10 Seconds) TJ Junction Temperature −55 +150 °C TSTG Storage Temperature −65 +150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 8. Restricted by thermal dissipation. (< Max TJ) RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VDD Supply Voltage Range 4.5 18.0 V VIN Input Voltage IN+, IN− 0 VDD V TA Operating Ambient Temperature −40 +125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 12 V, TJ = −40°C to +125°C unless otherwise noted. Currents are defined as positive into the device and negative out of the device.) Symbol Parameter Test Condition Min Typ Max Unit 18.0 V SUPPLY VDD Operating Range IDD Supply Current Inputs/EN Not Connected 4.5 FAN3100C (Note 9) 0.20 0.35 mA FAN3100T 0.50 0.80 mA VON Turn−On Voltage 3.5 3.9 4.3 V VOFF Turn−Off Voltage 3.3 3.7 4.1 V INPUTS (FAN3100T) VINL_T IN+, IN− Logic Low−Voltage, Maximum VINH_T IN+, IN− Logic High−Voltage, Minimum 0.8 V 2.0 V IIN+ Non−inverting Input IN from 0 to VDD −1 175 mA IIN− Inverting Input IN from 0 to VDD −175 1 mA 0.8 V VHYS IN+, IN− Logic Hysteresis Voltage 0.2 0.4 INPUTS (FAN3100C) VINL_C IN+, IN− Logic Low Voltage VINH_C IN+, IN− Logic High Voltage 30 %VDD 70 %VDD IINL IN Current, Low IN from 0 to VDD −1 175 mA IINH IN Current, High IN from 0 to VDD −175 1 mA VHYS_C IN+, IN− Logic Hysteresis Voltage 17 %VDD OUT Current, Mid−Voltage, Sinking (Note 10) OUT at VDD/2, CLOAD = 0.1 mF, f = 1 kHz 2.5 A OUTPUT ISINK www.onsemi.com 4 FAN3100T, FAN3100C ELECTRICAL CHARACTERISTICS (VDD = 12 V, TJ = −40°C to +125°C unless otherwise noted. Currents are defined as positive into the device and negative out of the device.) Symbol Parameter Test Condition Min Typ Max Unit OUTPUT ISOURCE OUT Current, Mid−Voltage, Sourcing (Note 10) OUT at VDD/2, CLOAD = 0.1 mF, f = 1 kHz IPK_SINK OUT Current, Peak, Sinking (Note 10) IPK_SOURCE OUT Current, Peak, Sourcing (Note 10) −1.8 A CLOAD = 0.1 mF, f = 1kHz 3 A CLOAD = 0.1 mF, f = 1 kHz −3 A 13 20 ns tRISE Output Rise Time (Note 11) CLOAD = 1000 pF tFALL Output Fall Time (Note 11) CLOAD = 1000 pF 9 14 ns tD1, tD2 Output Prop. Delay, CMOS Inputs (Note 11) 0−12 VIN, 1 V/ns Slew Rate 7 15 28 ns tD1, tD2 Output Prop. Delay, TTL Inputs (Note 11) 0−5 VIN, 1 V/ns Slew Rate 9 16 30 ns IRVS Output Reverse Current Withstand (Note 10) 500 9. Lower supply current due to inactive TTL circuitry. 10. Not tested in production. 11. See Timing Diagrams of Figure 3 and Figure 4. TIMING DIAGRAMS 90% 90% Output Output 10% Input 10% VINH Input VINL tD1 tD2 tRISE tFALL VINH VINL tD1 tFALL Figure 3. Non−Inverting tD2 tRISE Figure 4. Inverting www.onsemi.com 5 mA FAN3100T, FAN3100C TYPICAL PERFORMANCE CHARACTERISTICS (Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) Figure 5. IDD (Static) vs. Supply Voltage Figure 6. IDD (Static) vs. Supply Voltage Figure 7. IDD (No−Load) vs. Frequency Figure 8. IDD (No−Load) vs. Frequency Figure 10. IDD (1 nF Load) vs. Frequency Figure 9. IDD (1 nF Load) vs. Frequency www.onsemi.com 6 FAN3100T, FAN3100C TYPICAL PERFORMANCE CHARACTERISTICS (continued) (Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) Figure 11. IDD (Static) vs. Temperature Figure 12. IDD (Static) vs. Temperature Figure 13. Input Thresholds vs. Supply Voltage Figure 14. Input Thresholds vs. Supply Voltage Figure 15. Input Thresholds % vs. Supply Voltage www.onsemi.com 7 FAN3100T, FAN3100C TYPICAL PERFORMANCE CHARACTERISTICS (continued) (Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) Figure 17. TTL Input Thresholds vs. Temperature Figure 16. CMOS Input Thresholds vs. Temperature Figure 18. UVLO Thresholds vs. Temperature Figure 19. UVLO Hysteresis vs. Temperature Figure 21. Propagation Delay vs. Supply Voltage Figure 20. Propagation Delay vs. Supply Voltage www.onsemi.com 8 FAN3100T, FAN3100C TYPICAL PERFORMANCE CHARACTERISTICS (continued) (Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) Figure 23. Propagation Delay vs. Supply Voltage Figure 22. Propagation Delay vs. Supply Voltage Figure 24. Propagation Delay vs. Temperature Figure 25. Propagation Delay vs. Temperature Figure 26. Propagation Delay vs. Temperature Figure 27. Propagation Delay vs. Temperature www.onsemi.com 9 FAN3100T, FAN3100C TYPICAL PERFORMANCE CHARACTERISTICS (continued) (Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) Figure 29. Rise Time vs. Supply Voltage Figure 28. Fall Time vs. Supply Voltage Figure 30. Rise and Fall Time vs. Temperature Figure 32. Rise / Fall Waveforms with 10 nF Load Figure 31. Rise / Fall Waveforms with 1 nF Load www.onsemi.com 10 FAN3100T, FAN3100C TYPICAL PERFORMANCE CHARACTERISTICS (continued) (Typical characteristics are provided at 25°C and VDD = 12 V unless otherwise noted) Figure 33. Quasi−Static Source Current with VDD = 12 V Figure 34. Quasi−Static Sink Current with VDD = 12 V Figure 35. Quasi−Static Source Current with VDD = 8 V Figure 36. Quasi−Static Sink Current with VDD = 8 V VDD 4.7 mF Ceramic 470 mF Al. El. Current Probe LECROY AP015 IOUT IN 1 kHz 1 mF Ceramic VOUT CLOAD 1 mF Figure 37. Quasi−Static IOUT / VOUT Test Circuit www.onsemi.com 11 FAN3100T, FAN3100C APPLICATIONS INFORMATION Input Threshold situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is switched on. The output pin slew rate is determined by VDD voltage and the load on the output. It is not user adjustable, but if a slower rise or fall time at the MOSFET gate is needed, a series resistor can be added. The FAN3100 offers TTL or CMOS input thresholds. In the FAN3100T, the input thresholds meet industry−standard TTL logic thresholds, independent of the VDD voltage, and there is a hysteresis voltage of approximately 0.4 V. These levels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2 V is considered logic HIGH. The driving signal for the TTL inputs should have fast rising and falling edges with a slew rate of 6 V/ms or faster, so the rise time from 0 to 3.3 V should be 550 ns or less. With reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. In the FAN3100C, the logic input thresholds are dependent on the VDD level and, with VDD of 12 V, the logic rising edge threshold is approximately 55% of VDD and the input falling edge threshold is approximately 38% of VDD. The CMOS input configuration offers a hysteresis voltage of approximately 17% of VDD. The CMOS inputs can be used with relatively slow edges (approaching DC) if good decoupling and bypass techniques are incorporated in the system design to prevent noise from violating the input voltage hysteresis window. This allows setting precise timing intervals by fitting an R−C circuit between the controlling signal and the IN pin of the driver. The slow rising edge at the IN pin of the driver introduces a delay between the controlling signal and the OUT pin of the driver. VDD Input stage VOUT Figure 38. MillerDrivet Output Architecture Under−Voltage Lockout In the IDD (static) typical performance graphs (Figure 5 − Figure 6 and Figure 11 − Figure 12), the curve is produced with all inputs floating (OUT is LOW) and indicates the lowest static IDD current for the tested configuration. For other states, additional current flows through the 100 kW resistors on the inputs and outputs shown in the block diagrams (Figure 1 − Figure 2). In these cases, the actual static IDD current is the value obtained from the curves plus this additional current. The FAN3100 start−up logic is optimized to drive ground referenced N−channel MOSFETs with a under−voltage lockout (UVLO) function to ensure that the IC starts up in an orderly fashion. When VDD is rising, yet below the 3.9 V operational level, this circuit holds the output LOW, regardless of the status of the input pins. After the part is active, the supply voltage must drop 0.2 V before the part shuts down. This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power switching. This configuration is not suitable for driving high−side P−channel MOSFETs because the low output voltage of the driver would turn the P−channel MOSFET on with VDD below 3.9 V. MillerDrivet Gate Drive Technology VDD Bypass Capacitor Guidelines Static Supply Current FAN3100 drivers incorporate the MillerDrive architecture shown in Figure 38 for the output stage, a combination of bipolar and MOS devices capable of providing large currents over a wide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT swings between 1/3 to 2/3 VDD and the MOS devices pull the output to the high or low rail. The purpose of the MillerDrive architecture is to speed up switching by providing the highest current during the Miller plateau region when the gate−drain capacitance of the MOSFET is being charged or discharged as part of the turn−on / turn−off process. For applications that have zero voltage switching during the MOSFET turn−on or turn−off interval, the driver supplies high peak current for fast switching even though the Miller plateau is not present. This To enable this IC to turn a power device on quickly, a local, high−frequency, bypass capacitor CBYP with low ESR and ESL should be connected between the VDD and GND pins with minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10 mF to 47 mF often found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the VDD supply ≤ 5%. Often this is achieved with a value ≥ 20 times the equivalent load capacitance CEQV, defined here as Qgate/VDD. Ceramic capacitors of 0.1 mF to 1 mF or larger are common choices, as are dielectrics, such as X5R and X7R, which have good temperature characteristics and high pulse current capability. www.onsemi.com 12 FAN3100T, FAN3100C If circuit noise affects normal operation, the value of CBYP may be increased to 50−100 times the CEQV, or CBYP may be split into two capacitors. One should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1−10 nF, mounted closest to the VDD and GND pins to carry the higher−frequency components of the current pulses. VDD VDS CBYP FAN3100 PWM Layout and Connection Guidelines The FAN3100 incorporates fast−reacting input circuits, short propagation delays, and powerful output stages capable of delivering current peaks over 2 A to facilitate voltage transition times from under 10 ns to over 100 ns. The following layout and connection guidelines are strongly recommended: • Keep high−current output and power ground paths separate from logic input signals and signal ground paths. This is especially critical when dealing with TTL−level logic thresholds. • Keep the driver as close to the load as possible to minimize the length of high−current traces. This reduces the series inductance to improve high−speed switching, while reducing the loop area that can radiate EMI to the driver inputs and other surrounding circuitry. • The FAN3100 is available in two packages with slightly different pinouts, offering similar performance. In the 6−pin MLP package, Pin 2 is internally connected to the input analog ground and should be connected to power ground, Pin 5, through a short direct path underneath the IC. In the 5−pin SOT23, the internal analog and power ground connections are made through separate, individual bond wires to Pin 2, which should be used as the common ground point for power and control signals. • Many high−speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output re−triggering. These effects can be especially obvious if the circuit is tested in breadboard or non−optimal circuit layouts with long input, enable, or output leads. For best results, make connections to all pins as short and direct as possible. • The turn−on and turn−off current paths should be minimized as discussed in the following sections. Figure 39 shows the pulsed gate drive current path when the gate driver is supplying gate charge to turn the MOSFET on. The current is supplied from the local bypass capacitor, CBYP, and flows through the driver to the MOSFET gate and to ground. To reach the high peak currents possible, the resistance and inductance in the path should be minimized. The localized CBYP acts to contain the high peak current pulses within this driver−MOSFET circuit, preventing them from disturbing the sensitive analog circuitry in the PWM controller. Figure 39. Current Path for MOSFET Turn−On Figure 40 shows the current path when the gate driver turns the MOSFET off. Ideally, the driver shunts the current directly to the source of the MOSFET in a small circuit loop. For fast turn−off times, the resistance and inductance in this path should be minimized. VDS VDD CBYP FAN3100 PWM Figure 40. Current Path for MOSFET Turn−Off Truth Table of Logic Operation The truth table indicates the operational states using the dual−input configuration. In a non−inverting driver configuration, the IN− pin should be a logic LOW signal. If the IN− pin is connected to logic HIGH, a disable function is realized, and the driver output remains LOW regardless of the state of the IN+ pin. Table 1. FAN3100 TRUTH TABLE IN+ IN− OUT 0 0 0 0 1 0 1 0 1 1 1 0 In the non−inverting driver configuration in Figure 41, the IN− pin is tied to ground and the input signal (PWM) is applied to IN+ pin. The IN− pin can be connected to logic HIGH to disable the driver and the output remains LOW, regardless of the state of the IN+ pin. www.onsemi.com 13 FAN3100T, FAN3100C and the input signal applied to IN–, the OUT pulses are inverted with respect to the input. At power up, the inverted output remains LOW until the VDD voltage reaches the turn−on threshold, then it follows the input with inverted phase. VDD PWM IN+ IN− FAN 3100 OUT GND Turn−on Threshold VDD Figure 41. Dual−Input Driver Enabled, Non−Inverting Configuration IN− In the inverting driver application shown in Figure 42, the IN+ pin is tied HIGH. Pulling the IN+ pin to GND forces the output LOW, regardless of the state of the IN− pin. IN+ (VDD) VDD OUT Figure 44. Inverting Start−Up Waveforms IN+ PWM IN− FAN3100 OUT GND Thermal Guidelines Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits. The total power dissipation in a gate driver is the sum of two components; PGATE and PDYNAMIC: Figure 42. Dual−Input Driver Enabled, Inverting Configuration Operational Waveforms At power up, the driver output remains LOW until the VDD voltage reaches the turn−on threshold. The magnitude of the OUT pulses rises with VDD until steady−state VDD is reached. The non−inverting operation illustrated in Figure 43 shows that the output remains LOW until the UVLO threshold is reached, then the output is in−phase with the input. VDD P TOTAL + P GATE ) P DYNAMIC (eq. 1) Gate Driving Loss: The most significant power loss results from supplying gate current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MOSFET at a specified gate−source voltage, VGS, with gate charge, QG, at switching frequency, fSW, is determined by: Turn−on Threshold P GATE + Q G @ V GS @ f SW IN− (eq. 2) Dynamic Pre−drive / Shoot−through Current: A power loss resulting from internal current consumption under dynamic operating conditions, including pin pull−up / pull−down resistors, can be obtained using the IDD (no−Load) vs. Frequency graphs in Typical Performance Characteristics to determine the current IDYNAMIC drawn from VDD under actual operating conditions: IN+ OUT Figure 43. Non−Inverting Start−Up Waveforms P DYNAMIC + I DYNAMIC @ V DD For the inverting configuration of Figure 42, start−up waveforms are shown in Figure 44. With IN+ tied to VDD www.onsemi.com 14 (eq. 3) FAN3100T, FAN3100C Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming YJB was determined for a similar thermal design (heat sinking and air flow): T J + P TOTAL @ Y JB ) T B where: TJ The 5−pin SOT23 has a junction−to−lead thermal characterization parameter YJB = 51°C/W. In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along with airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prevented from exceeding the maximum rating of 150°C; with 80% derating, TJ would be limited to 120°C. Rearranging Equation 4 determines the board temperature required to maintain the junction temperature below 120°C: (eq. 4) = driver junction temperature; = (psi) thermal; YJB characterization parameter relating temperature rise to total power dissipation; TB = board temperature in location defined in the Thermal Characteristics table T B,MAX + T J * P TOTAL @ Y JB T B,MAX + 120°C * 0.24W @ 51°CńW + 108°C (eq. 9) For comparison purposes, replace the 5−pin SOT23 used in the previous example with the 6−pin MLP package with YJB = 2.8°C/W. The 6−pin MLP package can operate at a PCB temperature of 119°C, while maintaining the junction temperature below 120°C. This illustrates that the physically smaller MLP package with thermal pad offers a more conductive path to remove the heat from the driver. Consider the tradeoffs between reducing overall circuit size with junction temperature reduction for increased reliability. In a typical forward converter application with 48 V input, as shown in Figure 45, the FDS2672 would be a potential MOSFET selection. The typical gate charge would be 32 nC with VGS = VDD = 10 V. Using a TTL input driver at a switching frequency of 500 kHz, the total power dissipation can be calculated as: P GATE + 32nC @ 10V @ 500kHz + 0.160W (eq. 5) P DYNAMIC + 8mA @ 10V + 0.080W (eq. 6) P TOTAL + 0.24W (eq. 7) (eq. 8) www.onsemi.com 15 FAN3100T, FAN3100C TYPICAL APPLICATION DIAGRAMS VIN ENABLE Active LOW FAN3100 PWM IN+ AGND VDD IN− 1 6 2 5 3 4 PGND OUT Figure 45. Forward Converter, Primary−Side Gate Drive (MLP Package Show) Q1 VIN T2 T1 D1 VDD D2 FAN3100 Q2 CC PWM VSEC 0.1 μF Figure 46. Driver for Two−Transistor Forward Converter Gate Transformer VIN Q1 T1 D1 PWM Control/ Isolation L VSEC D2 VOUT Q5 Q3 Q2 SR VDRV ISOLATION FAN3100 Figure 47. Secondary Synchronous Rectifier Driver VDD R IN FAN3100C OUT C Delay IN OUT Figure 48. Programmable Delay Using CMOS Input www.onsemi.com 16 FAN3100T, FAN3100C ORDERING INFORMATION Input Threshold Package Shipping† FAN3100CMPX CMOS 6−Lead, 2x2 mm MLP 3,000 / Tape & Reel FAN3100CSX CMOS 5−Pin SOT23 3,000 / Tape & Reel FAN3100TMPX TTL 6−Lead, 2x2 mm MLP 3,000 / Tape & Reel FAN3100TSX TTL 5−Pin SOT23 3,000 / Tape & Reel Part Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Table 2. RELATED PRODUCTS Part Number Type Gate Drive (Note 12) (Sink/Src) Input Threshold Logic Package FAN3100T Single 2 A +2.5 A/−1.8 A TTL Single Channel of Two−Input/One−Output SOT23−5, MLP6 FAN3100C Single 2 A +2.5 A/−1.8A CMOS Single Channel of Two−Input/One−Output SOT23−5, MLP6 FAN3226C Dual 2 A +2.4 A/−1.6 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3226T Dual 2 A +2.4 A/−1.6 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3227C Dual 2 A +2.4 A/−1.6 A CMOS Dual Non−Inverting Channels + Dual Enable SOIC8, MLP8 FAN3227T Dual 2 A +2.4 A/−1.6 A TTL Dual Non−Inverting Channels + Dual Enable SOIC8, MLP8 FAN3228C Dual 2 A +2.4 A/−1.6 A CMOS Dual Channels of Two−Input/One−Output, Pin Config. 1 SOIC8, MLP8 FAN3228T Dual 2 A +2.4 A/−1.6 A TTL Dual Channels of Two−Input/One−Output, Pin Config. 1 SOIC8, MLP8 FAN3229C Dual 2 A +2.4 A/−1.6 A CMOS Dual Channels of Two−Input/One−Output, Pin Config. 2 SOIC8, MLP8 FAN3229T Dual 2 A +2.4 A/−1.6 A TTL Dual Channels of Two−Input/One−Output, Pin Config. 2 SOIC8, MLP8 FAN3223C Dual 4 A +4.3 A/−2.8 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3223T Dual 4 A +4.3 A/−2.8 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3224C Dual 4 A +4.3 A/−2.8 A CMOS Dual Non−Inverting Channels + Dual Enable SOIC8, MLP8 FAN3224T Dual 4 A +4.3 A/−2.8 A TTL Dual Non−Inverting Channels + Dual Enable SOIC8, MLP8 FAN3225C Dual 4 A +4.3 A/−2.8 A CMOS Dual Channels of Two−Input/One−Output SOIC8, MLP8 FAN3225T Dual 4 A +4.3 A/−2.8 A TTL Dual Channels of Two−Input/One−Output SOIC8, MLP8 12. Typical currents with OUT at 6 V and VDD = 12 V. MillerDrive is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 17 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFN6 2x2, 0.65P CASE 511CY ISSUE O 0.05 C 2.0 DATE 31 JUL 2016 A 1.72 2X 1.68 B 6 4 0.15 2.0 1.21 0.90 2.25 0.52(6X) 0.05 PIN#1 IDENT TOP VIEW C 1 2X 3 0.42(6X) 0.65 RECOMMENDED LAND PATTERN 0.75±0.05 0.10 C 0.20±0.05 0.08 NOTES: C SIDE VIEW 0.025±0.025 C A. PACKAGE DOES NOT FULLY CONFORM TO JEDEC MO−229 REGISTRATION SEATING PLANE B. DIMENSIONS ARE IN MILLIMETERS. 2.00±0.05 C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009. 1.40±0.05 (0.70) (0.20)4X PIN #1 IDENT 1 0.32±0.05 D. LAND PATTERN RECOMMENDATION IS EXISTING INDUSTRY LAND PATTERN. 3 (0.40) (6X) 0.80±0.05 (0.60) 6 4 0.30±0.05 0.65 1.30 BOTTOM VIEW DOCUMENT NUMBER: DESCRIPTION: 98AON13613G WDFN6 2X2, 0.65P (6X) 0.10 C 0.05 C A B Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOT−23, 5 Lead CASE 527AH−01 ISSUE O D DATE 19 DEC 2008 SYMBOL E1 MIN NOM A 0.90 1.45 A1 0.00 0.15 A2 0.90 b 0.30 0.50 c 0.08 0.22 E 1.15 D 2.90 BSC E 2.80 BSC E1 1.60 BSC L 1.30 0.95 BSC e e 0.45 0.30 L1 PIN #1 IDENTIFICATION MAX 0.60 0.60 REF L2 0.25 REF θ 0° 4° 8° θ1 5° 10° 15° θ2 5° 10° 15° TOP VIEW θ1 A2 A b θ2 A1 SIDE VIEW θ L1 L2 L c END VIEW Notes: (1) All dimensions in millimeters. Angles in degrees. (2) Complies with JEDEC standard MO-178. DOCUMENT NUMBER: DESCRIPTION: 98AON34320E SOT−23, 5 LEAD Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Email Requests to: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com ◊ TECHNICAL SUPPORT North American Technical Support: Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910 www.onsemi.com 1 Europe, Middle East and Africa Technical Support: Phone: 00421 33 790 2910 For additional information, please contact your local Sales Representative